Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI

Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI Young-Gi Song, Hae-Seong Jeong, Jae-Ha Kim, Sung-Yun Cho, Hyeok-Jung Kwon This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8486209/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 9 You are reading this latest preprint version Abstract The high-power RF system at the Korea Multi-purpose Accelerator Complex (KOMAC) operates at 350 MHz with a peak power of 1.6 MW, a pulse width of 1.5 ms. The RF duty factors of 24% and 9% for the 20 MeV and 100 MeV linac sections, respectively. Stable accelerator operation requires strict RF amplitude and phase stability within 1% and 1°, as well as cavity resonance detuning control within 10% of the RF bandwidth. To satisfy these demanding operational conditions, a digital high-power RF interlock system has been developed. The system supports remote and automatic threshold reconfiguration and is fully integrated into the EPICS control environment for centralized monitoring and operation. A Zynq SoC-based architecture digitizes forward, reverse, and pickup signals using ADCs, converts them into calibrated power values, and enables waveform and power monitoring during normal operation. In addition, a built-in postmortem function records pre- and post-interlock data, allowing operators to identify fault mechanisms and root causes with high temporal resolution. This paper presents the design and implementation of an RF protection system optimized for the 100 MeV proton linac at KOMAC, which consists of nine klystrons, nine circulators, and thirteen RF windows. Compared with the conventional analog interlock system, the proposed digital platform significantly enhances RF stability, fault diagnostics, and operational flexibility. RF VSWR ZYNQ EPICS Interlock Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 1. INTRODUCTION The Korea Multi-purpose Accelerator Complex (KOMAC) operates a 100 MeV proton linear accelerator that supplies high-intensity proton beams for neutron science, isotope production, and related applications [ 1 ]. The RF system comprises nine 350 MHz klystron amplifiers, each capable of delivering up to 1.6 MW of peak power, together with circulators and RF windows that ensure efficient RF transmission and protect accelerator components. For stable beam acceleration, RF amplitude and phase must be controlled within 1% and 1°, respectively, under high-power and high-duty operating conditions. Conventional RF interlock systems at KOMAC were implemented using analog comparators and fixed hardware thresholds. While effective for basic protection, these systems suffered from limited configurability, complex maintenance, and insufficient fault traceability [ 2 ][ 3 ]. In particular, threshold adjustments required manual intervention, and post-event analysis relied heavily on external oscilloscopes, making systematic fault diagnosis difficult during routine high-duty operation. To address these limitations, a digital RF interlock system based on a Zynq System-on-Chip (SoC) platform has been developed [ 4 ]. Forward, reverse, and pickup RF signals are digitized by 16-bit ADCs at 2 MS/s and processed in FPGA logic to calculate RF power, Voltage Standing Wave Ratio (VSWR), and arc detection in real time. Interlock decisions are executed in hardware with fixed latency, while the embedded ARM processor provides EPICS-based remote control, threshold configuration, and data acquisition functions [ 5 ]. Figure 1 illustrates the overall block diagram of the KOMAC high-power RF system. The section enclosed by the red dashed line represents the legacy analog interlock system and external oscilloscope used for RF monitoring, both of which are functionally replaced by the proposed digital interlock platform. The new system improves operational flexibility and system integration by enabling centralized monitoring and control within the accelerator control environment. In current KOMAC operation, both the modulator and high-power RF system employ automatic start-up logic. Accordingly, interlock signals generated by the digital RF interlock system are rapidly distributed to the automatic start-up system, the Machine Protection System (MPS) [ 6 ], and the RF switch at the LLRF analog stage. This integrated protection architecture enhances system reliability and operational transparency during high-power RF operation. By replacing the legacy analog interlock with a fully digital platform, the proposed system provides deterministic protection, improved maintainability, and enhanced diagnostic capability. This paper presents the design, implementation, and experimental verification of the developed RF interlock system for the KOMAC 100 MeV linac. 2. SYSTEM DESIGN 2.1 Hardware Configuration The RF interlock system was developed to enhance the reliability and response speed by replacing existing analog modules with a digital FPGA-based platform. In contrast to the previous design, which relied on discrete comparators and delay chains, the new system integrates interlock logic, data acquisition, and control functions within a single Zynq SoC, enabling signal analysis, postmortem recording, and seamless integration with the control system. The system is housed in a 19-inch 1U rack-mount chassis. The front panel provides eight ADC input channels and two trigger inputs, while the rear panel includes seven digital I/O channels as shown in Fig. 2 . LED indicators offer visual feedback on system status. Analog inputs receive RF signals from the klystron (forward and reverse) and cavity (forward, reverse, and pickup). Digital inputs monitor arc sensors in the circulator, klystron, and RF window, as well as vacuum fault signals. Digital outputs support remote arc-sensor testing and generate a fault-sum signal that is delivered to the RF switch and MPS in compliance with the klystron protection requirement of less than 10 us [ 7 ]. Each analog input channel includes attenuation and differential conversion stages prior to sampling by a 16-bit, 2 MS/s ADC (AD7380) [ 8 ]. Transient protection is implemented using Schottky and TVS diodes to suppress overvoltage conditions and improve noise immunity in the high-power RF environment. At the core of the system, a Zynq XC7Z020 SoC integrates programmable logic (PL) and dual-core ARM processors. The PL performs high-speed ADC acquisition, trigger handling, and interlock evaluation, while the processing system (PS) manages communication with the control system, data storage, and postmortem processing using 512 MB of DDR3 memory. Compared with the legacy analog interlock, which provided only fixed hardware thresholds, the proposed system enables programmable protection logic, continuous waveform capture, and data archiving, substantially improving diagnostic capability and system maintainability. 2.2 Design Criteria and Threshold Definition The RF interlock system is designed to perform real-time monitoring, fast protection, and post-event analysis for the KOMAC RF system. Timing-critical operations are implemented entirely in FPGA hardware to ensure guaranteed timing performance and minimal latency. Two trigger signals are employed: a Monitoring Trigger, which initiates waveform recording to DDR memory for visualization on the operator console, and a Calculation Trigger, which activates interlock detection and average-value computation. During each RF pulse, forward and reflected power signals are sampled simultaneously to compute the VSWR in real time. In the proposed system, the VSWR is calculated in the FPGA protection logic using the reflected to forward power ratio, as expressed by $$\:\text{V}\text{S}\text{W}\text{R}=\frac{1\:+\:\sqrt{\frac{Pref}{Pfwd}}}{1\:-\:\sqrt{\frac{Pref}{Pfwd}}}$$ 1 Where Pfwd and Pref denote the forward and reflected RF powers, respectively, as described in [ 9 ]. Based on allowable reflected-power limits and the operational constraints of the 1.6 MW pulsed klystron system, the VSWR protection thresholds were defined using a multi-level strategy. A warning level is issued when the mismatch reaches about VSWR ≈ 1.08 ~ 1.12, corresponding to reflected-power ratio of 1 ~ 5%. A soft-trip condition is activated when VSWR values of approximately 1.12 ~ 1.22 (5 ~ 10%) persist or occur repeatedly, leading to automatic power reduction or conditional shutdown on subsequent pulses. A hard-trip is triggered when the mismatch exceeds VSWR ≥ 1.5 (≥ 20%), resulting in an immediate emergency shutdown within 10 us to protect high-power RF components. 3. SYSTEM IMPLEMENTATION 3.1 FPGA and SoC Architecture The Zynq SoC’s heterogeneous architecture enables a clear separation between high-speed logic and supervisory processing. The PL handles ADC sampling, trigger processing, and interlock evaluation, while the PS manages EPICS communication, data storage, and postmortem file generation. Figure 3 illustrates the IP block diagram for the interlock system. The PL converts 16-bit ADC data to 32-bit floating-point values for power calculation and interlock evaluation. DDR memory is used for waveform buffering, postmortem data logging, and Ethernet-based data transfer. Additional peripherals include an EEPROM for configuration storage, a UART interface for debugging, and LED drivers for system status indication. Two trigger sequences as shown in Fig. 4 are implemented in the PL: Monitoring Trigger Sequence: ADC samples are continuously stored in DDR memory during the trigger high period. Upon completion, an interrupt notifies the PS to retrieve and visualize data. Calculation Trigger Sequence: The PL performs continuous averaging and VSWR calculations during the Calculation Trigger period. Forward and reflected RF signals are sampled by the ADCs at 500 ns intervals and processed directly in the PL to compute the VSWR, which is continuously compared with the predefined threshold. Once the computed VSWR exceeds the threshold, a digital output is asserted within the same RF pulse. The total processing latency for VSWR computation and threshold comparison in the PL was measured to be about 470 ns. Figure 5 presents the simulation results verifying the timing operation of the PL-based VSWR calculation and interlock decision. When the trigger returns low, averaging is terminated, and the PS applies calibration functions to compute the final RF power values. Figure 6 illustrates timing diagram of waveform acquisition and postmortem operation. At each Monitoring Trigger, the forward, reverse, and pickup RF waveforms are simultaneously recorded into DDR memory and a postmortem FIFO RAM. The waveforms are transferred to the PS DDR memory and delivered to users for live monitoring and visualization. Meanwhile, the FIFO RAM continuously retains waveform data for postmortem analysis. When an interlock event occurs, waveform recording to DDR is disabled, and the data stored in the FIFO RAM are preserved and converted in to CSV format file for fault analysis. After the interlock is cleared, normal waveform acquisition resumes. 3.2 Real-Time Interlock Processing and Data Flow Real-time RF protection is implemented entirely in FPGA logic to guarantee fixed latency and robust operation under high-power conditions. Interlocks are generated either by external digital fault inputs such as arc sensors and vacuum interlocks or by ADC-based threshold violations derived from RF power and VSWR calculations. Each interlock channel is independently configurable, supporting latch, bypass, and auto-reset modes. The interlock logic is synchronized with the RF pulse timing, ensuring that abnormal conditions are detected and mitigated within the same pulse. As shown in Fig. 7 , experimental verification confirmed that the total latency from fault detection to digital output assertion is around 1.34 us, satisfying klystron and RF component protection requirements. In addition to protection, the data flow architecture ensures that RF signal information used for interlock decisions is simultaneously available for diagnostic and post-event analysis, forming the basis for the postmortem function described in the following section. 3.3 Postmortem Data Acquisition and Fault Analysis In high-power RF systems, fast interlock action alone is insufficient for maintaining long-term operational reliability without a clear understanding of fault mechanisms. To address this limitation, the proposed system incorporates a dedicated postmortem data acquisition function that enables high-resolution analysis of RF performance before and after interlock events. During the Calculation Trigger period, the system records time-aligned waveform data for forward, reverse, and pickup RF signals, as well as the status of arc sensors and digital interlock inputs. This information is stored in DDR memory and subsequently transferred to Solid-State Storage (SSD) for long-term retention. The system supports storage of up to 60 sets of pre- and post-event data, enabling event correlation and fault trend analysis across multiple RF pulses. During the flat-top region of each RF pulse, ADC samples are acquired at 2 MS/s (500 ns sampling interval) over a l ms window, producing about 4,000 samples per channel per pulse. The system is designed to store waveform data from up to 60 consecutive pulses, requiring about 960 kB per channel. With six ADC channels, the total memory usage for postmortem recording is on the order of 6 MB, providing sufficient temporal resolution for detailed fault analysis. The postmortem data allow operators to precisely identify the timing and origin of RF faults and to correlate interlock events with modulator operation, cavity response, and external fault signals. Compared with the legacy analog system, which relied on external oscilloscopes and manual inspection, the proposed digital platform enables systematic root-cause analysis and significantly reduces troubleshooting and recovery time during high-power RF operation. 4. RESULTS The developed RF interlock system was tested under KOMAC RF operating conditions to verify its real-time protection performance. Figure 8 compares waveforms measured using an external oscilloscope and the internal ADCs, demonstrating consistent signal amplitudes and timing characteristics. Compared to the oscilloscope measurement, the ADC-measured voltage exhibits an approximately 94% amplitude level, resulting in systematic voltage discrepancy. This voltage difference is compensated using a combined hardware and software calibration approach to ensure measurement stability. Hardware calibration, implemented through precision analog conditioning, minimizes loading effects and major systematic errors at the ADC input. Software calibration subsequently compensates for residual gain and offset errors as well as temperature and component dependent variations. This dual calibration strategy provides robust long-term accuracy for RF interlock systems. Forward, reverse, and pickup RF signals were continuously at 2 MS/s, and fault conditions were artificially induced through arc sensor inputs. The system reliably detected interlocks originating from both digital fault inputs and ADC-based threshold violations. Upon fault detection, the RF pulse was interrupted within 10 us, meeting the klystron protection criteria. Flat-top ADC data were converted into RF power values using calibrated equations, confirming the validity of the real-time power computation. The postmortem function successfully captured waveform data before and after interlock events, enabling precise temporal analysis of fault characteristics. All system functions, including waveform monitoring, power calculation, and interlock status reporting, were verified through the control system. 5. CONCLUSIONS In this paper, a fully digital RF interlock and waveform acquisition system has been presented for reliable protection and diagnostics of the KOMAC RF systems. By separating monitoring and calculation triggers and implementing all timing-critical functions in FPGA hardware, the proposed system ensures a predictable interlock response while maintaining continuous waveform recording for postmortem analysis. The dual-path data handing architecture allows continuous waveform delivery to the control system during normal operation, while preserving fault-related data upon interlock events without data loss. Experimental results demonstrate stable operation, precise trigger coordination, and effective fault capture, validating the suitability of the proposed approach for high-power RF environments. The proposed digital interlock scheme improves operational flexibility by enabling adjustable thresholds and unified protection logic, and it can be readily extended to other accelerator RF systems requiring fast protection and detailed post-event diagnostics. Declarations Author Contribution Author ContributionsY.G. designed and developed the RF interlock system and wrote the manuscript.H.S. and J.H. contributed to hardware design and system integration.S.Y. and H.J. participated in experimental validation and data analysis.All authors reviewed and approved the final manuscript. Acknowledgement This study was supported by the Korea Multi-purpose Accelerator Complex (KOMAC) operation fund of the KAERI, the Ministry of Science and ICT (MSIT). KAERI ID no.524320-25. References S. Y. Lee et al., “Overview of the 100-MeV Proton Linear Accelerator at the Korea Multi-Purpose Accelerator Complex,” Journal of the Korean Physical Society, vol. 73, no. 9, pp. 1230–1238, 2018. S. Lee, H. S. Kim, and J. H. Jang, “RF Interlock and Protection System for the KOMAC 100-MeV Proton Accelerator,” in Proc. IPAC’16, Busan, Korea, 2016, pp. 2335–2337. H. S. Jeong, “RF Interlock Implementation Using Digital LLRF System for 100 MeV Proton Linac at KOMAC,” in Proc. IPAC’18, Vancouver, BC, Canada, 2018, doi:10.18429/JACoW-IPAC2018-WEPAL031 RF INTERLOCK. Xilinx Inc., “Zynq-7000 SoC Technical Reference Manual,” UG585, v1.13.1, Dec. 2020. EPICS Collaboration, “Experimental Physics and Industrial Control System (EPICS),” [Online]. Available: https://epics-controls.org Y. G. Song, “Interlock system for machine protection of the KOMAC 100-MeV proton linac,” Journal of the Korean Physical Society 66, 449–453 (2015). https://doi.org/10.3938/jkps.66.449 Toshiba Electron Tubes & Devices Co., Ltd., Operation Manual for E37621 Klystron Set, Document No. 2081.04.14, Toshiba Electron Tubes & Devices Co., Ltd., Japan. Analog Devices, “AD7380 Dual, Simultaneous Sampling, 16-Bit, 4 MSPS, Differential ADC,” Datasheet, Rev. C, 2023. D. M. Pozar, Microwave Engineering, 4th ed., Hoboken, NJ: Wiley, 2012, pp. 89–90. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 11 Feb, 2026 Reviews received at journal 10 Feb, 2026 Reviewers agreed at journal 04 Feb, 2026 Reviews received at journal 30 Jan, 2026 Reviewers agreed at journal 28 Jan, 2026 Reviewers invited by journal 28 Jan, 2026 Editor assigned by journal 28 Jan, 2026 Submission checks completed at journal 13 Jan, 2026 First submitted to journal 31 Dec, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8486209","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":585435224,"identity":"aca10ab8-afe0-4431-9421-7fcade0c1a68","order_by":0,"name":"Young-Gi Song","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA10lEQVRIiWNgGAWjYPACGwMQeQBESBCpJY10LYcN4EyCWgzOL3/4uODXeWP+9t6HBxj32DBIzj5AQMuNN8bGM/tum0mcOW5wgOFZGoM0XwIhLWfYpHl7btsw3EgD+uXAYQY5HkIOu3H8GVDLORv5+89AWv4ToeV8g5k0z48DZgY32EBaDjBIE9IieYPH2Ji3IdnY8AzQYQkHknkkewho4Tt//OFjnj92hvOOH2P+8OGAnZzEGQJaFG4kMDAwtkF5QDYhZzEwyPcfAJJ/CKobBaNgFIyCkQwA8GdF1SdMjOUAAAAASUVORK5CYII=","orcid":"","institution":"Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute","correspondingAuthor":true,"prefix":"","firstName":"Young-Gi","middleName":"","lastName":"Song","suffix":""},{"id":585435225,"identity":"5461d102-6a79-43ba-81ef-69f6137dfa83","order_by":1,"name":"Hae-Seong Jeong","email":"","orcid":"","institution":"Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Hae-Seong","middleName":"","lastName":"Jeong","suffix":""},{"id":585435226,"identity":"df981e21-3a59-43fd-a090-ab47c2a2df63","order_by":2,"name":"Jae-Ha Kim","email":"","orcid":"","institution":"Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Jae-Ha","middleName":"","lastName":"Kim","suffix":""},{"id":585435227,"identity":"da2a4dad-62ec-4eb1-96a6-f25aa5ee8453","order_by":3,"name":"Sung-Yun Cho","email":"","orcid":"","institution":"Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Sung-Yun","middleName":"","lastName":"Cho","suffix":""},{"id":585435228,"identity":"e839be28-24d8-404a-9b86-e4d33e6c378f","order_by":4,"name":"Hyeok-Jung Kwon","email":"","orcid":"","institution":"Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute","correspondingAuthor":false,"prefix":"","firstName":"Hyeok-Jung","middleName":"","lastName":"Kwon","suffix":""}],"badges":[],"createdAt":"2025-12-31 05:53:14","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8486209/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8486209/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":102347694,"identity":"9a2c7b54-2b6f-4bd8-b3b8-c0ee40fe5bde","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":491630,"visible":true,"origin":"","legend":"\u003cp\u003eOverall block diagram of the KOMAC high-power RF system. The red box indicates the legacy analog interlock system and external oscilloscope, which are functionally replaced by the proposed digital RF interlock system based on a Zynq SoC.\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/85ea482a49dba3ec3fdf569e.png"},{"id":102397443,"identity":"378d81d6-d8d0-4297-8c3f-dc02caf95ce2","added_by":"auto","created_at":"2026-02-11 10:16:59","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":374703,"visible":true,"origin":"","legend":"\u003cp\u003eRF interlock system hardware configuration, showing ADC input channels, trigger inputs, digital I/O ports, and status indicators.\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/2b71cefd9ac757959c3868b0.png"},{"id":102347697,"identity":"381e6aa9-2456-4ab7-b2f7-9e589e74eaf2","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":274922,"visible":true,"origin":"","legend":"\u003cp\u003eIP block design of the Zynq SoC-based RF interlock system, illustrating the division of functions between the programmable logic (PL) for continuous processing and the processing system (PS) for control, communication, and data management.\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/5add51602e4dc887b24cbfa7.png"},{"id":102347696,"identity":"a1d248d2-ccb9-4a48-81a4-2ffbc2d65b03","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":35990,"visible":true,"origin":"","legend":"\u003cp\u003eSequential diagram of the Monitoring Trigger and Calculation Trigger sequences used in the RF interlock system for waveform acquisition, power calculation, and interlock decision-making.\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/5aedb10f6155d3509640940e.png"},{"id":102347701,"identity":"94949518-5ef5-4346-b89c-0a6ab3135442","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":477444,"visible":true,"origin":"","legend":"\u003cp\u003eSimulation results of the programmable logic (PL), verifying the timing operation of VSWR computation and interlock decision generation based on ADC-sampled forward and reflected RF signals.\u003c/p\u003e","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/4ce4c0c97be105efc1199d85.png"},{"id":102397521,"identity":"d255eeaa-7252-4ac8-b3b9-5347a9b71ce5","added_by":"auto","created_at":"2026-02-11 10:17:41","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":229631,"visible":true,"origin":"","legend":"\u003cp\u003eTiming relationship between monitoring and calculation triggers, waveform acquisition, and postmortem operation during normal and interlock conditions.\u003c/p\u003e","description":"","filename":"floatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/d744a10a0e66931a3dbe5271.png"},{"id":102347700,"identity":"5d62634b-d5af-4a5c-88f3-a6be026a8f29","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":315822,"visible":true,"origin":"","legend":"\u003cp\u003eMeasured timing performance of the RF interlock system, showing the total latency from fault detection to digital output assertion, confirming compliance with klystron protection requirements.\u003c/p\u003e","description":"","filename":"floatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/bbf0a024e1f5f3f3777b34f2.png"},{"id":102347698,"identity":"ab12d28d-dc69-4ed8-9abd-3b2345d01ba8","added_by":"auto","created_at":"2026-02-10 17:47:34","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":376035,"visible":true,"origin":"","legend":"\u003cp\u003eComparison of RF forward, reverse, and pickup signal waveform measured using (left) external oscilloscope and (right) proposed ADC-based digital interlock system.\u003c/p\u003e","description":"","filename":"floatimage8.png","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/1cedf128583a6382b8892c07.png"},{"id":102399016,"identity":"13fd91db-b381-4410-9634-59e4196cbe15","added_by":"auto","created_at":"2026-02-11 10:32:12","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2986675,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8486209/v1/006e1f2f-ba12-4a23-8530-1fb317c6e7ef.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI","fulltext":[{"header":"1. INTRODUCTION","content":"\u003cp\u003eThe Korea Multi-purpose Accelerator Complex (KOMAC) operates a 100 MeV proton linear accelerator that supplies high-intensity proton beams for neutron science, isotope production, and related applications [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. The RF system comprises nine 350 MHz klystron amplifiers, each capable of delivering up to 1.6 MW of peak power, together with circulators and RF windows that ensure efficient RF transmission and protect accelerator components. For stable beam acceleration, RF amplitude and phase must be controlled within 1% and 1\u0026deg;, respectively, under high-power and high-duty operating conditions. Conventional RF interlock systems at KOMAC were implemented using analog comparators and fixed hardware thresholds. While effective for basic protection, these systems suffered from limited configurability, complex maintenance, and insufficient fault traceability [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e][\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. In particular, threshold adjustments required manual intervention, and post-event analysis relied heavily on external oscilloscopes, making systematic fault diagnosis difficult during routine high-duty operation.\u003c/p\u003e \u003cp\u003eTo address these limitations, a digital RF interlock system based on a Zynq System-on-Chip (SoC) platform has been developed [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. Forward, reverse, and pickup RF signals are digitized by 16-bit ADCs at 2 MS/s and processed in FPGA logic to calculate RF power, Voltage Standing Wave Ratio (VSWR), and arc detection in real time. Interlock decisions are executed in hardware with fixed latency, while the embedded ARM processor provides EPICS-based remote control, threshold configuration, and data acquisition functions [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e illustrates the overall block diagram of the KOMAC high-power RF system. The section enclosed by the red dashed line represents the legacy analog interlock system and external oscilloscope used for RF monitoring, both of which are functionally replaced by the proposed digital interlock platform. The new system improves operational flexibility and system integration by enabling centralized monitoring and control within the accelerator control environment.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eIn current KOMAC operation, both the modulator and high-power RF system employ automatic start-up logic. Accordingly, interlock signals generated by the digital RF interlock system are rapidly distributed to the automatic start-up system, the Machine Protection System (MPS) [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e], and the RF switch at the LLRF analog stage. This integrated protection architecture enhances system reliability and operational transparency during high-power RF operation. By replacing the legacy analog interlock with a fully digital platform, the proposed system provides deterministic protection, improved maintainability, and enhanced diagnostic capability. This paper presents the design, implementation, and experimental verification of the developed RF interlock system for the KOMAC 100 MeV linac.\u003c/p\u003e"},{"header":"2. SYSTEM DESIGN","content":"\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e \u003ch2\u003e2.1 Hardware Configuration\u003c/h2\u003e \u003cp\u003eThe RF interlock system was developed to enhance the reliability and response speed by replacing existing analog modules with a digital FPGA-based platform. In contrast to the previous design, which relied on discrete comparators and delay chains, the new system integrates interlock logic, data acquisition, and control functions within a single Zynq SoC, enabling signal analysis, postmortem recording, and seamless integration with the control system. The system is housed in a 19-inch 1U rack-mount chassis. The front panel provides eight ADC input channels and two trigger inputs, while the rear panel includes seven digital I/O channels as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e. LED indicators offer visual feedback on system status. Analog inputs receive RF signals from the klystron (forward and reverse) and cavity (forward, reverse, and pickup). Digital inputs monitor arc sensors in the circulator, klystron, and RF window, as well as vacuum fault signals. Digital outputs support remote arc-sensor testing and generate a fault-sum signal that is delivered to the RF switch and MPS in compliance with the klystron protection requirement of less than 10 us [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eEach analog input channel includes attenuation and differential conversion stages prior to sampling by a 16-bit, 2 MS/s ADC (AD7380) [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. Transient protection is implemented using Schottky and TVS diodes to suppress overvoltage conditions and improve noise immunity in the high-power RF environment. At the core of the system, a Zynq XC7Z020 SoC integrates programmable logic (PL) and dual-core ARM processors. The PL performs high-speed ADC acquisition, trigger handling, and interlock evaluation, while the processing system (PS) manages communication with the control system, data storage, and postmortem processing using 512 MB of DDR3 memory. Compared with the legacy analog interlock, which provided only fixed hardware thresholds, the proposed system enables programmable protection logic, continuous waveform capture, and data archiving, substantially improving diagnostic capability and system maintainability.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec4\" class=\"Section2\"\u003e \u003ch2\u003e2.2 Design Criteria and Threshold Definition\u003c/h2\u003e \u003cp\u003eThe RF interlock system is designed to perform real-time monitoring, fast protection, and post-event analysis for the KOMAC RF system. Timing-critical operations are implemented entirely in FPGA hardware to ensure guaranteed timing performance and minimal latency. Two trigger signals are employed: a Monitoring Trigger, which initiates waveform recording to DDR memory for visualization on the operator console, and a Calculation Trigger, which activates interlock detection and average-value computation.\u003c/p\u003e \u003cp\u003eDuring each RF pulse, forward and reflected power signals are sampled simultaneously to compute the VSWR in real time. In the proposed system, the VSWR is calculated in the FPGA protection logic using the reflected to forward power ratio, as expressed by\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:\\text{V}\\text{S}\\text{W}\\text{R}=\\frac{1\\:+\\:\\sqrt{\\frac{Pref}{Pfwd}}}{1\\:-\\:\\sqrt{\\frac{Pref}{Pfwd}}}$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eWhere Pfwd and Pref denote the forward and reflected RF powers, respectively, as described in [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eBased on allowable reflected-power limits and the operational constraints of the 1.6 MW pulsed klystron system, the VSWR protection thresholds were defined using a multi-level strategy. A warning level is issued when the mismatch reaches about VSWR\u0026thinsp;\u0026asymp;\u0026thinsp;1.08\u0026thinsp;~\u0026thinsp;1.12, corresponding to reflected-power ratio of 1\u0026thinsp;~\u0026thinsp;5%. A soft-trip condition is activated when VSWR values of approximately 1.12\u0026thinsp;~\u0026thinsp;1.22 (5\u0026thinsp;~\u0026thinsp;10%) persist or occur repeatedly, leading to automatic power reduction or conditional shutdown on subsequent pulses. A hard-trip is triggered when the mismatch exceeds VSWR\u0026thinsp;\u0026ge;\u0026thinsp;1.5 (\u0026ge;\u0026thinsp;20%), resulting in an immediate emergency shutdown within 10 us to protect high-power RF components.\u003c/p\u003e \u003c/div\u003e"},{"header":"3. SYSTEM IMPLEMENTATION","content":"\u003cdiv id=\"Sec6\" class=\"Section2\"\u003e \u003ch2\u003e3.1 FPGA and SoC Architecture\u003c/h2\u003e \u003cp\u003eThe Zynq SoC\u0026rsquo;s heterogeneous architecture enables a clear separation between high-speed logic and supervisory processing. The PL handles ADC sampling, trigger processing, and interlock evaluation, while the PS manages EPICS communication, data storage, and postmortem file generation. Figure\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e illustrates the IP block diagram for the interlock system. The PL converts 16-bit ADC data to 32-bit floating-point values for power calculation and interlock evaluation. DDR memory is used for waveform buffering, postmortem data logging, and Ethernet-based data transfer. Additional peripherals include an EEPROM for configuration storage, a UART interface for debugging, and LED drivers for system status indication.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eTwo trigger sequences as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e are implemented in the PL:\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eMonitoring Trigger Sequence: ADC samples are continuously stored in DDR memory during the trigger high period. Upon completion, an interrupt notifies the PS to retrieve and visualize data.\u003c/p\u003e \u003c/li\u003e \u003cli\u003e \u003cp\u003eCalculation Trigger Sequence: The PL performs continuous averaging and VSWR calculations during the Calculation Trigger period. Forward and reflected RF signals are sampled by the ADCs at 500 ns intervals and processed directly in the PL to compute the VSWR, which is continuously compared with the predefined threshold. Once the computed VSWR exceeds the threshold, a digital output is asserted within the same RF pulse. The total processing latency for VSWR computation and threshold comparison in the PL was measured to be about 470 ns. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e presents the simulation results verifying the timing operation of the PL-based VSWR calculation and interlock decision. When the trigger returns low, averaging is terminated, and the PS applies calibration functions to compute the final RF power values.\u003c/p\u003e \u003c/li\u003e \u003c/ul\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e illustrates timing diagram of waveform acquisition and postmortem operation. At each Monitoring Trigger, the forward, reverse, and pickup RF waveforms are simultaneously recorded into DDR memory and a postmortem FIFO RAM. The waveforms are transferred to the PS DDR memory and delivered to users for live monitoring and visualization. Meanwhile, the FIFO RAM continuously retains waveform data for postmortem analysis. When an interlock event occurs, waveform recording to DDR is disabled, and the data stored in the FIFO RAM are preserved and converted in to CSV format file for fault analysis. After the interlock is cleared, normal waveform acquisition resumes.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003e3.2 Real-Time Interlock Processing and Data Flow\u003c/h2\u003e \u003cp\u003eReal-time RF protection is implemented entirely in FPGA logic to guarantee fixed latency and robust operation under high-power conditions. Interlocks are generated either by external digital fault inputs such as arc sensors and vacuum interlocks or by ADC-based threshold violations derived from RF power and VSWR calculations. Each interlock channel is independently configurable, supporting latch, bypass, and auto-reset modes. The interlock logic is synchronized with the RF pulse timing, ensuring that abnormal conditions are detected and mitigated within the same pulse. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e, experimental verification confirmed that the total latency from fault detection to digital output assertion is around 1.34 us, satisfying klystron and RF component protection requirements.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eIn addition to protection, the data flow architecture ensures that RF signal information used for interlock decisions is simultaneously available for diagnostic and post-event analysis, forming the basis for the postmortem function described in the following section.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec8\" class=\"Section2\"\u003e \u003ch2\u003e3.3 Postmortem Data Acquisition and Fault Analysis\u003c/h2\u003e \u003cp\u003eIn high-power RF systems, fast interlock action alone is insufficient for maintaining long-term operational reliability without a clear understanding of fault mechanisms. To address this limitation, the proposed system incorporates a dedicated postmortem data acquisition function that enables high-resolution analysis of RF performance before and after interlock events. During the Calculation Trigger period, the system records time-aligned waveform data for forward, reverse, and pickup RF signals, as well as the status of arc sensors and digital interlock inputs. This information is stored in DDR memory and subsequently transferred to Solid-State Storage (SSD) for long-term retention. The system supports storage of up to 60 sets of pre- and post-event data, enabling event correlation and fault trend analysis across multiple RF pulses.\u003c/p\u003e \u003cp\u003eDuring the flat-top region of each RF pulse, ADC samples are acquired at 2 MS/s (500 ns sampling interval) over a l ms window, producing about 4,000 samples per channel per pulse. The system is designed to store waveform data from up to 60 consecutive pulses, requiring about 960 kB per channel. With six ADC channels, the total memory usage for postmortem recording is on the order of 6 MB, providing sufficient temporal resolution for detailed fault analysis. The postmortem data allow operators to precisely identify the timing and origin of RF faults and to correlate interlock events with modulator operation, cavity response, and external fault signals. Compared with the legacy analog system, which relied on external oscilloscopes and manual inspection, the proposed digital platform enables systematic root-cause analysis and significantly reduces troubleshooting and recovery time during high-power RF operation.\u003c/p\u003e \u003c/div\u003e"},{"header":"4. RESULTS","content":"\u003cp\u003eThe developed RF interlock system was tested under KOMAC RF operating conditions to verify its real-time protection performance. Figure\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e8\u003c/span\u003e compares waveforms measured using an external oscilloscope and the internal ADCs, demonstrating consistent signal amplitudes and timing characteristics. Compared to the oscilloscope measurement, the ADC-measured voltage exhibits an approximately 94% amplitude level, resulting in systematic voltage discrepancy. This voltage difference is compensated using a combined hardware and software calibration approach to ensure measurement stability. Hardware calibration, implemented through precision analog conditioning, minimizes loading effects and major systematic errors at the ADC input. Software calibration subsequently compensates for residual gain and offset errors as well as temperature and component dependent variations. This dual calibration strategy provides robust long-term accuracy for RF interlock systems.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eForward, reverse, and pickup RF signals were continuously at 2 MS/s, and fault conditions were artificially induced through arc sensor inputs. The system reliably detected interlocks originating from both digital fault inputs and ADC-based threshold violations. Upon fault detection, the RF pulse was interrupted within 10 us, meeting the klystron protection criteria. Flat-top ADC data were converted into RF power values using calibrated equations, confirming the validity of the real-time power computation. The postmortem function successfully captured waveform data before and after interlock events, enabling precise temporal analysis of fault characteristics. All system functions, including waveform monitoring, power calculation, and interlock status reporting, were verified through the control system.\u003c/p\u003e"},{"header":"5. CONCLUSIONS","content":"\u003cp\u003eIn this paper, a fully digital RF interlock and waveform acquisition system has been presented for reliable protection and diagnostics of the KOMAC RF systems. By separating monitoring and calculation triggers and implementing all timing-critical functions in FPGA hardware, the proposed system ensures a predictable interlock response while maintaining continuous waveform recording for postmortem analysis. The dual-path data handing architecture allows continuous waveform delivery to the control system during normal operation, while preserving fault-related data upon interlock events without data loss. Experimental results demonstrate stable operation, precise trigger coordination, and effective fault capture, validating the suitability of the proposed approach for high-power RF environments.\u003c/p\u003e \u003cp\u003eThe proposed digital interlock scheme improves operational flexibility by enabling adjustable thresholds and unified protection logic, and it can be readily extended to other accelerator RF systems requiring fast protection and detailed post-event diagnostics.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eAuthor ContributionsY.G. designed and developed the RF interlock system and wrote the manuscript.H.S. and J.H. contributed to hardware design and system integration.S.Y. and H.J. participated in experimental validation and data analysis.All authors reviewed and approved the final manuscript.\u003c/p\u003e\u003ch2\u003eAcknowledgement\u003c/h2\u003e\u003cp\u003eThis study was supported by the Korea Multi-purpose Accelerator Complex (KOMAC) operation fund of the KAERI, the Ministry of Science and ICT (MSIT). KAERI ID no.524320-25.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eS. Y. Lee et al., \u0026ldquo;Overview of the 100-MeV Proton Linear Accelerator at the Korea Multi-Purpose Accelerator Complex,\u0026rdquo; Journal of the Korean Physical Society, vol. 73, no. 9, pp. 1230\u0026ndash;1238, 2018.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eS. Lee, H. S. Kim, and J. H. Jang, \u0026ldquo;RF Interlock and Protection System for the KOMAC 100-MeV Proton Accelerator,\u0026rdquo; in Proc. IPAC\u0026rsquo;16, Busan, Korea, 2016, pp. 2335\u0026ndash;2337.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. S. Jeong, \u0026ldquo;RF Interlock Implementation Using Digital LLRF System for 100 MeV Proton Linac at KOMAC,\u0026rdquo; in Proc. IPAC\u0026rsquo;18, Vancouver, BC, Canada, 2018, doi:10.18429/JACoW-IPAC2018-WEPAL031 RF INTERLOCK.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eXilinx Inc., \u0026ldquo;Zynq-7000 SoC Technical Reference Manual,\u0026rdquo; UG585, v1.13.1, Dec. 2020.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eEPICS Collaboration, \u0026ldquo;Experimental Physics and Industrial Control System (EPICS),\u0026rdquo; [Online]. Available: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://epics-controls.org\u003c/span\u003e\u003cspan address=\"https://epics-controls.org\" targettype=\"URL\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eY. G. Song, \u0026ldquo;Interlock system for machine protection of the KOMAC 100-MeV proton linac,\u0026rdquo; Journal of the Korean Physical Society 66, 449\u0026ndash;453 (2015). \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://doi.org/10.3938/jkps.66.449\u003c/span\u003e\u003cspan address=\"10.3938/jkps.66.449\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eToshiba Electron Tubes \u0026amp; Devices Co., Ltd., Operation Manual for E37621 Klystron Set, Document No. 2081.04.14, Toshiba Electron Tubes \u0026amp; Devices Co., Ltd., Japan.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eAnalog Devices, \u0026ldquo;AD7380 Dual, Simultaneous Sampling, 16-Bit, 4 MSPS, Differential ADC,\u0026rdquo; Datasheet, Rev. C, 2023.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eD. M. Pozar, Microwave Engineering, 4th ed., Hoboken, NJ: Wiley, 2012, pp. 89\u0026ndash;90.\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"RF, VSWR, ZYNQ, EPICS, Interlock","lastPublishedDoi":"10.21203/rs.3.rs-8486209/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8486209/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe high-power RF system at the Korea Multi-purpose Accelerator Complex (KOMAC) operates at 350 MHz with a peak power of 1.6 MW, a pulse width of 1.5 ms. The RF duty factors of 24% and 9% for the 20 MeV and 100 MeV linac sections, respectively. Stable accelerator operation requires strict RF amplitude and phase stability within 1% and 1\u0026deg;, as well as cavity resonance detuning control within 10% of the RF bandwidth. To satisfy these demanding operational conditions, a digital high-power RF interlock system has been developed. The system supports remote and automatic threshold reconfiguration and is fully integrated into the EPICS control environment for centralized monitoring and operation. A Zynq SoC-based architecture digitizes forward, reverse, and pickup signals using ADCs, converts them into calibrated power values, and enables waveform and power monitoring during normal operation. In addition, a built-in postmortem function records pre- and post-interlock data, allowing operators to identify fault mechanisms and root causes with high temporal resolution.\u003c/p\u003e \u003cp\u003eThis paper presents the design and implementation of an RF protection system optimized for the 100 MeV proton linac at KOMAC, which consists of nine klystrons, nine circulators, and thirteen RF windows. Compared with the conventional analog interlock system, the proposed digital platform significantly enhances RF stability, fault diagnostics, and operational flexibility.\u003c/p\u003e","manuscriptTitle":"Design and Implementation of a Zynq SoC-Based Digital RF Interlock System for the 100 MeV Linear Accelerator at KAERI","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2026-02-10 17:47:29","doi":"10.21203/rs.3.rs-8486209/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2026-02-12T03:03:44+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-02-10T23:31:11+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"75397555092211707020596361808939525699","date":"2026-02-04T05:27:55+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2026-01-30T08:09:19+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"183248096202848642708909687372796417826","date":"2026-01-28T23:27:53+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2026-01-28T06:07:06+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2026-01-28T06:01:54+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2026-01-13T08:50:34+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of the Korean Physical Society","date":"2025-12-31T05:42:22+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"229451b8-fc1b-4142-98bc-6a7357429f67","owner":[],"postedDate":"February 10th, 2026","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2026-03-17T10:10:18+00:00","versionOfRecord":[],"versionCreatedAt":"2026-02-10 17:47:29","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-8486209","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-8486209","identity":"rs-8486209","version":["v1"]},"buildId":"XKTyCvWXoU3ODBz1xrDgd","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}