Triple-stacked FET Distributed Power Amplifier Using 28 nm CMOS Process

A broadband 28 nm complementary metal-oxide-semiconductor (CMOS) power amplifier was implemented using a distributed amplification design. To develop a model library for high-frequency design, various test patterns for active and passive elements were fabricated and compared through measurements. As a result, an n-channel field-effect transistor (NFET) with a symmetrical layout was adopted as the active device, and a co-planar waveguide (CPW) structure with floating first and second metal layers at the bottom was selected as the transmission line for the passive element. These choices demonstrated superior radio frequency (RF) characteristics at high frequencies compared to other device candidates. Furthermore, to address the low breakdown voltage of CMOS, a triple-stacked FET structure was designed as the gain cell of the distributed power amplifier (DPA). The fabricated DPA showed a maximum small-signal gain of 22 dB and a minimum of 10 dB from DC to 56 GHz, with a maximum saturated Pout of 20 dBm and a minimum of 13 dBm from 1 to 39 GHz. Notably, these results were achieved on the first attempt by designing solely based on measurement data from the test patterns.