Constraint-aware Annealing for CMOS-based Ising Machine LDPC Decoder

Constraint-aware Annealing for CMOS-based Ising Machine LDPC Decoder | Authorea try { document.documentElement.classList.add('js'); } catch (e) { } var _gaq = _gaq || []; _gaq.push(['_setAccount', 'G-8VDV14Y67G']); _gaq.push(['_trackPageview']); (function() { var ga = document.createElement('script'); ga.type = 'text/javascript'; ga.async = true; ga.src = ('https:' == document.location.protocol ? 'https://ssl' : 'http://www') + '.google-analytics.com/ga.js'; var s = document.getElementsByTagName('script')[0]; s.parentNode.insertBefore(ga, s); })(); Skip to main content Preprints Collections Wiley Open Research IET Open Research Ecological Society of Japan All Collections About About Authorea FAQs Contact Us Quick Search anywhere Search for preprint articles, keywords, etc. Search Search ADVANCED SEARCH SCROLL This is a preprint and has not been peer reviewed. Data may be preliminary. 27 August 2025 V1 Latest version Share on Constraint-aware Annealing for CMOS-based Ising Machine LDPC Decoder Authors : Eslam Elmitwalli 0000-0003-4396-2683 , Zeljko Ignjatovic , and Selçuk Köse Authors Info & Affiliations https://doi.org/10.22541/au.175631242.23660918/v1 Published IEEE Transactions on Circuits and Systems II: Express Briefs Version of record Peer review timeline 186 views 119 downloads Contents Abstract Supplementary Material Information & Authors Metrics & Citations View Options References Figures Tables Media Share Abstract Ising machines are efficient hardware solvers for combinatorial optimization problems (COPs). In CMOS-based Ising machines, the annealing process is crucial for efficiently navigating complex energy landscapes in mapped COPs such as Max-Cut and low-density parity-check (LDPC) decoding. QuBRIM, a CMOS-based Ising machine, has recently been utilized to solve LDPC decoding problems using multi-body interactions. A constraint-aware annealing schedule is proposed that increases the efficiency of solving the mapped COP. The proposed annealing method uses knowledge of the LDPC decoding problem to guide the annealing process. The annealing schedule is demonstrated through high-level simulations. The proposed methodology demonstrates a normalized energy efficiency (NEE) of 0.68 pJ/bit/iteration, which is a 1.8x improvement over random bit-flip annealing, and an 80% increase in throughput. Supplementary Material File (constraint_aware_annealing_for_cmos_based_ising_machine_ldpc_decoding_techrxiv.pdf) Download 1010.77 KB Information & Authors Information Version history V1 Version 1 27 August 2025 Peer review timeline Published IEEE Transactions on Circuits and Systems II: Express Briefs Version of Record 1 Mar 2025 Published Copyright This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License Keywords annealing combinatorial optimization ising machine ldpc decoding Authors Affiliations Eslam Elmitwalli 0000-0003-4396-2683 View all articles by this author Zeljko Ignjatovic View all articles by this author Selçuk Köse View all articles by this author Funding Information Defense Advanced Research Projects Agency FA8650-23-C-1034 National Science Foundation 2233378 Metrics & Citations Metrics Article Usage 186 views 119 downloads .FvxKWukQNSOunydq8rnd { width: 100px; } Citations Download citation Eslam Elmitwalli, Zeljko Ignjatovic, Selçuk Köse. Constraint-aware Annealing for CMOS-based Ising Machine LDPC Decoder. Authorea . 27 August 2025. DOI: https://doi.org/10.22541/au.175631242.23660918/v1 If you have the appropriate software installed, you can download article citation data to the citation manager of your choice. Simply select your manager software from the list below and click Download. For more information or tips please see 'Downloading to a citation manager' in the Help menu . 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