Investigation of Short Channel Effects in Al0.30Ga0.60As Channel Based Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) has been investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET's performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al0.30Ga0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and ION to IOFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable subthreshold slope and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/V, extremely near the ideal 60 mV/V value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/dec and a subthreshold value of around 64 mV/V.