Minimizing control dependencies of pipelining through optimizing branch selection

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Therefore, the execution efficiency of the pipelining is one of the critical factors impacting processor performance. The main factors that impact pipelining efficiency are data hazards caused by data dependencies and control hazards caused by control dependencies. Regarding the control hazards present in pipelining, although a few technologies are mentioned in the literature for addressing them, they frequently require significantly high latency and may not guarantee optimal quality. This paper introduces the Functional Function (FF), derived from the Fork function; by selectively executing branch instructions based on previous calculation results, the Functional Function can minimize control dependencies in pipelining and enhance the utilization of the processor pipelining via optimizing branch selection. The Intel VTune Profiler program analyzer was employed for data collection and analysis during the experiment to facilitate an unbiased comparison with existing methods. The experimental results indicate that the Functional Function significantly outperforms the existing methods, primarily reflected in the Pipeline utilization rate, CPI rate, and Bad Speculation rate. Furthermore, the utilization of the pipelining is enhanced by approximately 20%, accompanied by a nearly 1.5% increase in branch prediction accuracy compared with existing methods. Control hazards Functional Function Pipelining Loop unrolling Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 1. Introduction Most microprocessor implementations use forms of pipelining to enhance performance, overlapping the execution of multiple instructions [ 1 ] . Microprocessors have succinct specifications of the pipelining mechanism's intended behavior, and various methods are used to ensure that the pipelined execution faithfully implements the sequential instructions. Pipelining has been a fundamental technique to achieve parallelism for different computer systems [ 2 ] . One of the significant advantages of the pipelining mechanism is that it reduces delay per instruction, and the CPI reduces. It is universally acknowledged that there are two main architectures around which most of the Processors are designed: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC) [ 3 ] . Regardless of CISC architecture or RISC architecture, in the instruction processing stage, the efficiency of processor execution can be improved by adding a pipelining mechanism. Similarly, the pipelining mechanism gives the processor excellent instruction-level parallelism (ILP). Through parallel processing technology, processors can efficiently process massive amounts of data and improve the performance of computing-intensive applications. Another significant advantage is that the pipelining mechanism enhances the throughput and speedup of the system and can be used for high-speed processor applications. Microarchitecture implementation of the pipelining mechanism is more complex, and maintaining the CPI close to 1 is always challenging. The deviation of CPI from the ideal value is due to several reasons, such as branch miss-prediction [ 4 , 5 , 6 ] , memory latency [ 7 , 8 ] , pipeline hazards [ 9 , 10 , 11 ] , etc. The more common pipeline hazards are data hazards and control hazards. Much literature has provided solutions for these two hazards [ 12 , 13 , 14 , 15 , 16 ] . For example, pipeline pauses and bubbles can be used to deal with data hazards in the pipeline. Similarly, this approach can also be used to handle processor control hazards. However, whether it is pipeline stalls or the addition of bubbles, the impact will reduce the execution efficiency of the pipelining. Another standard method of handling control hazards, used by most modern computers, is branch prediction technology, which mainly improves system performance by predicting the results of branch instructions early in the pipeline. Control can be transferred to the correct instruction if the branch prediction is correct without triggering a pipeline stall. However, when a misprediction occurs, pipeline control must ensure that instruction execution following the mispredicted branch does not take effect, and the pipeline must be restarted at the correct branch address; the impact will also reduce the efficiency of the pipeline. This paper introduces a Functional Function for reducing pipeline control hazards by optimizing branch selection, thereby improving pipeline utilization. Functional Function is derived from the Fork function, and it bases the execution of branch instructions on the results of previous computations (condition code status) rather than the branch instruction. As a result, the number of branch selections in the pipeline will be reduced, thereby avoiding the adverse impact of branch instructions on the pipelining and improving the utilization of the pipelining. The rest of this paper is organized as follows: Section 2 presents the ILP, pipelining mechanism, and Loop unrolling mechanism; Section 3 presents the Functional Function; Section 4 presents the experimental results and analysis; and the conclusion and further work are described in Section 5. 2. METHODOLOGY Instruction-level parallelism (ILP) [ 23 , 17 , 18 , 19 ] is a measure of the average number of instructions that can be executed at the same time by a processor. Practically all processors can employ a pipelining mechanism to execute instructions, augmenting performance concurrently. Modern processors extensively employ microarchitectural designs to optimize ILP, including the pipelining and loop unrolling mechanisms. 2.1 Pipelining mechanism In modern computer systems, processors achieve high performance through the pipelining mechanism. Pipelining can be seen as transforming a source behavioral specification into a functionally equivalent description, which partitions all operators into pipeline-stage fragments executed in a time-sliced fashion [ 20 ] . In processing pipelining, the execution of an instruction progresses through a sequence of stages, each referred to as a pipeline stage. The number of pipeline stages is among the crucial aspects of any processor design. An increased number of pipeline stages enables a designer to achieve a higher operating frequency, enhancing overall throughput. Fundamentally, the pipelining mechanism is a time-parallel technology, with its workflow primarily divided into three phases: Instruction Loading, Instruction Streaming, and Instruction Emptying. In modern processor design, 10 to 20-stage pipelining processors are available [ 21 ] . As mentioned above, some control dependencies between pipelining instructions may decrease efficiency. This paper will introduce a classic five-stage pipelining processor and then explore the control hazards caused by the control dependencies. The five stages are as follows: Instruction Fetch (IF): IF refers to reading instructions from the pipeline. Instruction Decode (ID): ID refers to translating instructions fetched from memory. After decoding, the operand register index required by the instruction is obtained, and this index can be used to read the operand from the general register. Execution (EX): EX refers to performing actual operations on instructions. The most common component in the execution phase is the arithmetic logic unit, a hardware functional unit that implements specific operations. Memory Access (MEM): MEM refers to the process in which memory access instructions read data from the memory or write it into the memory. Memory access instructions are often one of the essential instruction types in the instruction set. Write Back (WB): WB refers to writing the instruction execution results to the general-purpose register set. At this stage, the CPU writes the execution result or memory access result to the register. The benefit of a five-stage pipeline is its ability to execute multiple operations of one instruction within a single clock cycle, thereby enhancing the processing efficiency of the processor. A representative five-stage processor pipelining instruction execution sequence [ 22 ] is presented below. As shown in Fig. 1 , on each cycle time, another instruction is fetched and begins its five-cycle execution. If an instruction is initiated every cycle time, the performance can be up to five times that of a non-pipelined processor. However, the pipelining mechanism depends on dependencies between instructions. For instance, if two instructions are data-dependent, they must be executed sequentially. As explained below, they cannot be executed simultaneously or overlap completely—various dependencies impact the pipelining mechanism. Data dependencies(also called actual data dependencies). The dependencies occur when the result of one instruction is used directly or indirectly by another. Control dependencies. The dependency determines the order of instructions for each branch. Instructions inside a branch cannot be moved before the branch is evaluated. Name dependencies. A name dependence occurs when two instructions use the same register or memory location, called a name, but there is no data flow between the instructions associated with that name. 2.2 Loop unrolling mechanism Loop unrolling, also known as loop unwinding, is a well-known compiler optimization that can lead to significant performance improvements [ 23 ] . The effects of loop unrolling on CPU programs have been understood and described extensively in past work [ 24 , 25 , 26 ] . A typical 1X1 Loop unrolling and 2X1 Loop unrolling instruction execution sequence is illustrated in Fig. 2 . Loop unrolling is a program transformation. The basic idea of loop unrolling is creating multiple copies of the loop body [ 27 ] to perform various iterations simultaneously. The quantity of copies is referred to as the unrolling factor. A programmer can perform this conversion manually or through an optimizing compiler. The objective of loop unrolling is to enhance a program's performance. Loop unrolling can enhance program performance in two primary ways. Firstly, it minimizes the number of operations that do not directly impact the program outcome, such as loop index computations and conditional branching. Secondly, it offers a method to modify the code further and decrease the number of operations within the overall computational critical path. However, excessive unrolling may impair performance due to increased register pressure and instruction cache misses [ 27 ] . Consequently, when implementing loop unrolling technology, evaluating its merits and drawbacks is crucial based on the specific context and choosing an appropriate loop unrolling coefficient (i.e., the number of times the identical code appears in the loop) to strike a balance between program size and execution speed. 3. Functional Function The traditional method of executing conditional operations involves conditional control transfers, where the program follows a specific execution path based on whether the condition is satisfied. This mechanism is straightforward and adaptable in programming, requiring only a single judgment statement for implementation. However, for modern processors, this may lead to significant inefficiencies. As previously mentioned, processors attain high performance through pipelining; contemporary processors employ branch prediction to enable the instruction pipeline to execute persistently. Upon a misprediction, the pipelining must guarantee that the instruction execution after the mispredicted branch does not materialize, and the pipelining must be restarted at the accurate branch address, markedly diminishing the efficiency of pipelining execution. This paper mainly presents a Functional Function that can reduce the instruction execution efficiency problem caused by control hazards in the pipelining by optimizing branch selection. The execution method of the Functional Function is similar to the Fork function. The difference is that the Functional Function treats one branch in the branch sequence (called a true branch) as a path for the sequential execution of instructions and the other branches (called false branches) as paths chosen for execution. When the logical value is unsatisfied, the program switches the true and false branches through conditional transmission statements to ensure the program is correct. The instruction execution of the Functional Function flow diagram is shown in Fig. 3 . For branch instructions, in an abstract sense, the Functional Function divides the branch into true and false branches, employing conditional operations to calculate values and ultimately utilizing these values to update the program state. Unlike branch prediction employed in conditional jump instructions, Functional Function selectively updates the program state via conditional statements. For instance, Fig. 4 displays the instruction sequence for a Functional Function and a conditional jump function. The Functional Function instructions are executed sequentially, sans any branch jump instructions. Conversely, the conditional jump function executes the program via branch jumps. 4. Experimental results and analysis 4.1 Experimental Setup The experimental environment is Windows 11 operating system, gcc (x86_64-win32-sjlj-rev0, Built by MinGW-W64 project) 8.1.0, Visual Studio Code, GNU cross-toolchain and Intel VTune Profiler 2024.0.1. The experiment is divided into two parts, namely, pass-by-value and pass-by-address. In the pass-by-value experiment, two arrays, A and B, are set up, and the absolute value of the difference between the two is assigned to array A. In the pass-by-address experiment, two distinct addresses are configured, and the program transfers data to these addresses through function calls. Figure 5 illustrates the experimental flow. The first step is to identify the code objects, followed by the metrics used for performance evaluation in the experiment. Although the proposed method applies to various conditional jump branches, this paper exemplifies common conditional jump functions because common conditional jump functions are typically more prevalent in programs. The experiment tests different common conditional jump functions, aiming to verify the actual advantages of Functional Function by testing various types of jump codes. In order to more conveniently observe the execution status of instructions inside the program, the experiment leverages the gcc compiler to parse the assembly instructions of the program’s high-level language. In addition, when analyzing program performance in subsequent stages, Intel Vtune Profiler will also conduct a comprehensive analysis of the assembly instructions. The data generated by the experiment are collected and analyzed through the Intel VTune Profiler performance analyzer. Utilizing the Intel VTune Profiler performance analyzer enables the generation of numerous performance analysis metrics. In this paper, three of the crucial metrics of the Intel VTune Profiler are employed in a comparative analysis of program performance: 1) CPI Rate. Cycles per Instruction Retired, or CPI, is a fundamental performance metric indicating how much time each executed instruction took in units of cycles. The smaller the CPI value, the faster the processor execution efficiency. 2) Pipeline Utilization. The Pipeline Utilization metric represents the Pipeline Slots fraction utilized by practical work, meaning the issues that are eventually completed. 3) Bad Speculation. Bad Speculation represents a Pipeline Slots fraction wasted due to incorrect speculations. 4.2 Experimental Results Part 1. Pass-by-value experiment Instruction-level parallelism was incorporated into the experiment, and the 2X1 loop unrolling mechanism was employed to enhance the program's performance further. The experiment entailed data analysis of three methods: 1) 1X1FF, the Functional Function sans loop unrolling; 2) 2X1FF, the Functional Function with 2X1 loop unrolling; and 3) 2X1JMP, the 2X1 loop unrolling conditional jump function. Results are summarized in Table 1 and Fig. 6 . The execution efficiency of the 2X1FF ranks highest among the three, followed by the 1X1FF, and the lowest efficiency is attributed to the 2X1JMP. When FF is used, as illustrated in Fig. 6 , the execution efficiency of the 2X1FF surpasses that of the 1X1FF, and the runtime of the former program spans from 110 ms to 125 ms, whereas the latter remains within the range of 140 ms to 160 ms. The only difference between the two is the loop unrolling factor; as mentioned, employing functionalities of loop unrolling can lessen the calculations on the critical path, thereby enhancing the program's efficiency, which is the main reason for this difference. Furthermore, both programs' pipeline utilization, Bad Speculation, and CPI rates are similar. What is different from the Functional Function is the conditional jump function. Table 1 Data indicators for three methods (The experiment carried out 600 data collections on three methods and randomly selected 100 of the data to form a table) methods Program Time(s) CPI Pipeline Utilization Bad Speculation 2X1FF 12.797 0.216 90.3% 1.2% 1X1FF 15.951 0.23 81.6% 1.3% 2X1JMP 22.985 0.326 69.3% 2.8% As seen from Fig. 6 , when 2X1JMP is used, whether the 1X1FF or the 2X1FF compared with the 2X1 JMP, its execution efficiency is improved hugely. The Program Time of the 2X1JMP is nearly twice that of the 2X1FF—the Program Time of the former ranges from 200 ms to 220 ms. Moreover, as shown in Table 1 , The Pipeline Utilization of the 2X1FF increased by about 20% compared with the 2X1JMP, the Bad Speculation rate decreased from 2.8–1.2%, and the CPI rate decreased from 0.326 to 0.216. The main reason for this difference in performance is the impact of branch prediction on the program, which is also encountered in the second experiment. The impact caused by branch prediction is mainly attributed to two points: 1) Pipeline execution efficiency. The performance improvement of branch prediction is based on the correct pipeline execution. As mentioned above, Functional Function execute branch instructions sequentially without branch prediction. This prediction further improves the pipeline utilization, and the conditional jump function pair improves the pipeline utilization through branch prediction. If the prediction is wrong, the pipeline efficiency will inevitably decrease. For example, an ideal 5-stage pipeline and an actual running 5-stage pipeline are given below to illustrate the impact of branch prediction on pipeline processors, as shown in Figs. 8 and 9 . A slot represents a pipeline stage, Code that executes ten cycles. 2) Instruction-level parallelism, the number of CPU cores used in the experiment is 8, meaning that eight parallel instructions can be executed simultaneously. If the branch is mispredicted, then the instruction pipeline of the conditional jump function will be re-executed, that is, using a different approach for the same program; loop unrolling may improve program performance on 2X1FF but may have side effects on 2X1JMP. In an ideal pipeline processor, one instruction will be completed during Instruction Streaming for every clock cycle unless a Bad Speculation occurs. When a branch prediction error occurs, the pipeline execution deviates from the scenario above, reducing the pipeline's execution efficiency. As shown in Fig. 9 below, twenty out of the fifty slots become stalled, resulting in a microarchitectural pipeline utilization of only 60%. In conclusion, the impact of branch prediction on processor performance can be seen from the above example. the Bad Speculation of the pipeline for these three methods 2X1FF, 1X1FF and 2X1JMP are 1.2%, 1.3%, and 2.8%, respectively. The pipeline utilization rates of the three are 90.3%, 81.6%, and 69.3%, respectively. It can be seen that using Functional Function, Bad Speculation decreased by about 1.5%, and the utilization of the pipeline increased by about 20%. Part 2. Pass-by-address experiment Unlike the pass-by-value experiment, the pass-by-address experiment is more intricate. This approach necessitates function calls to various addresses, resulting in a corresponding increase in the program's execution time. In addition, since address transfer involves operations on the stack and needs to be run on the stack, stack-related operations are required, which may increase the overall execution time of the program. Considering the factors mentioned above, the duration of the address transfer experiment might escalate, and the precise execution time will be derived from the experimental data. Figure 10 and Table 2 summarize the results of the three methods. As anticipated, the collective execution time of the three methods escalated. The 2X1FF remains the most efficient, with a running time between 200 ms and 220 ms, followed by the 1X1FF, with a running time between 250 ms and 270 ms, with the 2X1JMP still ranking as the least rapid; the Program Time hovers at 370 ms. When the FF is used, the Program Time trend of the Functional Function can be seen in Fig. 10 ; whether the 2X1FF or the 1X1FF, the Program Time has increased, and its running trend has mostly stayed the same compared with the first experiment. This can be attributed to the fact that for Functional Function, the main impact on program execution performance is using unrolling factors in the unrolling mechanism. Table 2 Data indicators for three methods (The experiment carried out 600 data collections on three methods and randomly selected 50 of the data to form a table) methods Program Time(s) CPI Pipeline Utilization Bad Speculation 2X1FF 10.630 0.320 63.4% 0.4% 1X1FF 10.891 0.374 60.8% 0.7% 2X1JMP 17.273 0.532 41% 2.1% When 2X1JMP is used, the execution time of the program has increased significantly. The Program Time is still about two times that of 2X1FF. However, its running trend remains stable. Compared with 2X1JMP, as shown in Table 2 , The pipelining utilization of the 2X1FF increased by about 20%, the Bad Speculation rate decreased from 2.1–0.4%, and the CPI rate decreased from 0.532 to 0.320. Based on the above experimental data analysis, two reasons exist, similar to the first experiment. 1) program execution sequence, as mentioned above, the difference between 2X1FF and 2X1JMP is that Functional Function do not require branch prediction, and sequential execution avoids The impact of branch prediction on pipeline performance. The reason for Bad Speculation in 2X1FF is due to the conditional test of program loops; 2) Loop unrolling mechanism. The improvement of program performance by loop unrolling is based on the correct execution sequence of the program. If the program is executed according to the wrong instruction sequence, then all the work done is in vain. In other words, for the same program, loop unrolling may improve program performance on 2X1FF but may have side effects on 2X1JMP. In conclusion, As shown in Table 2 above, the Bad Speculation of the three methods 2X1FF, 1X1FF, and 2X1JMP is 0.4%, 0.7%, and 2.1%, respectively. The Pipeline Utilization rates are 63.4%, 60.8%, and 41% respectively. CPI rates are 0.320, 0.374, and 0.532. The utilization of the pipeline is increased by about 20%, and the accuracy of branch prediction, as shown in the experimental data, is increased by about 1.5%. 5. Conclusions and further work This paper introduces a Functional Function. Functional Function is derived from the Fork function, and its operating mechanism is similar to the Fork function. When a conditional jump instruction is encountered, the program executes the current instruction sequentially, branches the current instruction, and selectively updates the program status according to the condition code, thereby avoiding the proportion of Bad Speculation in the program and enhancing the efficiency of the pipelining. Whether the pass-by-value experiment or the pass-by-address experiment, the Functional Function significantly outperformed the other existing methods in terms of performance and efficiency, including average Pipeline utilization rate, CPI rate, and Bad Speculation rate. Because of its robust performance, low program time, and the ability to give stable performance over various jump functions, the Functional Function is a viable solution for control hazards in the pipelining. However, the limitation of the experiment lies in the fact that the Intel user guide lists four factors that could affect the program's efficiency. In this study, only the impact of Bad Speculation is examined (Bad Speculation is most frequently due to branch misprediction), while the other three factors still need to be considered. Future research will delve deeper into the analysis of the remaining three factors. Declarations Funding This study was funded by [Natural Science Foundation of Heilongjiang Province, China] (Grant numbers [LH2019F027]). Conflicts of interest/Competing interests There are no Competing Interests, and the authors have no financial or proprietary interests in any material discussed in this article. Author Contribution Author Fei Gao completed the manuscript, pictures and tables of the entire paper.Author Jingbo Shao completed review of the manuscript. References Bryant, Randal E. Term-level verification of a pipelined CISC microprocessor. School of Computer Science, Carnegie Mellon University, 2005. Jiang, Weiwen, et al. "On the design of time-constrained and buffer-optimal self-timed pipelines." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38.8 (2018): 1515-1528. K. P. K and V. Prakash A. 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"Vectorization-aware loop unrolling with seed forwarding." Proceedings of the 29th International Conference on Compiler Construction. 2020. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Submission checks completed at journal 24 Apr, 2024 Editor assigned by journal 24 Apr, 2024 First submitted to journal 23 Apr, 2024 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4315205","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":295366636,"identity":"2388abad-6e3a-49ac-9d92-98c8abe7f2ea","order_by":0,"name":"Fei Gao","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA3UlEQVRIiWNgGAWjYNACAxseNvYGEMOCKPWMDQwVaTJ8PAdAWiSI1XLmsI2cRAKIQ4QW+fbm5w9/tjHzsEk+v7rhR4EEA397dwJeLQZnjhk287ax8bBJ55Td7AE6TOLM2Q34tUgkGDYztvGAtKTd4AFqMZDIxa9Ffv7zj40/2ySADjuTdvMPMVoYbvAYNvCcMeBhk2A/dpsoWwzO5BTO5qlI4GHjyWG7LWMgwUPQL/Ltxzd8/GHw3x7IeHbzzR8bOf72XgIOQwAeAzBJrHIQYH9AiupRMApGwSgYQQAAVVRD6OyRO5cAAAAASUVORK5CYII=","orcid":"","institution":"Harbin Normal University","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"Fei","middleName":"","lastName":"Gao","suffix":""},{"id":295366639,"identity":"f9a2223f-4a44-4d9a-b7ea-084214eb55ed","order_by":1,"name":"Jingbo Shao","email":"","orcid":"","institution":"Harbin Normal University","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Jingbo","middleName":"","lastName":"Shao","suffix":""}],"badges":[],"createdAt":"2024-04-24 03:37:11","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4315205/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4315205/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":55599979,"identity":"ebde514d-de45-4e8e-a4e7-6f1c92c571e5","added_by":"auto","created_at":"2024-04-30 11:28:19","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":44503,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ePipeline Time and Instruction Execution Diagram\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/9f3229b7bc7745215e9cdecb.png"},{"id":55600334,"identity":"fda766ac-2916-4d56-bf3b-19b612a22968","added_by":"auto","created_at":"2024-04-30 11:36:19","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":75128,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eLoop unrolling instruction execution sequence\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/6a2d2c773abe6f1c48fe98d0.png"},{"id":55599981,"identity":"3e41a4b6-610f-4424-8acf-23dd340ea6b7","added_by":"auto","created_at":"2024-04-30 11:28:19","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":42345,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eThe instruction execution of the Functional Function flow diagram\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/4afb101b2ec4c2ac1da43961.png"},{"id":55599988,"identity":"cbb0627f-2697-4501-8d92-ccc068c8495d","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":96363,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eAssembly code. The left side is the assembly code of the Functional Function, and the right side is the assembly code of the conditional jump instruction. Both have the same Function. However, Functional Function execute each instruction sequentially, while conditional jump functions selectively execute branch instructions.\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/3ca3f44077f760a19e4595d4.png"},{"id":55599982,"identity":"7793e2b1-b0ed-4fcd-b057-9fed7aa38fc4","added_by":"auto","created_at":"2024-04-30 11:28:19","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":67239,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eOptimization branch selection and experiment flow\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/9b0db3bbba2da8ca57c56a2f.png"},{"id":55599986,"identity":"388b666b-ccd8-43f9-a9b9-7a67f1964a26","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"jpg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":58758,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eExecution efficiency of three methods\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"6.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/0c7689f1b64d3f21565de000.jpg"},{"id":55600335,"identity":"22156253-9e3f-443c-8aec-8153f74bcda6","added_by":"auto","created_at":"2024-04-30 11:36:20","extension":"jpg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":35455,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eProgram/Function Time\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"7.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/4f6ce2119d5d305d01d0ddd3.jpg"},{"id":55599983,"identity":"de4a8d59-1a46-485b-87b4-dba7d86187f1","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":100599,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eAn ideal 5-stage pipeline execution phase\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/7a4b71b31e9daf5b60527dc5.png"},{"id":55599984,"identity":"a4402131-707e-463a-91da-e8b7acea4c6c","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":111584,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eAn actual 5-stage pipeline execution with Bad Speculation\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/609a449a989cb57c9886921c.png"},{"id":55599985,"identity":"b248390d-570b-47d2-9cb7-ed54d6cbbc5f","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"jpg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":50666,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eExecution efficiency of three methods\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"10.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/90c72ca51377b9594e709bba.jpg"},{"id":55599989,"identity":"2891b4e9-9bf7-435d-b330-351f280bdb39","added_by":"auto","created_at":"2024-04-30 11:28:20","extension":"jpg","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":39059,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eProgram/Function Time\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"11.jpg","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/99707bfea847de74b87a1545.jpg"},{"id":55601177,"identity":"580eb9f2-537f-4b8f-881b-5a5cb9babf3e","added_by":"auto","created_at":"2024-04-30 11:44:20","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1424548,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4315205/v1/365e7821-d35e-4cb3-bc00-5343f2a010b4.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Minimizing control dependencies of pipelining through optimizing branch selection","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eMost microprocessor implementations use forms of pipelining to enhance performance, overlapping the execution of multiple instructions\u003csup\u003e[\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]\u003c/sup\u003e. Microprocessors have succinct specifications of the pipelining mechanism's intended behavior, and various methods are used to ensure that the pipelined execution faithfully implements the sequential instructions. Pipelining has been a fundamental technique to achieve parallelism for different computer systems\u003csup\u003e[\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]\u003c/sup\u003e. One of the significant advantages of the pipelining mechanism is that it reduces delay per instruction, and the CPI reduces. It is universally acknowledged that there are two main architectures around which most of the Processors are designed: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC)\u003csup\u003e[\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]\u003c/sup\u003e. Regardless of CISC architecture or RISC architecture, in the instruction processing stage, the efficiency of processor execution can be improved by adding a pipelining mechanism. Similarly, the pipelining mechanism gives the processor excellent instruction-level parallelism (ILP). Through parallel processing technology, processors can efficiently process massive amounts of data and improve the performance of computing-intensive applications. Another significant advantage is that the pipelining mechanism enhances the throughput and speedup of the system and can be used for high-speed processor applications.\u003c/p\u003e \u003cp\u003eMicroarchitecture implementation of the pipelining mechanism is more complex, and maintaining the CPI close to 1 is always challenging. The deviation of CPI from the ideal value is due to several reasons, such as branch miss-prediction\u003csup\u003e[\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e, \u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]\u003c/sup\u003e, memory latency\u003csup\u003e[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e, \u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/sup\u003e, pipeline hazards\u003csup\u003e[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e, \u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e, \u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]\u003c/sup\u003e, etc. The more common pipeline hazards are data hazards and control hazards. Much literature has provided solutions for these two hazards\u003csup\u003e[\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e, \u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e, \u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e, \u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e, \u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]\u003c/sup\u003e. For example, pipeline pauses and bubbles can be used to deal with data hazards in the pipeline. Similarly, this approach can also be used to handle processor control hazards. However, whether it is pipeline stalls or the addition of bubbles, the impact will reduce the execution efficiency of the pipelining. Another standard method of handling control hazards, used by most modern computers, is branch prediction technology, which mainly improves system performance by predicting the results of branch instructions early in the pipeline. Control can be transferred to the correct instruction if the branch prediction is correct without triggering a pipeline stall. However, when a misprediction occurs, pipeline control must ensure that instruction execution following the mispredicted branch does not take effect, and the pipeline must be restarted at the correct branch address; the impact will also reduce the efficiency of the pipeline. This paper introduces a Functional Function for reducing pipeline control hazards by optimizing branch selection, thereby improving pipeline utilization. Functional Function is derived from the Fork function, and it bases the execution of branch instructions on the results of previous computations (condition code status) rather than the branch instruction. As a result, the number of branch selections in the pipeline will be reduced, thereby avoiding the adverse impact of branch instructions on the pipelining and improving the utilization of the pipelining. The rest of this paper is organized as follows: Section 2 presents the ILP, pipelining mechanism, and Loop unrolling mechanism; Section 3 presents the Functional Function; Section 4 presents the experimental results and analysis; and the conclusion and further work are described in Section 5.\u003c/p\u003e"},{"header":"2. METHODOLOGY","content":"\u003cp\u003eInstruction-level parallelism (ILP)\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e23\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e]\u003c/sup\u003e is a measure of the average number of instructions that can be executed at the same time by a processor. Practically all processors can employ a pipelining mechanism to execute instructions, augmenting performance concurrently. Modern processors extensively employ microarchitectural designs to optimize ILP, including the pipelining and loop unrolling mechanisms.\u003c/p\u003e\n\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\n\u003ch2\u003e2.1 Pipelining mechanism\u003c/h2\u003e\n\u003cp\u003eIn modern computer systems, processors achieve high performance through the pipelining mechanism. Pipelining can be seen as transforming a source behavioral specification into a functionally equivalent description, which partitions all operators into pipeline-stage fragments executed in a time-sliced fashion\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e]\u003c/sup\u003e. In processing pipelining, the execution of an instruction progresses through a sequence of stages, each referred to as a pipeline stage. The number of pipeline stages is among the crucial aspects of any processor design. An increased number of pipeline stages enables a designer to achieve a higher operating frequency, enhancing overall throughput. Fundamentally, the pipelining mechanism is a time-parallel technology, with its workflow primarily divided into three phases: Instruction Loading, Instruction Streaming, and Instruction Emptying. In modern processor design, 10 to 20-stage pipelining processors are available\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e21\u003c/span\u003e]\u003c/sup\u003e. As mentioned above, some control dependencies between pipelining instructions may decrease efficiency. This paper will introduce a classic five-stage pipelining processor and then explore the control hazards caused by the control dependencies. The five stages are as follows:\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003e\n\u003cp\u003eInstruction Fetch (IF): IF refers to reading instructions from the pipeline.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003eInstruction Decode (ID): ID refers to translating instructions fetched from memory. After decoding, the operand register index required by the instruction is obtained, and this index can be used to read the operand from the general register.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003eExecution (EX): EX refers to performing actual operations on instructions. The most common component in the execution phase is the arithmetic logic unit, a hardware functional unit that implements specific operations.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003eMemory Access (MEM): MEM refers to the process in which memory access instructions read data from the memory or write it into the memory. Memory access instructions are often one of the essential instruction types in the instruction set.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003eWrite Back (WB): WB refers to writing the instruction execution results to the general-purpose register set. At this stage, the CPU writes the execution result or memory access result to the register.\u003c/p\u003e\n\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003eThe benefit of a five-stage pipeline is its ability to execute multiple operations of one instruction within a single clock cycle, thereby enhancing the processing efficiency of the processor. A representative five-stage processor pipelining instruction execution sequence\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e]\u003c/sup\u003e is presented below.\u003c/p\u003e\n\u003cp\u003eAs shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e, on each cycle time, another instruction is fetched and begins its five-cycle execution. If an instruction is initiated every cycle time, the performance can be up to five times that of a non-pipelined processor. However, the pipelining mechanism depends on dependencies between instructions. For instance, if two instructions are data-dependent, they must be executed sequentially. As explained below, they cannot be executed simultaneously or overlap completely\u0026mdash;various dependencies impact the pipelining mechanism.\u003c/p\u003e\n\u003col\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eData dependencies(also called actual data dependencies).\u003c/strong\u003e The dependencies occur when the result of one instruction is used directly or indirectly by another.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eControl dependencies.\u003c/strong\u003e The dependency determines the order of instructions for each branch. Instructions inside a branch cannot be moved before the branch is evaluated.\u003c/p\u003e\n\u003c/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eName dependencies.\u003c/strong\u003e A name dependence occurs when two instructions use the same register or memory location, called a name, but there is no data flow between the instructions associated with that name.\u003c/p\u003e\n\u003c/li\u003e\n\u003c/ol\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\n\u003ch2\u003e2.2 Loop unrolling mechanism\u003c/h2\u003e\n\u003cp\u003eLoop unrolling, also known as loop unwinding, is a well-known compiler optimization that can lead to significant performance improvements\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e23\u003c/span\u003e]\u003c/sup\u003e. The effects of loop unrolling on CPU programs have been understood and described extensively in past work\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e26\u003c/span\u003e]\u003c/sup\u003e. A typical 1X1 Loop unrolling and 2X1 Loop unrolling instruction execution sequence is illustrated in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e.\u003c/p\u003e\n\u003cp\u003eLoop unrolling is a program transformation. The basic idea of loop unrolling is creating multiple copies of the loop body\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e27\u003c/span\u003e]\u003c/sup\u003e to perform various iterations simultaneously. The quantity of copies is referred to as the unrolling factor. A programmer can perform this conversion manually or through an optimizing compiler. The objective of loop unrolling is to enhance a program's performance. Loop unrolling can enhance program performance in two primary ways. Firstly, it minimizes the number of operations that do not directly impact the program outcome, such as loop index computations and conditional branching. Secondly, it offers a method to modify the code further and decrease the number of operations within the overall computational critical path. However, excessive unrolling may impair performance due to increased register pressure and instruction cache misses\u003csup\u003e[\u003cspan class=\"CitationRef\"\u003e27\u003c/span\u003e]\u003c/sup\u003e. Consequently, when implementing loop unrolling technology, evaluating its merits and drawbacks is crucial based on the specific context and choosing an appropriate loop unrolling coefficient (i.e., the number of times the identical code appears in the loop) to strike a balance between program size and execution speed.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"3. Functional Function","content":"\u003cp\u003eThe traditional method of executing conditional operations involves conditional control transfers, where the program follows a specific execution path based on whether the condition is satisfied. This mechanism is straightforward and adaptable in programming, requiring only a single judgment statement for implementation. However, for modern processors, this may lead to significant inefficiencies. As previously mentioned, processors attain high performance through pipelining; contemporary processors employ branch prediction to enable the instruction pipeline to execute persistently. Upon a misprediction, the pipelining must guarantee that the instruction execution after the mispredicted branch does not materialize, and the pipelining must be restarted at the accurate branch address, markedly diminishing the efficiency of pipelining execution. This paper mainly presents a Functional Function that can reduce the instruction execution efficiency problem caused by control hazards in the pipelining by optimizing branch selection. The execution method of the Functional Function is similar to the Fork function. The difference is that the Functional Function treats one branch in the branch sequence (called a true branch) as a path for the sequential execution of instructions and the other branches (called false branches) as paths chosen for execution. When the logical value is unsatisfied, the program switches the true and false branches through conditional transmission statements to ensure the program is correct. The instruction execution of the Functional Function flow diagram is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e.\u003c/p\u003e \u003cp\u003eFor branch instructions, in an abstract sense, the Functional Function divides the branch into true and false branches, employing conditional operations to calculate values and ultimately utilizing these values to update the program state. Unlike branch prediction employed in conditional jump instructions, Functional Function selectively updates the program state via conditional statements. For instance, Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e displays the instruction sequence for a Functional Function and a conditional jump function. The Functional Function instructions are executed sequentially, sans any branch jump instructions. Conversely, the conditional jump function executes the program via branch jumps.\u003c/p\u003e "},{"header":"4. Experimental results and analysis","content":"\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\n \u003ch2\u003e4.1 Experimental Setup\u003c/h2\u003e\n \u003cp\u003eThe experimental environment is Windows 11 operating system, gcc (x86_64-win32-sjlj-rev0, Built by MinGW-W64 project) 8.1.0, Visual Studio Code, GNU cross-toolchain and Intel VTune Profiler 2024.0.1. The experiment is divided into two parts, namely, pass-by-value and pass-by-address. In the pass-by-value experiment, two arrays, A and B, are set up, and the absolute value of the difference between the two is assigned to array A. In the pass-by-address experiment, two distinct addresses are configured, and the program transfers data to these addresses through function calls.\u003c/p\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e illustrates the experimental flow. The first step is to identify the code objects, followed by the metrics used for performance evaluation in the experiment. Although the proposed method applies to various conditional jump branches, this paper exemplifies common conditional jump functions because common conditional jump functions are typically more prevalent in programs. The experiment tests different common conditional jump functions, aiming to verify the actual advantages of Functional Function by testing various types of jump codes. In order to more conveniently observe the execution status of instructions inside the program, the experiment leverages the gcc compiler to parse the assembly instructions of the program\u0026rsquo;s high-level language. In addition, when analyzing program performance in subsequent stages, Intel Vtune Profiler will also conduct a comprehensive analysis of the assembly instructions.\u003c/p\u003e\n \u003cp\u003eThe data generated by the experiment are collected and analyzed through the Intel VTune Profiler performance analyzer. Utilizing the Intel VTune Profiler performance analyzer enables the generation of numerous performance analysis metrics. In this paper, three of the crucial metrics of the Intel VTune Profiler are employed in a comparative analysis of program performance: 1) CPI Rate. Cycles per Instruction Retired, or CPI, is a fundamental performance metric indicating how much time each executed instruction took in units of cycles. The smaller the CPI value, the faster the processor execution efficiency. 2) Pipeline Utilization. The Pipeline Utilization metric represents the Pipeline Slots fraction utilized by practical work, meaning the issues that are eventually completed. 3) Bad Speculation. Bad Speculation represents a Pipeline Slots fraction wasted due to incorrect speculations.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec8\" class=\"Section2\"\u003e\n \u003ch2\u003e4.2 Experimental Results\u003c/h2\u003e\n \u003cp\u003e\u003cstrong\u003ePart 1. Pass-by-value experiment\u003c/strong\u003e\u003c/p\u003e\n \u003cp\u003eInstruction-level parallelism was incorporated into the experiment, and the 2X1 loop unrolling mechanism was employed to enhance the program\u0026apos;s performance further. The experiment entailed data analysis of three methods: 1) 1X1FF, the Functional Function sans loop unrolling; 2) 2X1FF, the Functional Function with 2X1 loop unrolling; and 3) 2X1JMP, the 2X1 loop unrolling conditional jump function.\u003c/p\u003e\n \u003cp\u003eResults are summarized in Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e and Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e. The execution efficiency of the 2X1FF ranks highest among the three, followed by the 1X1FF, and the lowest efficiency is attributed to the 2X1JMP. When FF is used, as illustrated in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e, the execution efficiency of the 2X1FF surpasses that of the 1X1FF, and the runtime of the former program spans from 110 ms to 125 ms, whereas the latter remains within the range of 140 ms to 160 ms. The only difference between the two is the loop unrolling factor; as mentioned, employing functionalities of loop unrolling can lessen the calculations on the critical path, thereby enhancing the program\u0026apos;s efficiency, which is the main reason for this difference. Furthermore, both programs\u0026apos; pipeline utilization, Bad Speculation, and CPI rates are similar. What is different from the Functional Function is the conditional jump function.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab1\" border=\"1\"\u003e\n \u003ccaption\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eData indicators for three methods (The experiment carried out 600 data collections on three methods and randomly selected 100 of the data to form a table)\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003emethods\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eProgram Time(s)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eCPI\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePipeline Utilization\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eBad Speculation\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e2X1FF\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e12.797\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.216\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e90.3%\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e1.2%\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e1X1FF\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e15.951\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.23\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e81.6%\u003c/strong\u003e\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e1.3%\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e2X1JMP\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e22.985\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e0.326\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e\u003cstrong\u003e69.3%\u003c/strong\u003e\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e2.8%\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eAs seen from Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e, when 2X1JMP is used, whether the 1X1FF or the 2X1FF compared with the 2X1 JMP, its execution efficiency is improved hugely. The Program Time of the 2X1JMP is nearly twice that of the 2X1FF\u0026mdash;the Program Time of the former ranges from 200 ms to 220 ms. Moreover, as shown in Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e, The Pipeline Utilization of the 2X1FF increased by about 20% compared with the 2X1JMP, the Bad Speculation rate decreased from 2.8\u0026ndash;1.2%, and the CPI rate decreased from 0.326 to 0.216. The main reason for this difference in performance is the impact of branch prediction on the program, which is also encountered in the second experiment. The impact caused by branch prediction is mainly attributed to two points:\u003c/p\u003e\n \u003cp\u003e1) Pipeline execution efficiency. The performance improvement of branch prediction is based on the correct pipeline execution. As mentioned above, Functional Function execute branch instructions sequentially without branch prediction. This prediction further improves the pipeline utilization, and the conditional jump function pair improves the pipeline utilization through branch prediction. If the prediction is wrong, the pipeline efficiency will inevitably decrease. For example, an ideal 5-stage pipeline and an actual running 5-stage pipeline are given below to illustrate the impact of branch prediction on pipeline processors, as shown in Figs. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e and \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e. A slot represents a pipeline stage, Code that executes ten cycles.\u003c/p\u003e\n \u003cp\u003e2) Instruction-level parallelism, the number of CPU cores used in the experiment is 8, meaning that eight parallel instructions can be executed simultaneously. If the branch is mispredicted, then the instruction pipeline of the conditional jump function will be re-executed, that is, using a different approach for the same program; loop unrolling may improve program performance on 2X1FF but may have side effects on 2X1JMP.\u003c/p\u003e\n \u003cp\u003eIn an ideal pipeline processor, one instruction will be completed during Instruction Streaming for every clock cycle unless a Bad Speculation occurs. When a branch prediction error occurs, the pipeline execution deviates from the scenario above, reducing the pipeline\u0026apos;s execution efficiency. As shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e below, twenty out of the fifty slots become stalled, resulting in a microarchitectural pipeline utilization of only 60%.\u003c/p\u003e\n \u003cp\u003eIn conclusion, the impact of branch prediction on processor performance can be seen from the above example. the Bad Speculation of the pipeline for these three methods 2X1FF, 1X1FF and 2X1JMP are 1.2%, 1.3%, and 2.8%, respectively. The pipeline utilization rates of the three are 90.3%, 81.6%, and 69.3%, respectively. It can be seen that using Functional Function, Bad Speculation decreased by about 1.5%, and the utilization of the pipeline increased by about 20%.\u003c/p\u003e\n \u003cp\u003e\u003cstrong\u003ePart 2. Pass-by-address experiment\u003c/strong\u003e\u003c/p\u003e\n \u003cp\u003eUnlike the pass-by-value experiment, the pass-by-address experiment is more intricate. This approach necessitates function calls to various addresses, resulting in a corresponding increase in the program\u0026apos;s execution time. In addition, since address transfer involves operations on the stack and needs to be run on the stack, stack-related operations are required, which may increase the overall execution time of the program. Considering the factors mentioned above, the duration of the address transfer experiment might escalate, and the precise execution time will be derived from the experimental data.\u003c/p\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e and Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e summarize the results of the three methods. As anticipated, the collective execution time of the three methods escalated. The 2X1FF remains the most efficient, with a running time between 200 ms and 220 ms, followed by the 1X1FF, with a running time between 250 ms and 270 ms, with the 2X1JMP still ranking as the least rapid; the Program Time hovers at 370 ms. When the FF is used, the Program Time trend of the Functional Function can be seen in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e; whether the 2X1FF or the 1X1FF, the Program Time has increased, and its running trend has mostly stayed the same compared with the first experiment. This can be attributed to the fact that for Functional Function, the main impact on program execution performance is using unrolling factors in the unrolling mechanism.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab2\" border=\"1\"\u003e\n \u003ccaption\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eData indicators for three methods (The experiment carried out 600 data collections on three methods and randomly selected 50 of the data to form a table)\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003emethods\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eProgram Time(s)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eCPI\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePipeline Utilization\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eBad Speculation\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e2X1FF\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e10.630\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.320\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e63.4%\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.4%\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e1X1FF\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e10.891\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.374\u003c/p\u003e\n \u003c/th\u003e\n \u003cth rowspan=\"2\" align=\"left\"\u003e\n \u003cp\u003e60.8%\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0.7%\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e2X1JMP\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e17.273\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e0.532\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e41%\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e2.1%\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eWhen 2X1JMP is used, the execution time of the program has increased significantly. The Program Time is still about two times that of 2X1FF. However, its running trend remains stable. Compared with 2X1JMP, as shown in Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e, The pipelining utilization of the 2X1FF increased by about 20%, the Bad Speculation rate decreased from 2.1\u0026ndash;0.4%, and the CPI rate decreased from 0.532 to 0.320. Based on the above experimental data analysis, two reasons exist, similar to the first experiment.\u003c/p\u003e\n \u003cp\u003e1) program execution sequence, as mentioned above, the difference between 2X1FF and 2X1JMP is that Functional Function do not require branch prediction, and sequential execution avoids The impact of branch prediction on pipeline performance. The reason for Bad Speculation in 2X1FF is due to the conditional test of program loops;\u003c/p\u003e\n \u003cp\u003e2) Loop unrolling mechanism. The improvement of program performance by loop unrolling is based on the correct execution sequence of the program. If the program is executed according to the wrong instruction sequence, then all the work done is in vain. In other words, for the same program, loop unrolling may improve program performance on 2X1FF but may have side effects on 2X1JMP.\u003c/p\u003e\n \u003cp\u003eIn conclusion, As shown in Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e above, the Bad Speculation of the three methods 2X1FF, 1X1FF, and 2X1JMP is 0.4%, 0.7%, and 2.1%, respectively. The Pipeline Utilization rates are 63.4%, 60.8%, and 41% respectively. CPI rates are 0.320, 0.374, and 0.532. The utilization of the pipeline is increased by about 20%, and the accuracy of branch prediction, as shown in the experimental data, is increased by about 1.5%.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"5. Conclusions and further work","content":"\u003cp\u003eThis paper introduces a Functional Function. Functional Function is derived from the Fork function, and its operating mechanism is similar to the Fork function. When a conditional jump instruction is encountered, the program executes the current instruction sequentially, branches the current instruction, and selectively updates the program status according to the condition code, thereby avoiding the proportion of Bad Speculation in the program and enhancing the efficiency of the pipelining. Whether the pass-by-value experiment or the pass-by-address experiment, the Functional Function significantly outperformed the other existing methods in terms of performance and efficiency, including average Pipeline utilization rate, CPI rate, and Bad Speculation rate. Because of its robust performance, low program time, and the ability to give stable performance over various jump functions, the Functional Function is a viable solution for control hazards in the pipelining.\u003c/p\u003e \u003cp\u003eHowever, the limitation of the experiment lies in the fact that the Intel user guide lists four factors that could affect the program's efficiency. In this study, only the impact of Bad Speculation is examined (Bad Speculation is most frequently due to branch misprediction), while the other three factors still need to be considered. Future research will delve deeper into the analysis of the remaining three factors.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eFunding\u003c/h2\u003e \u003cp\u003eThis study was funded by [Natural Science Foundation of Heilongjiang Province, China] (Grant numbers [LH2019F027]).\u003c/p\u003e\u003ch2\u003eConflicts of interest/Competing interests\u003c/h2\u003e \u003cp\u003eThere are no Competing Interests, and the authors have no financial or proprietary interests in any material discussed in this article.\u003c/p\u003e \u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eAuthor Fei Gao completed the manuscript, pictures and tables of the entire paper.Author Jingbo Shao completed review of the manuscript.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eBryant, Randal E. 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Therefore, the execution efficiency of the pipelining is one of the critical factors impacting processor performance. The main factors that impact pipelining efficiency are data hazards caused by data dependencies and control hazards caused by control dependencies. Regarding the control hazards present in pipelining, although a few technologies are mentioned in the literature for addressing them, they frequently require significantly high latency and may not guarantee optimal quality. This paper introduces the Functional Function (FF), derived from the Fork function; by selectively executing branch instructions based on previous calculation results, the Functional Function can minimize control dependencies in pipelining and enhance the utilization of the processor pipelining via optimizing branch selection. The Intel VTune Profiler program analyzer was employed for data collection and analysis during the experiment to facilitate an unbiased comparison with existing methods. The experimental results indicate that the Functional Function significantly outperforms the existing methods, primarily reflected in the Pipeline utilization rate, CPI rate, and Bad Speculation rate. Furthermore, the utilization of the pipelining is enhanced by approximately 20%, accompanied by a nearly 1.5% increase in branch prediction accuracy compared with existing methods.\u003c/p\u003e","manuscriptTitle":"Minimizing control dependencies of pipelining through optimizing branch selection","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-04-30 11:28:15","doi":"10.21203/rs.3.rs-4315205/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"checksComplete","content":"","date":"2024-04-25T00:21:02+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2024-04-25T00:21:02+00:00","index":"","fulltext":""},{"type":"submitted","content":"Software Quality Journal","date":"2024-04-24T03:20:39+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"software-quality-journal","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"sqjo","sideBox":"Learn more about [Software Quality Journal](http://link.springer.com/journal/11219)","snPcode":"11219","submissionUrl":"https://submission.nature.com/new-submission/11219/3","title":"Software Quality Journal","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"837d5e39-0ce4-43a2-a4c8-080e945a3e19","owner":[],"postedDate":"April 30th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2024-04-30T11:28:15+00:00","versionOfRecord":[],"versionCreatedAt":"2024-04-30 11:28:15","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4315205","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4315205","identity":"rs-4315205","version":["v1"]},"buildId":"rHA-KDH7Qsr4HCuvH75dn","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}