An efficient power optimization method for fixed polarity Reed-Muller logic circuits based on a multi-strategy gray wolf optimization algorithm

Abstract Optimization of power consumption has emerged as a pivotal objective in the domain of integrated circuit design. The optimization of Fixed Polarity Reed-Muller (FPRM) circuit power entails addressing a combinatorial optimization challenge that seeks to identify the optimal polarity configuration within the polarity optimization space, ultimately minimizing power consumption. In the current methodologies for FPRM circuit power optimization, drawbacks such as suboptimal efficiency and subpar results are evident. In response to these challenges, we introduce a novel Multi-Strategy Grey Wolf Optimization (M-GWO) algorithm. M-GWO leverages chaotic mapping for population initialization, integrates a global search optimizer inspired by the stochastic and spiral search behaviors of the whale optimization algorithm, and incorporates a local depth-exploiting optimizer based on the running and predation behaviors of the wolf pack optimization algorithm. Subsequently, we present a power optimization approach for FPRM logic circuits, utilizing the M-GWO algorithm. This method employs M-GWO to explore the polarity optimization space of FPRM circuits, seeking the optimal polarity configuration with minimal power consumption to achieve circuit power optimization. Experimental validation, conducted on the Microelectronics Center of North Carolina Benchmark test circuits and the Institute of Electrical and Electronics Engineers Congress on Evolutionary Computation benchmarks test functions, attests to the efficacy, superiority, and universality of the M-GWO.