Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance Jeetendra Singh, Debapriya Chakraborty, Naveen Kumar This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-330678/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 5 You are reading this latest preprint version Abstract In this paper, a dopingless nanotube field-effect transistor (DL-NT-FET) has been proposed and its performance analysis is done using a technology computer-aided design (TCAD) tool, ATLAS provided by Silvaco. The elimination of doping is brought in by the application of the charge-plasma (CP) technique. A comparative examination of transfer characteristics (I D -V GS ), transconductance (g m ), gate capacitances (C gs and C gd ), output characteristics (I D -V DS ), output conductance (g ds ), average subthreshold slope (AVSS), the threshold voltage (V t ), the ratio of on-current to off-current (I ON /I OFF ) and on-current has been made by varying the channel length (Lg), radius (R), gate work function (Φ), and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater I ON /I OFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The I OFF value increases significantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. The I ON degrades 15% by increasing the temperature from 200K to 400K. The output conductance g ds also degrades on increasing the temperature. A proliferation of 39% is observed in the C gs at the V GS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the C gd for the same increment in the channel length. Materials Chemistry Materials Engineering nanotube FET Dopingless charge plasma output conductance average subthreshold slope and gate capacitance Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Introduction The complementary metal-oxide-semiconductor (CMOS) technology has advanced through the decades to dominate the semiconductor industry with excellent features of low power and cost, dense packaging, and high-speed devices that are continuously scaled down in size [1-3]. When it comes to designing RF/analog circuits in the nanometer regime, several challenges have been encountered due to strict process requirements to maintain sharp source/drain region and short channel effects (SCEs) [4-7]. The junctionless field-effect transistor (JLFET) solves many of the issues related to SCEs but still, it suffers from poor carrier mobility due to high channel doping, which leads to transconductance/gain degradation and hence low ON current [8, 9]. Dopingless nanotube FET (DL-NT-FET) can provide a solution by making use of the charge-plasma (CP) technique in which abrupt doped source and drain regions are formed in the intrinsic substrate with the help of suitable work function metal electrode or poly-Si electrode at the high temperature [10-12]. The gate-all-around (GAA) and shell-gated nanotube provide strong gate control over the channel carrier which results in enhanced surface inversion and hence superior drain current [13, 14]. Hence, the proposed device exploits both the advantages of GAA structure (i.e. allowing better electrostatics and reduced SCEs) and dopingless configuration (like reduced random dopant fluctuations(RDFs), less mobility degradation, better gm) [15, 16]. Besides the collective merit of GAA and dopingless nanotube, the impact of temperature on the performance parameters of the proposed DL-NT-FET is the first time investigated along with other design parameters. In this article, a dopingless nanotube field-effect transistor (DL-NT-FET) is designed and its various performance parameters; transfer characteristics (ID-VGS), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (ID-VDS), output conductance (gds), average subthreshold slope (AVSS), the threshold voltage (Vt), the ratio of on-current to off-current (ION/IOFF) are investigated. The impact of nanotube radius (R), channel length (Lg), and gate work function variations on the performance parameters are examined to achieve high performance. The various performance parameters are also evaluated at a different temperature to study the temperature-dependent variability. Device structure The 2-D structure of the proposed device is shown in Fig. 1(a) whereas the 3-D structure of the same is depicted in Fig. 1(b). The source, channel, and drain regions have been formed on an intrinsic Si body with the radius being 10nm and the silicon thickness being 7nm leaving the inner oxide thickness. CP technique is used to establish the source and drain regions of this dopingless device [17]. The gate oxide is made of SiO2 and is 2nm in thickness. Both drain and source lengths are 30nm while the channel length is 20nm. P-type polysilicon (workfunction= 3.9eV) is used in forming the source and drain core-electrodes. The gate contact is also made of polysilicon (workfunction=4.6eV). The poly-Silicon core-electrodes help to induce N+ regions at the source and drain sides. A SiO2 layer surrounds these electrodes followed by an intrinsic Silicon layer in the core. Poly-silicon electrodes are also attached at the bottom and top of this layer. The second layer of SiO2 is muffled on all sides of the Si layer. A shell consisting of polysilicon (work function=4.6 eV) has been wrapped over the oxide layer to form a contact for the gate. Aluminum is generally preferred for gate material of MOSFET but here the polysilicon is mainly utilized because polysilicon composition matches with the channel bulk-silicon and therefore offers low threshold voltage as compared to that of metal gate material [18]. The proposed device is simulated utilizing Silvaco TCAD to analyze the various results. To account for accurate mobility evaluation in the channel, the Lombardi mobility model along with concentration and field-dependent mobility models are considered. Shockley–Read–Hall (SRH) and Auger generation-recombination models are contemplated to acknowledge the lifetime of constant minority carriers and large current density. The simulation temperature was initially 300K for the proposed device and then observations were also taken at different temperatures to compare the effect on different device parameters. The variation of the electron-hole concentration and the energy band diagram of the proposed DL-NT-FET is illustrated in Fig. 2 for OFF-state conditions (VGS=0V and VDS=1V) and ON-state conditions (VGS=1V and VDS=1V) respectively. As it can be noticed from Fig. 2(a) that the concentration of the electrons in the channel region goes high from the low and the holes concentration goes low from high when the device comes into the ON-state condition from OFF-state condition due to the formation of the inversion layer of the electrons and depletion of the holes from the channel [19]. The energy levels of the conduction band and valance band are high in the OFF-state condition as compared to the energy levels of the conduction band and valance band in the ON-state condition Fig. 2(b). The bands bend downwards in ON-state because when a positive gate voltage is applied in the polysilicon gate, the Fermi potential (potential between Fermi level and intrinsic Fermi level) decreases due to an increase in the surface potential, and this result in large electron carriers in the intrinsic (initially) channel region [20]. The introduction of these high electrons shifts the conduction band down towards the Fermi level. Simultaneously the holes are also de-voided from the channel due to positive potential on the gate therefore the valance band also shifts downwards away from the Fermi level. Fig. 3 depicts the variation of electric field and potential in the OFF-state and ON-state conditions. It can be seen from Fig. 3(a) that the electric field uplifts in the interface of source-channel and suppressed at the interface of channel-drain when the device comes in the ON-state condition from the OFF-state, this is due to the application of the positive gate voltage along with the drain voltage [21]. The low electric field at the channel-drain interface indicates less control of the drain to the channel and hence the DL-NT-FET implies low short channel effects. On the other hand, the surface potential goes high in the ON-state as intended due to more bending in the energy bands, at this stage the surface becomes doubled that of Fermi potential. Fig. 4 shows the variation of the electron mobility and electron-hole pair recombination rate of the DL-NT-FET in OFF-state and On-state conditions. The electron mobility goes lower at the source-channel interface and becomes higher at the channel-drain interface Fig. 4(a). It is because the electric field is higher at the source-channel interface and lower at the channel-drain interface as is seen in Fig. 3(a). It can be observed from Fig. 4(b) that the recombination rate of the electron-hole pairs is zero in the channel region ON-state condition of the device channel region. The drain current variation with channel length is plotted in Fig. 5(a) and its extracted performance parameters are listed in Table 1, it is noted that on increasing the channel length the ION/IOFF ratio enhances while the threshold voltage and Average sub-threshold slope (AVSS) of the DL-NT-FET reduce. An augmentation of 2 orders in the ION/IOFF ratio and a reduction of 22% and 13% in the threshold voltage and AVSS respectively have been recorded on increasing the channel length from 15 nm to 35 nm. The impact of the gate work function variation on the transfer characteristics of the DL-NT-FET is shown in Fig. 5(b) and various device properties that are extracted from its transfer characteristics are mentioned in Table 2. It can be observed that the OFF-current (IOFF) reduces significantly as compare to the ON-current (ION) and therefore the ION/IOFF ratio enhances on increasing the gate work function. The threshold voltage also decreases on augmenting the gate work function whereas the AVSS initially decreases up to a work function of 4.5eV but then starts increasing. Six orders increment in the ION/IOFF ratio and an 81% reduction in the threshold voltage has been observed when the gate work function is augmented from 4.3eV to 4.7eV. Fig. 5(c) exhibits the variation of ID-VGS characteristics with temperature and the various performance parameters at different temperatures are summarized in Table 3. The IOFF value increases significantly on increasing the temperature while the small degradation in the ION has been noticed as a result of mobility degradation and velocity saturation. And therefore 6 orders diminution in the ION/IOFF ratio is noticed when the temperature is increased from 200 K to 450 K. threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92% while the AVSS rises 114% on increasing the temperature from 200K to 450K. The effect of nanotube radius on the transfer characteristics and hence on various performance parameters are depicted in Fig. 5(d) and Table 4 respectively. On enhancing the radius of the nanotube of the DL-NT-FET, the ION and IOFF both are increasing but the IOFF increases more rapidly as compare to the ION and therefore the ION/IOFF ratio reduces. The ION/IOFF ratio is degraded by 3 orders on augmenting the radius from 8 nm to 16 nm. The threshold voltage and AVSS are increased by increasing the radius of the nanotube; there is an increment of 47% in threshold voltage whereas an increment of 19% in the AVSS has been observed while increasing the radius of the nanotube from 8 nm to 16 nm. Table 1 Effect of gate work-functions on various device performance parameters of DL-NT-FET Gate-work function (eV) AVSS (mV/decade) Threshold voltage(V) I ON (A/m) I OFF (µA/m) I ON /I OFF 4.3 70.7 0.494785 41.29 930287 44.3891 4.4 68.7 0.394785 38.03 52766.2 720.727 4.5 68.3 0.294785 34.53 1935.24 17845.3 4.6 68.8 0.194785 30.93 64.15 482264 4.7 71 0.0947849 27.21 2.04 13316400 Table 2 Various device performance parameters at the different channel length of nanotube of DL-NT-FET Channel length (nm) AVSS (mV/decade) Threshold voltage(V) I ON (A/m) I OFF (µA/m) I ON /I OFF 15 74.58 0.219144 31.15 367.3 84711.9 20 68.8 0.194785 30.93 64.15 482264 25 67.7 0.18286 30.81 21.95 1403350 30 66.0 0.176297 30.70 11.26 2725660 35 64.57 0.170009 30.57 7.38 4141140 Table 3 Variation in the device performance parameters at various temperature conditions Temperature (K) AVSS (mV/decade) The threshold voltage(V) I ON (A/m) I OFF (A/µm) I ON /I OFF 200 48 0.14432 31.9 0.024 1287990000 250 58.6 0.168484 31.44 2.68 11714000 300 68.8 0.194785 30.93 64.15 482264 350 80.7 0.222111 30.40 637.585 47691.7 400 89.2 0.249834 29.83 3624.34 8232.48 450 103.3 0.277697 29.22 14074.1 2076.18 Table 4 Various device performance parameters at the different radius of nanotube of DL-NT-FET Radius(nm) AVSS (mV/decade) The threshold voltage(V) I ON (A/m) I OFF (µA/m) I ON /I OFF 8 67.5 0.178221 24.17 13.05 1852290 10 68.8 0.194785 30.93 64.15 482264 12 72.2 0.212351 37.72 298.04 126582 14 78.1 0.231078 44.63 1308.17 34118 16 80.3 0.250602 51.70 5366.02 9635.24 Fig. 6 (a) shows the variation of transconductance with VGS at different channel lengths which is a specific figure of merit of a FET and it measures the precision in the conversance of gate voltage into the current. It is noticed from Fig. 6(a) that the transconductance increases with the increasing channel length (up to 25 nm) then it remains constant. The transconductance increases with the channel length because of higher change in drain current is obtained at the large channel length with a small change in gate voltage. At the 25 nm channel length, the obtained value of the gm is 5.2x10-5 S/µm at the gate voltage of 0.45 V. Fig. 6(b) depicts the changes in the gate to source capacitance (Cgs) and drain to source capacitance (Cgd) with the gate voltage. A proliferation of 39% is observed in the Cgs at the VGS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the Cgd for the same increment in the channel length. The behavior of drain current concerning VDS for different values of VGS at the channel length of 20 nm and 35nm has been shown in Fig. 7(a), where it is again found that ID is more for channel length 20nm than that of for channel length 35nm. Moreover, it is also noticed that at smaller VGS, the saturation in the drain current occurs earlier as compare to the large VGS; this is because of limited space-charge inversion in the channel which implies greater gate control over the channel. Fig. 7(b) shows how the output conductance (gds) varies with VDS where VGS is fixed at 1V and readings for 20nm and 35nm channels are taken. It is well known that gds is a crucial parameter in determining the intrinsic gain of a device and for better gain, it should be low. It can be seen from Fig. 7(b) that its value does not change with the channel length and the obtained value of the gds­ for the designed DL-NT-FET is 3.4x10-5 (S/µm). The output characteristics (ID-VDS) at the various temperatures are plotted in Fig. 8(a) and it is observed that the drain current decreases with an increase in the temperature. The ID decreases with the temperature because scattering phenomena increase with the temperature and this results in low carrier mobility in the channel and hence low drain current at the higher temperature [22]. The ID degrades 15% on increasing the temperature from 200K to 400 K. Fig. 8(b) shows the variation of the output conductance (gds) with the VDS at different temperature and it is found that gds also degrades on increasing the temperature and it is due to the reduction of ID at the higher temperature. The impact of the nanotube radius in the output characteristics and output transconductance is plotted in Fig. 9(a) and Fig. 9(b) respectively and it is found that both the parameters are increasing with augmenting the radius. The ID enhances the increasing radius because a large radius renders large space charges in the inversion condition and the large drain current implies the higher output transconductance. An increment of 100% in the drain current and 137% in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm. Conclusion This manuscript covers a proposed dopingless nanotube FET structure. Different characteristics of the device have been examined by TCAD simulated results. The obtained AVSS for 20nm channel length, the radius of 10nm simulated at 300K is 68.80mV/decade which has much scope of improvement by optimization of the device. A comparative analysis of transfer characteristics (ID-VGS), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (ID-VDS), and output conductance (gds), has been made by varying the channel length (Lg), radius (R), gate work function (Φ) and temperature. An increment of 100% in the drain current and 137% in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm. The gate capacitances Cgs and Cgd are higher for the longer channel. On increasing the temperature from 300k to 400K, the output conductance is found to decrease as well as the drain current gets saturated to a lower value whereas, by decreasing temperature to 200K, the opposite happens. An augmentation of six orders in the ION/IOFF ratio and 81% reduction in the threshold voltage has been observed when the gate work function is enhanced from 4.3eV to 4.7eV. The ION/IOFF decreases with a temperature rise, there are 6 orders diminution in the ION/IOFF ratio is noticed when the temperature is increased from 200 K to 450 K. The threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92% while the AVSS rises 114% on increasing the temperature from 200K to 450K. The transconductance curve has the highest peak value for the longest channel. It can thus be concluded that, after a thorough investigation of the behavior of the proposed dopingless nanotube FET parameters under several variations, it can be well understood that there are a good number of challenges to get the optimized results. Declarations Funding statement: No funding was received to assist with the preparation of this manuscript. Conflict of Interest: The authors declare that they have no conflict of interest. Author contributions: All authors have equally participated in the preparing of the manuscript during implementation of ideas, findings results, and writing of the manuscript. Availability of data and material: current submission does not contain the pool data of the manuscript but the data used in the manuscript will be provided on request. Compliance with ethical standards: The Authors accepted principles of ethical standard and they have no conflict of interest. Consent to participate: Informed consent. Consent for Publication: Consent is granted. Acknowledgments: Not Applicable. References Huang, J.S.T., and Schrankler, J.W., 1987. Switching characteristics of scaled CMOS circuits at 77 K. IEEE transactions on electron devices , 34 (1), pp.101-106. Kong, L., Chen, Y. and Liu, Y., 2020. Recent progresses of NMOS and CMOS logic functions based on two-dimensional semiconductors. Nano Research, pp.1-16. Singh, J. and Raj, B., 2019. Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(6), pp.1322-1328. Pourghaderi, M.A., Pham, A.T., Ilatikhameneh, H., Kim, J., Park, H.H., Jin, S., Chung, W.Y., Choi, W., Maeda, S. and Lee, K.H., 2017. Universality of Short-Channel Effects on Ultrascaled MOSFET Performance. IEEE Electron Device Letters, 39(2), pp.168-171. Ribeiro, T.A. and Pavanello, M.A., 2020, February. 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Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Minor revisions 15 Apr, 2021 Reviews received at journal 24 Mar, 2021 Editor assigned by journal 23 Mar, 2021 Editor invited by journal 23 Mar, 2021 First submitted to journal 14 Mar, 2021 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-330678","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":18596121,"identity":"8413a3bf-b6c0-4496-a0aa-d6bcda950d86","order_by":0,"name":"Jeetendra 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1","display":"","copyAsset":false,"role":"figure","size":149220,"visible":true,"origin":"","legend":"(a) 2-D cross-sectional view of the proposed device (b) 3-D view of the proposed device","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/886fc63dbef09c553bf2178f.png"},{"id":7906574,"identity":"a8978d9d-5e98-4188-adc5-9c01d6d4ade7","added_by":"auto","created_at":"2021-04-12 14:23:06","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":61256,"visible":true,"origin":"","legend":"Variation of (a) Electrons and holes carrier concentration and (b) the energy band diagram of DL-NT-FET in OFF condition (VGS=0V and VDS=1V) and in ON condition (VGS=1V and VDS=1V), x coordinate shows the distance from the source to drain along the channel","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/4017e281989da63b3e0d22c0.png"},{"id":7906572,"identity":"a970d236-37cb-4a09-9a0d-44489f275763","added_by":"auto","created_at":"2021-04-12 14:23:06","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":41913,"visible":true,"origin":"","legend":"Variation of (a) Electric Field and (b) Potential of DL-NT-FET in OFF condition (VGS=0V and VDS=1V) and in ON condition (VGS=1V and VDS=1V), x coordinate shows the distance from the source to drain along the channel","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/afbcfc4ad750e140acc8fcbe.png"},{"id":7906995,"identity":"e55fca6e-7c7f-462c-8814-a12e6b330cf0","added_by":"auto","created_at":"2021-04-12 14:26:06","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":40769,"visible":true,"origin":"","legend":"Variation of (a) Electron Mobility and (b) Electro-hole recombination rate of DL-NT-FET in OFF condition (VGS=0V and VDS=1V) and in ON condition (VGS=1V and VDS=1V), x coordinate shows the distance from the source to drain along the channel","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/ef7b6f728b603e92a6b607a6.png"},{"id":7906999,"identity":"a3c4193a-d6dc-41c0-95c3-c48f24aa3303","added_by":"auto","created_at":"2021-04-12 14:26:07","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":77841,"visible":true,"origin":"","legend":"Variation of (ID-VGS) characteristics of the DL-NT-FET at VDS=1V for (a) the varying the channel length (Lg) (b) the varying the gate electrode work function (ΦG) (c) at various temperature (T), and (d) the varying the radius (R) of the DL-NT-FET.","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/c4bf25b3bd07d305645ec044.png"},{"id":7907523,"identity":"6b5139f9-457a-423d-80b4-f297734a552e","added_by":"auto","created_at":"2021-04-12 14:29:06","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":45209,"visible":true,"origin":"","legend":"Variation of (a) transconductance (gm) and (b) gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) with gate voltage at various channel length and VDS=1V","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/52dc33255cdafaf4f807304e.png"},{"id":7907000,"identity":"000cc22f-6677-432a-81d8-8ee23b2637f2","added_by":"auto","created_at":"2021-04-12 14:26:07","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":84167,"visible":true,"origin":"","legend":"(a) Output characteristics for channel lengths 20nm and 35nm at different VGS. (b) Output conductance vs VDS for channel lengths 20nm and 35nm at VGS=1V.","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/5ef660b791a1b661e448166f.png"},{"id":7907001,"identity":"9c865f62-7994-4bbc-bfae-9e282a6947a6","added_by":"auto","created_at":"2021-04-12 14:26:07","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":74577,"visible":true,"origin":"","legend":"Variation of (a) output characteristics (IDS-VDS) at different temperatures and (b) output conductance for different temperatures (both at VGS=1V) ","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/8fa06ec7685d65ec6586614a.png"},{"id":7906998,"identity":"6d72b1e7-a599-49a2-ac1d-0041d6fd0793","added_by":"auto","created_at":"2021-04-12 14:26:06","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":114843,"visible":true,"origin":"","legend":"(a) Output characteristics for different radius (b) Output conductance Vs. VDS for the different radius (both at VGS=1V)","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/27a6e20194642f9c992df8c1.png"},{"id":13685571,"identity":"ca3d0018-1ba1-4996-9c84-e3a8c8b42245","added_by":"auto","created_at":"2021-09-17 12:13:20","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":830566,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-330678/v1/5ec0aecf-1fd6-4688-be54-e97885b6cd9e.pdf"}],"financialInterests":"","formattedTitle":"Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance","fulltext":[{"header":"Introduction","content":"\u003cp\u003eThe complementary metal-oxide-semiconductor (CMOS) technology has advanced through the decades to dominate the semiconductor industry with excellent features of low power and cost, dense packaging, and high-speed devices that are continuously scaled down in size [1-3]. When it comes to designing RF/analog circuits in the nanometer regime, several challenges have been encountered due to strict process requirements to maintain sharp source/drain region and short channel effects (SCEs) [4-7]. The junctionless field-effect transistor (JLFET) solves many of the issues related to SCEs but still, it suffers from poor carrier mobility due to high channel doping, which leads to transconductance/gain degradation and hence low ON current [8, 9]. Dopingless nanotube FET (DL-NT-FET) can provide a solution by making use of the charge-plasma (CP) technique in which abrupt doped source and drain regions are formed in the intrinsic substrate with the help of suitable work function metal electrode or poly-Si electrode at the high temperature [10-12]. The gate-all-around (GAA) and shell-gated nanotube provide strong gate control over the channel carrier which results in enhanced surface inversion and hence superior drain current [13, 14]. Hence, the proposed device exploits both the advantages of GAA structure (i.e. allowing better electrostatics and reduced SCEs) and dopingless configuration (like reduced random dopant fluctuations(RDFs), less mobility degradation, better gm) [15, 16]. Besides the collective merit of GAA and dopingless nanotube, the impact of temperature on the performance parameters of the proposed DL-NT-FET is the first time investigated along with other design parameters.\u003c/p\u003e\n\u003cp\u003eIn this article, a dopingless nanotube field-effect transistor (DL-NT-FET) is designed and its various performance parameters; transfer characteristics (ID-VGS), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (ID-VDS), output conductance (gds), average subthreshold slope (AVSS), the threshold voltage (Vt), the ratio of on-current to off-current (ION/IOFF) are investigated. The impact of nanotube radius (R), channel length (Lg), and gate work function variations on the performance parameters are examined to achieve high performance. The various performance parameters are also evaluated at a different temperature to study the temperature-dependent variability.\u003c/p\u003e"},{"header":"Device structure","content":"\u003cp\u003eThe 2-D structure of the proposed device is shown in Fig. 1(a) whereas the 3-D structure of the same is depicted in Fig. 1(b). The source, channel, and drain regions have been formed on an intrinsic Si body with the radius being 10nm and the silicon thickness being 7nm leaving the inner oxide thickness. CP technique is used to establish the source and drain regions of this dopingless device [17]. The gate oxide is made of SiO2 and is 2nm in thickness. Both drain and source lengths are 30nm while the channel length is 20nm. P-type polysilicon (workfunction= 3.9eV) is used in forming the source and drain core-electrodes. The gate contact is also made of polysilicon (workfunction=4.6eV). The poly-Silicon core-electrodes help to induce N+ regions at the source and drain sides. A SiO2 layer surrounds these electrodes followed by an intrinsic Silicon layer in the core. Poly-silicon electrodes are also attached at the bottom and top of this layer. The second layer of SiO2 is muffled on all sides of the Si layer. A shell consisting of polysilicon (work function=4.6 eV) has been wrapped over the oxide layer to form a contact for the gate. Aluminum is generally preferred for gate material of MOSFET but here the polysilicon is mainly utilized because polysilicon composition matches with the channel bulk-silicon and therefore offers low threshold voltage as compared to that of metal gate material [18]. The proposed device is simulated utilizing Silvaco TCAD to analyze the various results. To account for accurate mobility evaluation in the channel, the Lombardi mobility model along with concentration and field-dependent mobility models are considered. Shockley\u0026ndash;Read\u0026ndash;Hall (SRH) and Auger generation-recombination models are contemplated to acknowledge the lifetime of constant minority carriers and large current density. The simulation temperature was initially 300K for the proposed device and then observations were also taken at different temperatures to compare the effect on different device parameters.\u003c/p\u003e\n\u003cp\u003eThe variation of the electron-hole concentration and the energy band diagram of the proposed DL-NT-FET is illustrated in Fig. 2 for OFF-state conditions (VGS=0V and VDS=1V) and ON-state conditions (VGS=1V and VDS=1V) respectively. As it can be noticed from Fig. 2(a) that the concentration of the electrons in the channel region goes high from the low and the holes concentration goes low from high when the device comes into the ON-state condition from OFF-state condition due to the formation of the inversion layer of the electrons and depletion of the holes from the channel [19]. The energy levels of the conduction band and valance band are high in the OFF-state condition as compared to the energy levels of the conduction band and valance band in the ON-state condition Fig. 2(b). \u0026nbsp;The bands bend downwards in ON-state because when a positive gate voltage is applied in the polysilicon gate, the Fermi potential (potential between Fermi level and intrinsic Fermi level) decreases due to an increase in the surface potential, and this result in large electron carriers in the intrinsic (initially) channel region [20]. The introduction of these high electrons shifts the conduction band down towards the Fermi level. Simultaneously the holes are also de-voided from the channel due to positive potential on the gate therefore the valance band also shifts downwards away from the Fermi level.\u003c/p\u003e\n\u003cp\u003eFig. 3 depicts the variation of electric field and potential in the OFF-state and ON-state conditions. It can be seen from Fig. 3(a) that the electric field uplifts in the interface of source-channel and suppressed at the interface of channel-drain when the device comes in the ON-state condition from the OFF-state, this is due to the application of the positive gate voltage along with the drain voltage [21]. The low electric field at the channel-drain interface indicates less control of the drain to the channel and hence the DL-NT-FET implies low short channel effects. On the other hand, the surface potential goes high in the ON-state as intended due to more bending in the energy bands, at this stage the surface becomes doubled that of Fermi potential.\u003c/p\u003e\n\u003cp\u003eFig. 4 shows the variation of the electron mobility and electron-hole pair recombination rate of the DL-NT-FET in OFF-state and On-state conditions. The electron mobility goes lower at the source-channel interface and becomes higher at the channel-drain interface Fig. 4(a). It is because the electric field is higher at the source-channel interface and lower at the channel-drain interface as is seen in Fig. 3(a). It can be observed from Fig. 4(b) that the recombination rate of the electron-hole pairs is zero in the channel region ON-state condition of the device channel region.\u003c/p\u003e\n\u003cp\u003eThe drain current variation with channel length is plotted in Fig. 5(a) and its extracted performance parameters are listed in Table 1, it is noted that on increasing the channel length the ION/IOFF ratio enhances while the threshold voltage and Average sub-threshold slope (AVSS) of the DL-NT-FET reduce. An augmentation of 2 orders in the ION/IOFF ratio and a reduction of 22% and 13% in the threshold voltage and AVSS respectively have been recorded on increasing the channel length from 15 nm to 35 nm. The impact of the gate work function variation on the transfer characteristics of the DL-NT-FET is shown in Fig. 5(b) and various device properties that are extracted from its transfer characteristics are mentioned in Table 2. It can be observed that the OFF-current (IOFF) reduces significantly as compare to the ON-current (ION) and therefore the ION/IOFF ratio enhances on increasing the gate work function. The threshold voltage also decreases on augmenting the gate work function whereas the AVSS initially decreases up to a work function of 4.5eV but then starts increasing. Six orders increment in the ION/IOFF ratio and an 81% reduction in the threshold voltage has been observed when the gate work function is augmented from 4.3eV to 4.7eV. Fig. 5(c) exhibits the variation of ID-VGS characteristics with temperature and the various performance parameters at different temperatures are summarized in Table 3. The IOFF value increases significantly on increasing the temperature while the small degradation in the ION has been noticed as a result of mobility degradation and velocity saturation. And therefore 6 orders diminution in the ION/IOFF ratio is noticed when the temperature is increased from 200 K to 450 K. threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92% while the AVSS rises 114% on increasing the temperature from 200K to 450K. The effect of nanotube radius on the transfer characteristics and hence on various performance parameters are depicted in Fig. 5(d) and Table 4 respectively. On enhancing the radius of the nanotube of the DL-NT-FET, the ION and IOFF both are increasing but the IOFF increases more rapidly as compare to the ION and therefore the ION/IOFF ratio reduces. The ION/IOFF ratio is degraded by 3 orders on augmenting the radius from 8 nm to 16 nm. The threshold voltage and AVSS are increased by increasing the radius of the nanotube; there is an increment of 47% in threshold voltage whereas an increment of 19% in the AVSS has been observed while increasing the radius of the nanotube from 8 nm to 16 nm.\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eTable 1\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eEffect of gate work-functions on various device performance parameters of DL-NT-FET\u003c/p\u003e\n\u003ctable style=\"margin-left: auto; margin-right: auto;\" border=\"1\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003eGate-work function (eV)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003eAVSS (mV/decade)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eThreshold voltage(V)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e (A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eI\u003csub\u003eOFF\u003c/sub\u003e (\u0026micro;A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e/I\u003csub\u003eOFF\u003c/sub\u003e\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003e4.3\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003e70.7\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e0.494785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003e41.29\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e930287\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e44.3891\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003e4.4\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003e68.7\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e0.394785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003e38.03\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e52766.2\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e720.727\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003e4.5\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003e68.3\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e0.294785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003e34.53\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e1935.24\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e17845.3\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003e4.6\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003e68.8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e0.194785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003e30.93\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e64.15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e482264\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"88\"\u003e\n\u003cp\u003e4.7\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"87\"\u003e\n\u003cp\u003e71\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e0.0947849\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"74\"\u003e\n\u003cp\u003e27.21\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e2.04\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e13316400\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\n\u003cp\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003e\u0026nbsp;Table 2\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eVarious device performance parameters at the different channel length of nanotube of DL-NT-FET\u0026nbsp;\u003c/p\u003e\n\u003ctable style=\"margin-left: auto; margin-right: auto;\" border=\"1\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003eChannel length (nm)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eAVSS (mV/decade)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eThreshold voltage(V)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e (A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003eI\u003csub\u003eOFF\u003c/sub\u003e (\u0026micro;A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e/I\u003csub\u003eOFF\u003c/sub\u003e\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003e15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e74.58\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.219144\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e31.15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003e367.3\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e84711.9\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003e20\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e68.8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.194785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e30.93\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003e64.15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e482264\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003e25\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e67.7\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.18286\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e30.81\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003e21.95\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e1403350\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003e30\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e66.0\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.176297\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e30.70\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003e11.26\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e2725660\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"63\"\u003e\n\u003cp\u003e35\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e64.57\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.170009\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e30.57\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"76\"\u003e\n\u003cp\u003e7.38\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"68\"\u003e\n\u003cp\u003e4141140\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\n\u003cp style=\"text-align: center;\"\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eTable 3\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eVariation in the device performance parameters at various temperature conditions\u003c/p\u003e\n\u003ctable style=\"margin-left: auto; margin-right: auto;\" border=\"1\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003eTemperature\u003c/p\u003e\n\u003cp\u003e(K)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003eAVSS (mV/decade)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eThe threshold voltage(V)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e (A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eI\u003csub\u003eOFF\u003c/sub\u003e (A/\u0026micro;m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e/I\u003csub\u003eOFF\u003c/sub\u003e\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e200\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e48\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.14432\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e31.9\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.024\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e1287990000\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e250\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e58.6\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.168484\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e31.44\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e2.68\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e11714000\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e300\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e68.8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.194785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e30.93\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e64.15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e482264\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e350\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e80.7\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.222111\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e30.40\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e637.585\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e47691.7\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e400\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e89.2\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.249834\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e29.83\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e3624.34\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e8232.48\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"83\"\u003e\n\u003cp\u003e450\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"90\"\u003e\n\u003cp\u003e103.3\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.277697\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e29.22\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e14074.1\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e2076.18\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\n\u003cp\u003e\u0026nbsp;\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eTable 4\u003c/p\u003e\n\u003cp style=\"text-align: center;\"\u003eVarious device performance parameters at the different radius of nanotube of DL-NT-FET\u003c/p\u003e\n\u003ctable style=\"margin-left: auto; margin-right: auto;\" border=\"1\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003eRadius(nm)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eAVSS (mV/decade)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003eThe threshold voltage(V)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e (A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003eI\u003csub\u003eOFF\u003c/sub\u003e (\u0026micro;A/m)\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003eI\u003csub\u003eON\u003c/sub\u003e/I\u003csub\u003eOFF\u003c/sub\u003e\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e67.5\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.178221\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e24.17\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e13.05\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003e1852290\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e10\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e68.8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.194785\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e30.93\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e64.15\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003e482264\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e12\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e72.2\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.212351\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e37.72\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e298.04\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003e126582\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e14\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e78.1\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.231078\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e44.63\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e1308.17\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003e34118\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd width=\"77\"\u003e\n\u003cp\u003e16\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e80.3\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"78\"\u003e\n\u003cp\u003e0.250602\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e51.70\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"84\"\u003e\n\u003cp\u003e5366.02\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd width=\"72\"\u003e\n\u003cp\u003e9635.24\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\n\u003cp\u003eFig. 6 (a) shows the variation of transconductance with VGS at different channel lengths which is a specific figure of merit of a FET and it measures the precision in the conversance of gate voltage into the current. It is noticed from Fig. 6(a) that the transconductance increases with the increasing channel length (up to 25 nm) then it remains constant. The transconductance increases with the channel length because of higher change in drain current is obtained at the large channel length with a small change in gate voltage. At the 25 nm channel length, the obtained value of the gm is 5.2x10-5 S/\u0026micro;m at the gate voltage of 0.45 V. Fig. 6(b) depicts the changes in the gate to source capacitance (Cgs) and drain to source capacitance (Cgd) with the gate voltage. A proliferation of 39% is observed in the Cgs at the VGS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the Cgd for the same increment in the channel length.\u003c/p\u003e\n\u003cp\u003eThe behavior of drain current concerning VDS for different values of VGS at the channel length of 20 nm and 35nm has been shown in Fig. 7(a), where it is again found that ID is more for channel length 20nm than that of for channel length 35nm. Moreover, it is also noticed that at smaller VGS, the saturation in the drain current occurs earlier as compare to the large VGS; this is because of limited space-charge inversion in the channel which implies greater gate control over the channel. Fig. 7(b) shows how the output conductance (gds) varies with VDS where VGS is fixed at 1V and readings for 20nm and 35nm channels are taken. It is well known that gds is a crucial parameter in determining the intrinsic gain of a device and for better gain, it should be low. It can be seen from Fig. 7(b) that its value does not change with the channel length and the obtained value of the gds\u0026shy; for the designed DL-NT-FET is 3.4x10-5 (S/\u0026micro;m).\u003c/p\u003e\n\u003cp\u003eThe output characteristics (ID-VDS) at the various temperatures are plotted in Fig. 8(a) and it is observed that the drain current decreases with an increase in the temperature. The ID decreases with the temperature because scattering phenomena increase with the temperature and this results in low carrier mobility in the channel and hence low drain current at the higher temperature [22]. The ID degrades 15% on increasing the temperature from 200K to 400 K. Fig. 8(b) shows the variation of the output conductance (gds) with the VDS at different temperature and it is found that gds also degrades on increasing the temperature and it is due to the reduction of ID at the higher temperature. \u0026nbsp;\u003c/p\u003e\n\u003cp\u003eThe impact of the nanotube radius in the output characteristics and output transconductance is plotted in Fig. 9(a) and Fig. 9(b) respectively and it is found that both the parameters are increasing with augmenting the radius. The ID enhances the increasing radius because a large radius renders large space charges in the inversion condition and the large drain current implies the higher output transconductance. An increment of 100% in the drain current and 137% in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm.\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;\u003c/p\u003e"},{"header":"Conclusion","content":"\u003cp\u003eThis manuscript covers a proposed dopingless nanotube FET structure. Different characteristics of the device have been examined by TCAD simulated results. The obtained AVSS for 20nm channel length, the radius of 10nm simulated at 300K is 68.80mV/decade which has much scope of improvement by optimization of the device. A comparative analysis of transfer characteristics (ID-VGS), transconductance (gm), gate capacitances (Cgs and Cgd), output characteristics (ID-VDS), and output conductance (gds), has been made by varying the channel length (Lg), radius (R), gate work function (\u0026Phi;) and temperature. An increment of 100% in the drain current and 137% in the output transconductance has been noted when the radius of the nanotube increases from 8 nm to 16 nm. The gate capacitances Cgs and Cgd are higher for the longer channel. On increasing the temperature from 300k to 400K, the output conductance is found to decrease as well as the drain current gets saturated to a lower value whereas, by decreasing temperature to 200K, the opposite happens. An augmentation of six orders in the ION/IOFF ratio and 81% reduction in the threshold voltage has been observed when the gate work function is enhanced from 4.3eV to 4.7eV. The ION/IOFF decreases with a temperature rise, there are 6 orders diminution in the ION/IOFF ratio is noticed when the temperature is increased from 200 K to 450 K. The threshold voltage and the AVSS both are rose with the temperature. The threshold voltage rises 92% while the AVSS rises 114% on increasing the temperature from 200K to 450K. The transconductance curve has the highest peak value for the longest channel. It can thus be concluded that, after a thorough investigation of the behavior of the proposed dopingless nanotube FET parameters under several variations, it can be well understood that there are a good number of challenges to get the optimized results.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eFunding statement:\u003c/h2\u003e\n\u003cp\u003eNo funding was received to assist with the preparation of this manuscript.\u003c/p\u003e\n\u003ch2\u003eConflict of Interest:\u003c/h2\u003e\n\u003cp\u003eThe authors declare that they have no conflict of interest.\u003c/p\u003e\n\u003ch2\u003eAuthor contributions:\u003c/h2\u003e\n\u003cp\u003eAll authors have equally participated in the preparing of the manuscript during implementation of ideas, findings results, and writing of the manuscript.\u003c/p\u003e\n\u003ch2\u003eAvailability of data and material:\u003c/h2\u003e\n\u003cp\u003ecurrent submission does not contain the pool data of the manuscript but the data used in the manuscript will be provided on request.\u003c/p\u003e\n\u003ch2\u003eCompliance with ethical standards:\u003c/h2\u003e\n\u003cp\u003eThe Authors accepted principles of ethical standard and they have no conflict of interest.\u003c/p\u003e\n\u003ch2\u003eConsent to participate:\u003c/h2\u003e\n\u003cp\u003eInformed consent.\u003c/p\u003e\n\u003ch2\u003eConsent for Publication:\u003c/h2\u003e\n\u003cp\u003eConsent is granted.\u003c/p\u003e\n\u003ch2\u003eAcknowledgments:\u003c/h2\u003e\n\u003cp\u003eNot Applicable.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eHuang, J.S.T., and Schrankler, J.W., 1987. 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Journal of Physics and Chemistry of Solids, 1(4), pp.262-269.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"silicon","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scon","sideBox":"Learn more about [Silicon](https://www.springer.com/journal/12633)","snPcode":"12633","submissionUrl":"https://submission.nature.com/new-submission/12633/3","title":"Silicon","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"nanotube FET, Dopingless, charge plasma, output conductance, average subthreshold slope, and gate capacitance","lastPublishedDoi":"10.21203/rs.3.rs-330678/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-330678/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"In this paper, a dopingless nanotube field-effect transistor (DL-NT-FET) has been proposed and its performance analysis is done using a technology computer-aided design (TCAD) tool, ATLAS provided by Silvaco. The elimination of doping is brought in by the application of the charge-plasma (CP) technique. A comparative examination of transfer characteristics (I D -V GS ), transconductance (g m ), gate capacitances (C gs and C gd ), output characteristics (I D -V DS ), output conductance (g ds ), average subthreshold slope (AVSS), the threshold voltage (V t ), the ratio of on-current to off-current (I ON /I OFF ) and on-current has been made by varying the channel length (Lg), radius (R), gate work function (Φ), and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater I ON /I OFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The I OFF value increases significantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. The I ON degrades 15% by increasing the temperature from 200K to 400K. The output conductance g ds also degrades on increasing the temperature. A proliferation of 39% is observed in the C gs at the V GS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the C gd for the same increment in the channel length.","manuscriptTitle":"Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2021-04-12 14:23:04","doi":"10.21203/rs.3.rs-330678/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Minor revisions","date":"2021-04-15T09:46:40+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2021-03-25T00:00:00+00:00","index":0,"fulltext":""},{"type":"editorAssigned","content":"","date":"2021-03-24T00:00:00+00:00","index":"","fulltext":""},{"type":"editorInvited","content":"Silicon","date":"2021-03-24T00:00:00+00:00","index":"","fulltext":""},{"type":"submitted","content":"Silicon","date":"2021-03-15T00:22:27+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"silicon","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scon","sideBox":"Learn more about [Silicon](https://www.springer.com/journal/12633)","snPcode":"12633","submissionUrl":"https://submission.nature.com/new-submission/12633/3","title":"Silicon","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"a7a7387d-d50b-49f2-a5d5-38b3d6ca5281","owner":[],"postedDate":"April 12th, 2021","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[{"id":3564734,"name":"Materials Chemistry"},{"id":3564735,"name":"Materials Engineering"}],"tags":[],"updatedAt":"2021-05-28T12:12:31+00:00","versionOfRecord":[],"versionCreatedAt":"2021-04-12 14:23:04","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-330678","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-330678","identity":"rs-330678","version":["v1"]},"buildId":"WrCJVZZCHTDjtuVLN7oU0","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}