Improved performance of Error Controlling Codes using novel XOR gates

Improved performance of Error Controlling Codes using novel XOR gates | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Improved performance of Error Controlling Codes using novel XOR gates Billa Nazma This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7347519/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Error correction codes (ECCs) are essential for maintaining data integrity in sophisticated digital systems, including System-on-Chip (SoC) architectures and Data Link Layer protocols. This work introduces a VLSI-optimized implementation of Hamming, Dual Rail, Checksum-XOR, and Two-Dimensional Parity with Duplication (2DPD) codes, highlighting their effectiveness in error detection and correction. The suggested method utilizes innovative XOR gate topologies realized in complementary metal-oxide-semiconductor (CMOS) technology to attain high-speed, low-power performance and improved throughput. The XOR gate implementation in Fig. 6(h) exhibits enhanced performance, attaining considerable increases in Power-Delay Product (PDP) efficiency. Hamming codes provide single-error rectification and double-error detection via strategic placement of parity bits, whereas Checksum-XOR improves error detection in protocols such as TCP and UDP. Dual Rail coding enhances fault tolerance in safety-critical System-on-Chip designs by utilizing signal redundancy, while 2DPD provides resilient error correction for memory arrays and specific network topologies. Experimental findings indicate that Fig. 6(h) attains PDP efficiency enhancements of up to 90.68% for Dual Rail and 90.56% for 2DPD codes relative to CMOS across 8-bit, 16-bit, and 32-bit configurations, demonstrating consistent superiority over other XOR gate designs depicted in Figs. 6(b), 6(e), and 6(i). Thorough trade-off evaluations of redundancy, computational complexity, and error-correction capacity substantiate the proposed designs, especially Fig. 6(h), as exceptionally appropriate for low-power, high-performance applications in contemporary digital systems. Electronic Materials and Devices System on Chip Data link layer protocols Error Controlling Codes XOR Low-power design Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Introduction Network on Chip (NoC) addresses challenges among multiple IP blocks within a system-on-chip (SoC) [ 19 , 6 ]. The primary concern of NoC is communication reliability. Semiconductor defects can be categorized as transient, permanent, or intermittent. Transient failures may arise from power supply noise, crosstalk noise, electromagnetic interference, and variations in transistor size. [ 1 , 2 , 4 ]. NoC design methods facilitate high integration. Manufacturing defects and device deterioration present enduring challenges. Hardware instability, fluctuations in junction temperature, and voltage degradation may lead to intermittent issues [ 21 ]. Error detection and correction coding addresses interconnect damage resulting from misinterpretations of information and management signals [3,14]. Crosstalk noise presents a significant challenge in deep sub-micron technology, leading to timing delays and power inefficiencies. The high connector aspect ratio and low wire spacing significantly elevate coupling capacitance, thereby impacting timing, power consumption, and signal integrity [ 22 ]. The Crosstalk-Induced Bus Delay (CIBD) in parallel interconnects lacking crosstalk reduction is expressed as (1 + 4λ) τ0, with λ representing the ratio of coupling capacitance Cc to self-capacitance Cb, and τ0 denoting the delay of a crosstalk-free wire [ 6 ]. Techniques such as bus inversion [ 2 ], shielding, spacing, duplication, and crosstalk avoidance codes (CAC) like Fibonacci codes [ 1 ] can reduce CIBD to (1 + 2λ)τ0. CAC methodologies circumvented conflicting transitions in neighboring interconnects to reduce effective coupling capacitance. Supplementary crosstalk avoidance/reduction codes decrease the CIBD from (1 + 3λ)τ0 to (1 + 2λ)τ0 [ 10 ]. Many coding solutions integrate low-power code (LPC) with error detection and repair, while others present coding techniques that encompass parallel connection power consumption and reliability. A hybrid error correction and detection code utilizing CAC addresses to mitigate crosstalk and other transient fault noise [ 23 ]. Error-regulating codes are essential in Network-on-Chip (NoC) for the development of crosstalk-resistant interconnects. Various error detection and correction schemes include dual rail, MDR, boundary shift code (BSC) [ 17 ], shield pattern combined with bus inverting code [ 2 ], duplicate-add-parity (DAP) and DAPX [ 25 ], simple Hamming codes, CRC, Latin square codes [14], product codes based on Hamming codes [ 16 ], among others. Error-controlling codes that incur overhead in power, latency, and area are essential for ensuring dependability in Network on-chip systems. This work employs different XOR gates to reduce the overhead in power, time, and area associated with error-controlling codes. Research indicates that ECC codes, including two-dimensional parity with duplication, checksum-xor, dual tail, and Hamming, have not yet been implemented utilizing revolutionary XOR gates logic. This paper analysed the power and delay effects of the new XOR gates on error-controlling codes. The order of sections is as follows. Section 2 presents Hamming forward error correcting codes and dual rail code. Section 3 provides a detailed explanation of checksum-XOR and two-dimensional parity, focusing on their application in duplication error detection codes. Section 4 illustrates the superiority of unique XOR gate logic over CMOS technology. Section 5 presents the experimental results, which encompass average power consumption, delay, and the power delay product (PDP). The conclusion of the paper is presented in Section 6. 2. Forward Error Code Correction Error-correcting coding (see Fig. 1 [ 19 ]) Encodes "k" data bits (d 0 , d 1 , …, d k−1 ) along with " m " parity bits into a " n "-bit code word (where n = m + k ) featuring a Hamming Distance D , which allows for the correction of up to D − 1 errors (with D = 3 enabling single-bit correction). A decoder mitigates interconnect noise, such as power and crosstalk, through the implementation of a syndrome generator (SG) and a decoder (SD). SG analyses the received and transmitted data to generate a " m "-bit syndrome S. The SD produces an error vector E, which is XORed with the received data (d i XOR ei) to facilitate correction. 2.1 Hamming Code Hamming codes are designed to correct single-bit errors using a total of " h " bits, where " h " is the sum of message bits " m " and parity bits " p " ( h = m + p ). The inequality 2 p ≥ h + 1 defines p , with the optimal value of m calculated as m = 2 p – p -1. The relationship between code length h and m is defined by the inequality \(\:\frac{{\text{2}}^{\text{ℎ}}}{\text{ℎ+1}}\text{≥}{\text{2}}^{\text{m}}\) . The gate count and associated costs are influenced by the variables m and p, as illustrated in Fig. 2 . 2.2: Dual Rail Code The dual rail configuration (refer to Fig. 3 ) replicates 8-bit data (C 0 –C 7 ) while calculating C 8 . SG produces a single syndrome bit designated as S0. Multiplexers determine the appropriate bits based on the state of S 0 : when S 0 is set to 0, error-free data is selected; when S0 is set to 1, data or C 8 errors are selected. The system encounters failures with even-numbered data errors; however, it mitigates crosstalk through wire spacing, resulting in improved power efficiency compared to Hamming for larger values of m . 3. Error Detection Codes The implementation of complex multi-bit correction results in a degradation of performance, thereby favouring the use of error detection codes. A code with Hamming Distance D is capable of detecting D − 1 errors and correcting ( D − 1)/2 errors. 3.1 Checksum-XOR Based Data (e.g., D 0 –D 7 ) is organized into a 2D matrix, with column checksums calculated as follows: CS_D 0 = D 0 XOR D 1 , and transmitted accordingly. Receivers perform checksum recalculation; a zero value indicates acceptance of data, while a non-zero value triggers retransmission. The system demonstrates efficiency; however, it encounters failures related to errors in even-numbered columns (see Fig. 4 ). 3.2 Two-Dimensional Parities with Duplication (2DPD) 2DPD (Fig. 5 ) attains a performance level of D = 4, enabling the detection of 3-bit errors or the correction of 1-bit errors while also detecting 2-bit errors. Duplication allows for D = 8, facilitating the detection of 7-bit errors and minimizing crosstalk. Encoding calculates the row and column parities in a two-dimensional matrix, transmitting a total of 2(K + C + R + 1) bits. Decoding employs XOR operations for the generation of check bits and for the issuance of retransmission requests (REQ). If REQ equals 0, data is accepted; if not, retransmission will take place. The system experiences failure when encountering seven or more errors, resulting in elevated power and space costs. Table 1 Normalized word size of ECC coding schemes to transmit Scheme 64 bit 32 bit 16 bit 8 bit Hamming code 71 38 21 12 Dual rail 129 65 33 17 Checksum-xor 68 36 20 10 2DPD 162 90 50 30 4. NOVEL XOR GATES 4.1. FULL SWING XOR GATE Figure 6 (a) presents the complete configuration of the XOR/XNOR gate implemented through double pass-transistor logic (DPL). The configuration is comprised of eight transistors. The output of these structures is fully operational; however, the main concern with this circuit is the use of two high power consumption NOT gates situated on the critical path. Increasing the dimensions of the transistors in NOT gates is necessary to achieve a reduction in critical path delay. This modification will lead to an increase in capacitance at the intermediate node. As a result, there will be a minor increase in both delay and power consumption. Figure 6 (b) illustrates the full-swing XOR/XNOR gate implemented using pass-transistor logic. This circuit is constructed utilizing six transistors. The delay and power performance surpass that of Fig. 6 (a). The issue with this circuit involves the utilization of a NOT gate within the critical path. Figure 6 (c) illustrates the full-swing XOR-XNOR gate constructed using CPL logic. This configuration is implemented with a total of ten transistors. The PMOS transistors in this configuration are arranged in a cross-coupled structure connected to the outputs. The issue with this circuit involves the implementation of feedback through a cross-coupled structure at the outputs, which results in increased delay and short-circuit power. Additionally, NOT gates are present on the critical path. Figure 6 (d) illustrates an additional XOR-XNOR circuit. The design incorporates eight transistors, as illustrated below. The critical path of the circuit exceeds that depicted in Fig. 6 (c). The short circuit current will flow in the circuit when the input transitions from logic "01" to "00". Six transistors form the full-swing XOR-XNOR gate in Fig. 6 (e). The feedback transistors (N3 and P3) restore weak logic levels at the output nodes (XOR and XNOR) when inputs are “00” or “11.” The worst-case delay causes the output voltage to reach its final voltage in two phases. Short circuit current flows when the feedback mechanism is not fully activated. This circuit is sensitive to process, voltage, and temperature changes. Ten transistors form the full-swing XOR-XNOR gate in Fig. 6 (f). This setup resolves delayed response times. This circuit has full-swing output and great driving power. The feedback circuit adds parasitic capacitance to the XOR and XNOR gate output nodes. Power usage and delay rise slightly. Ten transistors form the full-swing XOR-XNOR gate in Fig. 6 (g). The circuit's power consumption increases when a NOT gate creates a large intermediate node capacitance. More electricity is used than in Fig. 6 (f). 4.2 NON FULL SWING XOR CIRCUIT Figure 6 (h) illustrates the non-full-swing XOR-XNOR gate, comprising four transistors. This circuit is characterized by its inability to achieve the final voltage value at the output. This circuit exhibits efficiency regarding power consumption and latency. Figure 6(i) The new XOR-XNOR circuit mitigates the problems associated with previous XOR and XNOR circuits. The circuit configuration is characterized by little output capacitance, and the critical path lacks NOT gates. It consumes less electricity and functions at an exceptionally rapid velocity. The features of this circuit are its full-swing output and robust driving capacity. Results and Conclusions Figures 6 (a) to 6(i) show how XOR gates implement regulating codes. Five XOR gates in Fig. 6 (b), Fig. 6 (h), Fig. 6 (e), and Fig. 6 (i) demonstrate ECC efficiency improvements. This work was realised using CADENCE VIRTUOSO tool in 45nm technology. The results are in Tables 2 – 7 . Table 2 shows power, latency, and PDP performance data for 8, 16, and 32-bit Hamming code. Table 2 shows that Fig. 6 (h) has the lowest Hamming Encoder PDP values for 8-bit (3.07) and 16-bit (11.8) configurations. Figure 6 (i) displays the 32-bit configuration's lowest PDP (67.15). Figure 6 (e) shows the lowest Hamming Decoder PDP for 8-bit (10.14), while Fig. 6 (h) shows the lowest for 16-bit (25.59) and 32-bit (78.2). In Hamming CODEC, Fig. 6 (h) shows the lowest CODEC PDP for 8-bit (13.6) and 16-bit (37.39) configurations, while Fig. 6 (i) shows the lowest for 32-bit (129.09). Table 2 Performance measure of Hamming code in terms of Power, Delay and PDP for 8, 16, and 32-bit Type of Circuit ENCODER DECODER CODEC DELAY (ps) POWER (µW) PDP (10^-18J) DELAY (ps) POWER (µW) PDP (10^-18J) PDP (10^-18J) 8-Bit Figure 6 (b) 0.319 15.8 5.05 0.82 24 19.68 24.73 Figure 6 (h) 0.318 9.65 3.07 0.81 13 10.53 13.6 Figure 6 (e) 0.365 11.9 4.35 0.78 13 10.14 14.49 Figure 6 (i) 0.297 12.5 3.72 0.74 14 10.36 14.08 CMOS 0.319 33.8 10.79 0.9 29 26.1 36.89 16-Bit Figure 6 (b) 0.922 41.8 38.54 0.85 58 49.3 87.84 Figure 6 (h) 0.559 21.1 11.8 0.78 32.8 25.59 37.39 Figure 6 (e) 0.74 25.1 18.58 0.77 34 26.18 44.76 Figure 6 (i) 0.64 26 16.64 0.73 36 26.28 42.92 CMOS 0.934 49 45.77 0.83 72.1 59.85 105.62 32-Bit Figure 6 (b) 1.23 88.4 108.74 0.88 99.9 87.92 196.66 Figure 6 (h) 0.779 62.3 48.54 0.85 92 78.2 126.74 Figure 6 (e) 0.872 75.8 66.1 0.83 86 71.38 137.48 Figure 6 (i) 0.831 80.8 67.15 0.78 79.4 61.94 129.09 CMOS 0.885 155 137.18 0.91 112 101.92 239.1 Table 3 Performance measure of Dual rail code in terms of Power, Delay and PDP for 8, 16, and 32-bit Type of Circuit ENCODER DECODER CODEC DELAY (ps) POWER (µW) PDP (10^-18J) DELAY (ps) POWER (µW) PDP (10^-18J) PDP (10^-18J) 8-Bit Figure 6 (b) 0.293 10.5 3.08 0.96 12 11.52 14.6 Figure 6 (h) 0.429 4.4 1.89 0.96 2.4 2.31 4.2 Figure 6 (e) 0.433 3.5 1.52 0.95 4.4 4.18 5.7 Figure 6 (i) 0.483 3.5 1.7 0.89 3.9 3.48 5.18 CMOS 0.483 17.1 8.26 1.1 13 14.3 22.56 16-Bit Figure 6 (b) 0.445 20.2 8.99 0.97 22 21.34 30.33 Figure 6 (h) 0.392 7.31 2.87 0.97 4.4 4.27 7.14 Figure 6 (e) 0.112 9.01 1.01 0.96 9.4 9.03 10.04 Figure 6 (i) 0.152 9.07 1.38 0.93 7.64 7.11 8.49 CMOS 0.48 33.6 16.13 0.6 91.8 55.08 71.21 32-Bit Figure 6 (b) 0.634 40.3 25.56 0.97 40 38.8 64.36 Figure 6 (h) 0.265 27.2 7.21 0.97 10.89 10.57 17.78 Figure 6 (e) 0.122 18.4 2.25 0.95 18 17.1 19.35 Figure 6 (i) 0.149 19.1 2.85 0.97 16.4 15.91 18.76 CMOS 1.2 77.9 93.48 1.17 83 97.11 190.59 Table 3 presents the Power, Delay, and PDP performance for 8, 16, and 32-bit Dual rail codes. According to Table 3 , Fig. 6 (e) consistently attains the lowest PDP across all bit sizes for dual rail encoders, whereas Fig. 6 (h) demonstrates the highest efficiency for decoders. In the case of the Dual rail CODEC, Fig. 6 (h) consistently exhibits the lowest Power Delay Product (PDP). Utilize Fig. 6 (h) for decoders and CODEC, and Fig. 6 (e) for encoders in low-power, low-PDP applications. For low-latency applications, Fig. 6 (e) is optimal for encoders (16-bit and 32-bit), whereas Fig. 6 (i) or e are suitable for decoders. Table 4 presents the performance of 8, 16, and 32-bit checksums in terms of power, latency, and PDP. The Checksum Encoder's minimum PDP for 8-bit, 16-bit, and 32-bit is presented in Table 4 . Figure 6 (h) illustrates the lowest eight-bit PDP, Fig. 6 (i) depicts the lowest sixteen-bit PDP, and Fig. 6 (j) represents the lowest thirty-two-bit PDP. The decoder efficiency is maximized in Figs. 6 (h) and 6(i). Figure 6 (h) exhibits the lowest CODEC PDP among all bit sizes. Utilize Fig. 6 (h) for the encoder and decoder in low-delay applications across all bit sizes. For low-power applications, refer to Fig. 6 (i) for encoders and 8-bit/16-bit decoders, and (b) for 32-bit decoders. The efficiency of the CODEC and decoder (PDP) is maximized in Fig. 6 (h), although the encoder efficiency is superior in Fig. 6 (b) or (h). Table 4 Performance measure of Checksum-XOR based code in terms of Power, Delay and PDP for 8, 16, and 32-bit Type of Circuit ENCODER DECODER CODEC DELAY (ps) POWER (µW) PDP (10^-18J) DELAY (ps) POWER (µW) PDP (10^-18J) PDP (10^-18J) 8-Bit Figure 6 (b) 0.139 5.21 6.69 0.62 48.1 3.24 9.93 Figure 6 (h) 0.049 5.17 2.95 0.56 60.09 2.9 5.85 Figure 6 (e) 0.12 6.56 7.22 0.82 60.13 5.38 12.6 Figure 6 (i) 0.13 4.89 5.2 0.694 40 3.4 8.6 CMOS 0.223 5.264 13.39 0.814 60.04 4.29 17.68 16-Bit Figure 6 (b) 0.449 18.11 21.6 1.063 48.1 19.26 40.86 Figure 6 (h) 0.215 15.1 17.2 0.711 80 10.74 27.94 Figure 6 (e) 0.593 20.78 47.52 1.397 80.12 29.03 76.55 Figure 6 (i) 0.48 10.48 31.55 0.82 65.72 8.6 40.15 CMOS 0.697 20.16 55.76 1.458 80 29.4 85.16 32-Bit Figure 6 (b) 0.683 40.3 32.86 1.996 48.1 80.44 113.3 Figure 6 (h) 0.34 40.17 54.4 0.905 160 36.36 90.76 Figure 6 (e) 0.95 52.31 152.1 1.44 160.1 75.33 227.43 Figure 6 (i) 0.37 40.17 49.07 1.39 132.6 55.84 104.91 CMOS 1.003 55.25 161.49 2.625 161 145.04 306.53 The performance metrics for 2DPD are shown in Table 5 , with particular attention paid to power, delay, and PDP for 8, 16, and 32-bit configurations. Table 5 shows that Fig. 6 (h) consistently shows the lowest encoder PDP for all bit sizes. Across all bit sizes, Fig. 6 (h) shows the decoder PDP's maximum efficiency. Figure 6 (h) consistently demonstrates the lowest CODEC PDP across all bit sizes. Figure 6 (i) displays competitive results in terms of delay and power consumption, while Fig. 6 (h) shows superior performance for both the encoder and the decoder in terms of delay and PDP. While decoders often show lower power consumption in novel designs, encoders show lower delays than decoders across a range of bit sizes. For 32-bit, decoder PDPs are higher than encoder PDPs due to higher delays; however, Fig. 6 (h) successfully mitigates this discrepancy. Figure 6 (h): It is a good option for applications that need low latency and energy efficiency because it performs optimally for delay (encoder and decoder) and PDP (encoder, decoder, and CODEC) across all bit sizes. Along with the decoder PDP for 16-bit, Fig. 6 (i) shows competitiveness in encoder delay and power, making it suitable for designs that place a high priority on power efficiency. For low-latency applications, it is recommended to use Fig. 6 (h) for both the encoder and decoder for all bit sizes, and Fig. 6 (i) as a reliable substitute for encoders only. For 8-bit and 16-bit decoders in low-power applications, see Fig. 6 (e); for encoders and 32-bit decoders, use Fig. 6 (h) or Fig. 6 (i). For all components and bit sizes, Fig. 6 (h) is the best choice in terms of overall efficiency (PDP). Table 5 Performance measure of 2DPD code in terms of Power, Delay and PDP for 8, 16, and 32-bit Type of Circuit ENCODER DECODER CODEC DELAY (ps) POWER (µW) PDP (10^-18J) DELAY (ps) POWER (µW) PDP (10^-18J) PDP (10^-18J) 8-Bit Figure 6 (b) 0.488 20.03 9.78 1.63 10.327 16.84 26.62 Figure 6 (h) 0.249 18.26 4.55 0.98 5.36 5.26 9.81 Figure 6 (e) 0.484 20.03 9.7 1.603 5.314 8.52 18.22 Figure 6 (i) 0.23 20.2 4.65 0.985 6.288 6.2 10.85 CMOS 2.55 20.99 53.53 2.431 9.382 22.81 76.34 16-Bit Figure 6 (b) 0.76 35.65 27.1 2.455 16.83 41.32 68.42 Figure 6 (h) 0.39 26.51 10.34 1.26 8.74 11.02 21.36 Figure 6 (e) 0.76 35.65 27.1 1.429 8.66 12.38 39.48 Figure 6 (i) 0.36 35.95 12.95 2.445 10.25 25.07 38.02 CMOS 4.1 42.36 173.68 3.659 14.32 52.4 226.08 32-Bit Figure 6 (b) 1.06 63.78 67.61 4.752 30.06 142.85 210.46 Figure 6 (h) 0.54 47.43 25.62 2.48 15.61 38.72 64.34 Figure 6 (e) 1.05 68.78 72.22 2.86 16.47 47.11 119.33 Figure 6 (i) 0.49 64.31 31.52 4.678 14.31 66.95 98.47 CMOS 5.52 75.78 418.31 6.958 25.57 177.92 596.23 Table 6 PDP Efficiency (%) improvement of Hamming Code, Dual rail, Checksum, 2DPD CODEC using XOR gate shown in Fig. 6 (h) Type of Circuit Improved PDP Efficiency (%) HC DR CS 2DPD 8-Bit Figure 6 (b) 45.01 71.24 41.09 63.15 Figure 6 (e) 6.15 26.32 53.58 46.16 Figure 6 (i) 3.41 18.92 31.98 9.59 CMOS 63.14 81.39 66.92 87.15 16-Bit Figure 6 (b) 57.44 76.46 31.63 68.79 Figure 6 (e) 16.47 28.89 63.51 45.9 Figure 6 (i) 12.89 15.91 30.42 43.82 CMOS 64.6 89.98 67.2 90.56 32-Bit Figure 6 (b) 35.56 72.38 19.9 69.43 Figure 6 (e) 7.82 8.12 60.1 46.09 Figure 6 (i) 1.83 5.23 13.49 34.67 CMOS 47 90.68 70.4 89.21 The XOR gate implementation shown in Fig. 6 (h) exhibits notable enhancements in Power Delay Product (PDP) efficiency across various error-correcting code realizations, such as Hamming, Dual Rail, Checksum, and 2DPD codes, for configurations of 8-bit, 16-bit, and 32-bit. The enhancements are evaluated in comparison to various XOR gate implementations illustrated in Figs. 6 (b), 6(e), 6(i), along with a standard CMOS implementation. The results consistently demonstrate the enhanced performance of the Fig. 6 (h) design, especially for Dual Rail and 2DPD codes, with efficiency improvements frequently surpassing 80% relative to the CMOS baseline. The Hamming code implementation utilizing the XOR gate as depicted in Fig. 6 (h) demonstrates enhancements in PDP efficiency of 45.01%, 6.15%, 3.41%, and 63.14% for the 8-bit configuration when compared to Figs. 6 (b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates improvements of 57.44%, 16.47%, 12.89%, and 64.60%. In contrast, the 32-bit configuration shows gains of 35.56%, 7.82%, 1.83%, and 47.00% when compared to the same respective baselines. The results demonstrate a strong performance across different bit widths, highlighting significant efficiency benefits compared to the CMOS implementation. The implementation of the Dual Rail code using the XOR gate as illustrated in Fig. 6 (h) demonstrates significant improvements in PDP efficiency. The 8-bit configuration demonstrates improvements of 71.24%, 26.32%, 18.92%, and 81.39% when compared to Figs. 6 (b), 6(e), 6(i), and the CMOS baseline, respectively. The 16-bit configuration demonstrates increased gains of 76.46%, 28.89%, 15.91%, and 89.98%. In comparison, the 32-bit configuration records gains of 72.38%, 8.12%, 5.23%, and 90.68% relative to the same baselines. The results highlight the remarkable efficiency of the Fig. 6 (h) design for Dual Rail codes, especially in comparison to CMOS, with enhancements nearing or surpassing 90%. The Checksum code utilizes the XOR gate realization depicted in Fig. 6 (h), which demonstrates PDP efficiency enhancements of 41.09%, 53.58%, 31.98%, and 66.92% for the 8-bit configuration when compared to Figs. 6 (b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates enhancements of 31.63%, 63.51%, 30.42%, and 67.20%. In contrast, the 32-bit configuration exhibits improvements of 19.90%, 60.10%, 13.49%, and 70.40% when compared to the same baselines. The results indicate consistent performance enhancements, with the most notable improvements recorded in comparison to Fig. 6 (e) and CMOS. The implementation of the 2DPD code utilizing the XOR gate as depicted in Fig. 6 (h) demonstrates enhancements in PDP efficiency of 63.15%, 46.16%, 9.59%, and 87.15% for the 8-bit configuration when compared to Figs. 6 (b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates improvements of 68.79%, 45.90%, 43.82%, and 90.56%. In comparison, the 32-bit configuration exhibits gains of 69.43%, 46.09%, 34.67%, and 89.21% relative to the same baselines. The results demonstrate that the implementation shown in Fig. 6 (h) exhibits superior performance, especially at higher bit widths and in comparison to the CMOS baseline, where the observed efficiency gains are among the highest recorded. Table 7 PDP Efficiency (%) improvement of Hamming Code, Dual rail, Checksum, 2DPD CODEC using XOR gate shown in Fig. 6 (i) Type of Circuit Improved PDP Efficiency (%) HC DR CS 2DPD 8-Bit Figure 6 (b) 43.07 64.53 13.4 59.25 Figure 6 (h) -3.53 -23.34 -47.01 -10.61 Figure 6 (e) 2.83 9.13 31.75 40.46 CMOS 61.84 77.04 51.36 85.79 16-Bit Figure 6 (b) 51.14 72.01 1.74 44.44 Figure 6 (h) -14.8 -18.91 -43.71 -78 Figure 6 (e) 4.12 15.44 47.56 3.7 CMOS 59.37 88.08 52.86 83.19 32-Bit Figure 6 (b) 34.36 70.86 7.42 53.22 Figure 6 (h) -1.86 -5.52 -15.58 -53.05 Figure 6 (e) 6.11 3.05 53.88 17.49 CMOS 46.02 90.16 65.78 83.49 With configurations of 8-bit, 16-bit, and 32-bit widths, the Power-Delay Product (PDP) efficiency of the XOR gate implementation shown in Fig. 6 (i) was assessed across the realizations of the Hamming, Dual Rail, Checksum, and 2DPD error-correcting codes. Figures 6 (b), 6(h), and 6(e) compare the PDP efficiency to a baseline CMOS design and various XOR gate implementations. With benefits ranging from 1.74–90.16%, the results show significant efficiency increases in the majority of comparisons, especially when compared to CMOS. In contrast to Fig. 6 (h), the implementation continuously exhibits worse efficiency; performance gaps are indicated by negative values for all bit widths and coding schemes. In comparison to Figs. 6 (b), 6(h), 6(e), and CMOS, the XOR gate realization in Fig. 6 (i) for the 8-bit configuration achieves PDP efficiency increases of 43.07%, -3.53%, 2.83%, and 61.84% for the Hamming code, respectively. The increases versus the identical baselines are 51.14%, -14.80%, 4.12%, and 59.37% in the 16-bit configuration and 34.36%, -1.86%, 6.11%, and 46.02% in the 32-bit setup. Although notable efficiency gains are seen versus CMOS and other configurations, the negative values against Fig. 6 (h) show that it performs better than Fig. 6 (i). Significant PDP efficiency benefits are shown by the Dual Rail code implementation using the XOR gate in Fig. 6 (i), especially when compared to CMOS. Comparing the 8-bit arrangement to Figs. 6 (b), 6(h), 6(e), and CMOS, the improvements are 64.53%, -23.34%, 9.13%, and 77.04%, respectively. In comparison to the identical baselines, the 32-bit configuration achieves 70.86%, -5.52%, 3.05%, and 90.16%, while the 16-bit configuration displays increases of 72.01%, -18.91%, 15.44%, and 88.08%. Although Fig. 6 (i) is still less efficient than Fig. 6 (h), its strength is shown by the significant efficiency gains vs CMOS, particularly in the 32-bit arrangement. In comparison to Figs. 6 (b), 6(h), 6(e), and CMOS, the XOR gate realization in Fig. 6 (i) offers PDP efficiency increases of 13.40%, -47.01%, 31.75%, and 51.36% for the 8-bit configuration for the Checksum code, respectively. Compared to the identical baselines, the 16-bit configuration improves by 1.74%, -43.71%, 47.56%, and 52.86%, whereas the 32-bit configuration improves by 7.42%, -15.58%, 53.88%, and 65.78%. Although there are still notable advances over Fig. 6 (e) and CMOS, the notable decreases in efficiency relative to Fig. 6 (h), especially in the 8-bit and 16-bit designs, suggest a performance difference. In comparison to Figs. 6 (b), 6(h), 6(e), and CMOS, the 2DPD code implementation using the XOR gate in Fig. 6 (i) yields PDP efficiency increases of 59.25%, -10.61%, 40.46%, and 85.79% for the 8-bit configuration, respectively. Compared to the identical baselines, the benefits for the 32-bit configuration are 53.22%, -53.05%, 17.49%, and 83.49%, whereas the gains for the 16-bit configuration are 44.44%, -78.00%, 3.70%, and 83.19%. Even though the 16-bit configuration has a large negative value compared to Fig. 6 (h), which indicates a big performance gap, the design still proves to be effective in certain cases because it shows significant efficiency improvements over CMOS. Conclusion In comparison to the realizations in Fig. 6 (b), Fig. 6 (e), Fig. 6 (i), and CMOS, the XOR gate realization in Fig. 6 (h) consistently offers notable improvements in PDP (Power-Delay Product) efficiency across a range of bit sizes (8-bit, 16-bit, and 32-bit) and coding schemes (Hamming, Dual rail, Check sum, and 2DPD). The Dual rail and 2DPD codes show the most advantages, especially when compared to CMOS, where efficiency increases frequently surpass 80%. The improvements vary from 1.83–90.68%. In comparison to the XOR gate realizations in Fig. 6 (b), Fig. 6 (e), and CMOS, the XOR gate realization in Fig. 6 (i) offers enhanced PDP (Power-Delay Product) efficiency across a range of bit sizes (8-bit, 16-bit, and 32-bit) and coding schemes (Hamming, Dual rail, Check sum, and 2DPD), with efficiency gains ranging from 1.74–90.16%. Remarkably, Dual rail and 2DPD codes show the biggest improvements over CMOS, frequently above 80%. With negative values ranging from − 1.86% to -78% across all coding schemes and bit sizes, Fig. 6 (i) consistently displays lower PDP efficiency than Fig. 6 (h), suggesting that Fig. 6 (h) performs better in those situations. References M. Mutyam et al., Fibonacci codes for cross talk avoidance. IEEE Trans. (VLSI) Syst. 20(10), 1899–1903 (2012) B.K. Kaushik, D. Agarwal, Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects. Elsevier Trans. Microelectron. J.44 , 827–833 (2013) N. Jafarzadesh, M. Palesi, Data encoding techniques for reducing energy consumption in network-onchip. IEEE Trans. VLSI Syst. 22(3), 675–685 (2014) W.N. Flayyih, K. Samsudin, Crosstalk-aware multiple error detection scheme based on two dimensional parities for energy efficient network on chip. IEEE Trans. Circuits Syst. 1 61 , 2034–2047 (2014) Sundarrajan Rangachari, Jaiganesh Balakrishnan, and Nitin Chandrachoodan, ‘‘Scenario-Aware Dynamic Power Reduction Using Bias Addition,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 2,February 2017, pp.450–461. Yang, J., & Kumar, R. (2017). Crosstalk-Resistant Coding Techniques for Scalable NoC Interconnects. ACM Journal on Emerging Technologies in Computing Systems, 13(3), 38. https://doi.org/10.1145/3085592 Abdollahi, A., Fallah, F., & Pedram, M. (2017). Evaluation of 2-Dimensional Parity Techniques for Error Detection in SoC Memory Architectures.Microelectronics Reliability, 74, 146–153. https://doi.org/10.1016/j.microrel.2017.05.016 Kumar, M., & Chauhan, D. S. (2018). High Speed and Low Power XOR/XNOR Design Techniques: A Review. Microprocessors and Microsystems, 61, 1–14. https://doi.org/10.1016/j.micpro.2018.04.002 Chen, X., et al. (2018). Design and Analysis of Error Control Schemes for Reliable Network-on-Chip Architectures.IEEE Transactions on Computers, 67(6), 855–867. https://doi.org/10.1109/TC.2017.2780224 Rahimi, A., et al. (2018). Checksum and Redundancy Coding for Fault Tolerance in Data-Intensive SoC Systems. IEEE Transactions on Computers, 67(9), 1322–1335. https://doi.org/10.1109/TC.2018.2817121 Nasri, M., & Torkestani, J. A. (2018). Adaptive Error Correction Technique for Crosstalk Reduction in VLSI Interconnects. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10), 3432–3444. https://doi.org/10.1109/TCSI.2018.2829022 Chennakesavulu, M., Jayachandra Prasad, T., Sumalatha, V., 2018. Improved Performance of Error Controlling Codes Using Pass Transistor Logic. Circ. Syst.Sig. Process. 37 (3), 1145–1161. Springer publications. Saxena, A., & Chauhan, D. S. (2019). Design and Analysis of Low Power XOR Gate Using Novel 4T and 6T Logic Styles. Microelectronics Journal, 88, 1–10. https://doi.org/10.1016/j.mejo.2019.04.001 Taghavi, M., & Alipour, M. (2020). An Efficient ECC Architecture for Reliable Low-Power Network-on-Chip Communication. Integration, the VLSI Journal, 72, 125–134. https://doi.org/10.1016/j.vlsi.2020.05.004 Kiani, M., & Pedram, M. (2021). Dual-Rail Logic Design in Low-Swing Noise-Immune Digital Circuits. Integration, the VLSI Journal, 76, 45–54. https://doi.org/10.1016/j.vlsi.2021.03.001 Sharma, V., & Gupta, P. (2023). Hamming Codes and Their Applications in Modern Digital Systems. International Journal of Circuit Theory and Applications, 51(7), 1567–1580. Singh, P., & Kumar, S. (2023). Hybrid Error Correction Codes for Crosstalk-Resistant NoC Interconnects. IEEE Transactions on Very Large Scale Integration Systems, 31(6), 789–801. Wang, Z., & Zhang, Q. (2023). Low-Power XOR Gate Designs for Error-Correcting Codes in SoC. IEEE Journal of Solid-State Circuits, 58(9), 2345–2357. Chen, X., & Li, Y. (2023). Advances in Network-on-Chip Design for Low-Power SoC Applications. IEEE Transactions on Circuits and Systems, 70(5), 1234–1246. Kumar, A., & Singh, R. (2024). Error Detection and Correction in Data Link Layer Protocols Using Checksum-XOR. Journal of Network and Computer Applications, 220, 103245. Zhang, H., & Liu, M. (2024). Fault-Tolerant Interconnect Designs for Network-on-Chip Systems. ACM Transactions on Embedded Computing Systems, 23(2), 89–102. Liu, T., & Chen, J. (2024). Impact of Coupling Capacitance on NoC Performance and Power Efficiency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(4), 1012–1024. Gupta, R., & Sharma, A. (2024). Crosstalk Mitigation in NoC Using Error Detection and Correction Codes. Journal of VLSI Design, 45(3), 567–579. Lee, S., & Kim, H. (2025). Novel XOR Gate Topologies for Low-Power VLSI Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 72(2), 345–357. Patel, N., & Desai, R. (2025). Dual Rail and 2DPD Codes for Enhanced Fault Tolerance in SoC Designs. Journal of Electronic Design and Automation, 50(1), 45–58. Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7347519","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":498869223,"identity":"9c0ecc44-1015-4b83-afba-b0e42008b1d3","order_by":0,"name":"Billa Nazma","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA9ElEQVRIiWNgGAWjYDADA2bmxgMMFUAWM3MDsVoYGw4wnAFpYSRWCwNQC2MbiElAC3//2YMff+bYMZizA7X8nFcbzd8O1PKjYhtOLRI38pIlJLclM1g2MzYc7N12PHfGYcYGxp4zt3Fbc4PHQMJwGzODAVDlAd5tx3IbgAxmxjbcWuTPnzH+kbitHqzl4N85x3LnE9JicCDHTOLgtsNgLYd5G2pyNxDSYngjx8yycdtxHpBfDsscO5C7EWQdPr/IAR128+e2ajlz/sMHH76pqcudd/7wwQc/KvB4Hwp4oPRhMHmAoHokUEeK4lEwCkbBKBghAAD8jV9fkWe4gQAAAABJRU5ErkJggg==","orcid":"https://orcid.org/0009-0001-6296-0627","institution":"JNTUA","correspondingAuthor":true,"prefix":"","firstName":"Billa","middleName":"","lastName":"Nazma","suffix":""}],"badges":[],"createdAt":"2025-08-11 14:45:14","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-7347519/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7347519/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":88884196,"identity":"ad5131ec-cfa4-426b-93d8-bc96370c5333","added_by":"auto","created_at":"2025-08-12 11:40:10","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":94511,"visible":true,"origin":"","legend":"\u003cp\u003eBlock diagram of error correcting coding scheme\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/c0906db8fef6bc03cc10dbb0.png"},{"id":88884195,"identity":"f2fb50ee-93cf-401f-ad8d-48fe8073cd08","added_by":"auto","created_at":"2025-08-12 11:40:10","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":95738,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic diagram of (7,4) hamming code (a) encoder, (b) decoder\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/2458c428c1bc45146cbdd459.png"},{"id":88883319,"identity":"293354e6-a9fa-45e0-ae38-dc0d0f818252","added_by":"auto","created_at":"2025-08-12 11:32:10","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":47080,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic diagram of 8-bit dual rail code a) Encoder b) Decoder\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/f3d15badc903335c4a380aee.png"},{"id":88883316,"identity":"92d40788-7d97-41da-aac7-c3b18f35e5c7","added_by":"auto","created_at":"2025-08-12 11:32:10","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":44738,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic diagram of 8-bit Checksum-XOR based a) Encoder b) Decoder\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/e50255a96101814ab6c5e041.png"},{"id":88883327,"identity":"af067af1-7b4b-4d63-905f-9e832d761e31","added_by":"auto","created_at":"2025-08-12 11:32:10","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":741900,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic diagram of 8-bit 2DPD a) Encoder b) Decoder\u003c/p\u003e","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/b50ba4565d6d7c53e105a98c.png"},{"id":88883324,"identity":"40721318-05b0-44f8-9052-1ce2dede08aa","added_by":"auto","created_at":"2025-08-12 11:32:10","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":515668,"visible":true,"origin":"","legend":"\u003cp\u003eSee image above for figure legend\u003c/p\u003e","description":"","filename":"61.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/8067f2105696f3a3dd9d5b2f.png"},{"id":88884991,"identity":"e397bb33-73c8-4d69-b0d1-5811a945c6e4","added_by":"auto","created_at":"2025-08-12 11:48:10","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":45917,"visible":true,"origin":"","legend":"\u003cp\u003eCODEC PDP Efficiency (%) a) for 8-bit b) 16-bit and c) 32-bit\u003c/p\u003e","description":"","filename":"floatimage9.png","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/f4143d48b9b6b5e20d36790e.png"},{"id":88886660,"identity":"efb73477-fd53-4bd3-93d4-a03cb8b0b78b","added_by":"auto","created_at":"2025-08-12 12:04:12","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2499723,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7347519/v1/caebc0e4-e91d-4147-b12c-da02f0cf61a2.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003e\u003cstrong\u003eImproved performance of Error Controlling Codes using novel XOR gates\u003c/strong\u003e\u003c/p\u003e","fulltext":[{"header":"Introduction","content":"\u003cp\u003eNetwork on Chip (NoC) addresses challenges among multiple IP blocks within a system-on-chip (SoC) [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e19\u003c/span\u003e, \u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. The primary concern of NoC is communication reliability. Semiconductor defects can be categorized as transient, permanent, or intermittent. Transient failures may arise from power supply noise, crosstalk noise, electromagnetic interference, and variations in transistor size. [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e, \u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. NoC design methods facilitate high integration. Manufacturing defects and device deterioration present enduring challenges. Hardware instability, fluctuations in junction temperature, and voltage degradation may lead to intermittent issues [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. Error detection and correction coding addresses interconnect damage resulting from misinterpretations of information and management signals [3,14]. Crosstalk noise presents a significant challenge in deep sub-micron technology, leading to timing delays and power inefficiencies. The high connector aspect ratio and low wire spacing significantly elevate coupling capacitance, thereby impacting timing, power consumption, and signal integrity [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e22\u003c/span\u003e]. The Crosstalk-Induced Bus Delay (CIBD) in parallel interconnects lacking crosstalk reduction is expressed as (1\u0026thinsp;+\u0026thinsp;4λ) τ0, with λ representing the ratio of coupling capacitance Cc to self-capacitance Cb, and τ0 denoting the delay of a crosstalk-free wire [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. Techniques such as bus inversion [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], shielding, spacing, duplication, and crosstalk avoidance codes (CAC) like Fibonacci codes [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] can reduce CIBD to (1\u0026thinsp;+\u0026thinsp;2λ)τ0. CAC methodologies circumvented conflicting transitions in neighboring interconnects to reduce effective coupling capacitance. Supplementary crosstalk avoidance/reduction codes decrease the CIBD from (1\u0026thinsp;+\u0026thinsp;3λ)τ0 to (1\u0026thinsp;+\u0026thinsp;2λ)τ0 [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. Many coding solutions integrate low-power code (LPC) with error detection and repair, while others present coding techniques that encompass parallel connection power consumption and reliability. A hybrid error correction and detection code utilizing CAC addresses to mitigate crosstalk and other transient fault noise [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e23\u003c/span\u003e]. Error-regulating codes are essential in Network-on-Chip (NoC) for the development of crosstalk-resistant interconnects. Various error detection and correction schemes include dual rail, MDR, boundary shift code (BSC) [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e17\u003c/span\u003e], shield pattern combined with bus inverting code [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], duplicate-add-parity (DAP) and DAPX [\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e25\u003c/span\u003e], simple Hamming codes, CRC, Latin square codes [14], product codes based on Hamming codes [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e16\u003c/span\u003e], among others.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eError-controlling codes that incur overhead in power, latency, and area are essential for ensuring dependability in Network on-chip systems. This work employs different XOR gates to reduce the overhead in power, time, and area associated with error-controlling codes. Research indicates that ECC codes, including two-dimensional parity with duplication, checksum-xor, dual tail, and Hamming, have not yet been implemented utilizing revolutionary XOR gates logic. This paper analysed the power and delay effects of the new XOR gates on error-controlling codes.\u003c/p\u003e\u003cp\u003eThe order of sections is as follows. Section \u003cspan refid=\"Sec2\" class=\"InternalRef\"\u003e2\u003c/span\u003e presents Hamming forward error correcting codes and dual rail code. Section \u003cspan refid=\"Sec5\" class=\"InternalRef\"\u003e3\u003c/span\u003e provides a detailed explanation of checksum-XOR and two-dimensional parity, focusing on their application in duplication error detection codes. Section \u003cspan refid=\"Sec8\" class=\"InternalRef\"\u003e4\u003c/span\u003e illustrates the superiority of unique XOR gate logic over CMOS technology. Section \u003cspan refid=\"Sec11\" class=\"InternalRef\"\u003e5\u003c/span\u003e presents the experimental results, which encompass average power consumption, delay, and the power delay product (PDP). The conclusion of the paper is presented in Section 6.\u003c/p\u003e\n\u003ch3\u003e2. Forward Error Code Correction\u003c/h3\u003e\n\u003cp\u003eError-correcting coding (see Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e19\u003c/span\u003e]) Encodes \"k\" data bits (d\u003csub\u003e0\u003c/sub\u003e, d\u003csub\u003e1\u003c/sub\u003e, \u0026hellip;, d\u003csub\u003ek\u0026minus;1\u003c/sub\u003e) along with \"\u003cem\u003em\u003c/em\u003e\" parity bits into a \"\u003cem\u003en\u003c/em\u003e\"-bit code word (where \u003cem\u003en\u003c/em\u003e\u0026thinsp;=\u0026thinsp;\u003cem\u003em\u0026thinsp;+\u0026thinsp;k\u003c/em\u003e) featuring a Hamming Distance \u003cem\u003eD\u003c/em\u003e, which allows for the correction of up to \u003cem\u003eD\u0026thinsp;\u0026minus;\u0026thinsp;1\u003c/em\u003e errors (with \u003cem\u003eD\u0026thinsp;=\u0026thinsp;3\u003c/em\u003e enabling single-bit correction). A decoder mitigates interconnect noise, such as power and crosstalk, through the implementation of a syndrome generator (SG) and a decoder (SD). SG analyses the received and transmitted data to generate a \"\u003cem\u003em\u003c/em\u003e\"-bit syndrome S. The SD produces an error vector E, which is XORed with the received data (d\u003cem\u003ei\u003c/em\u003e XOR ei) to facilitate correction.\u003c/p\u003e\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\u003ch2\u003e2.1 \u003cem\u003eHamming Code\u003c/em\u003e\u003c/h2\u003e\u003cp\u003eHamming codes are designed to correct single-bit errors using a total of \"\u003cem\u003eh\u003c/em\u003e\" bits, where \"\u003cem\u003eh\u003c/em\u003e\" is the sum of message bits \"\u003cem\u003em\u003c/em\u003e\" and parity bits \"\u003cem\u003ep\u003c/em\u003e\" (\u003cem\u003eh\u003c/em\u003e\u0026thinsp;=\u0026thinsp;\u003cem\u003em\u003c/em\u003e\u0026thinsp;+\u0026thinsp;\u003cem\u003ep\u003c/em\u003e). The inequality 2\u003csup\u003ep\u003c/sup\u003e\u0026thinsp;\u0026ge;\u0026thinsp;\u003cem\u003eh\u003c/em\u003e\u0026thinsp;+\u0026thinsp;1 defines \u003cem\u003ep\u003c/em\u003e, with the optimal value of \u003cem\u003em\u003c/em\u003e calculated as \u003cem\u003em\u003c/em\u003e\u0026thinsp;=\u0026thinsp;2\u003csup\u003e\u003cem\u003ep\u003c/em\u003e\u003c/sup\u003e \u0026ndash;\u003cem\u003ep\u003c/em\u003e-1. The relationship between code length h and m is defined by the inequality \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{{\\text{2}}^{\\text{ℎ}}}{\\text{ℎ+1}}\\text{\u0026ge;}{\\text{2}}^{\\text{m}}\\)\u003c/span\u003e\u003c/span\u003e. The gate count and associated costs are influenced by the variables m and p, as illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\u003ch2\u003e2.2: \u003cem\u003eDual Rail Code\u003c/em\u003e\u003c/h2\u003e\u003cp\u003eThe dual rail configuration (refer to Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e) replicates 8-bit data (C\u003csub\u003e0\u003c/sub\u003e\u0026ndash;C\u003csub\u003e7\u003c/sub\u003e) while calculating C\u003csub\u003e8\u003c/sub\u003e. SG produces a single syndrome bit designated as S0. Multiplexers determine the appropriate bits based on the state of S\u003csub\u003e0\u003c/sub\u003e: when S\u003csub\u003e0\u003c/sub\u003e is set to 0, error-free data is selected; when S0 is set to 1, data or C\u003csub\u003e8\u003c/sub\u003e errors are selected. The system encounters failures with even-numbered data errors; however, it mitigates crosstalk through wire spacing, resulting in improved power efficiency compared to Hamming for larger values of \u003cem\u003em\u003c/em\u003e.\u003c/p\u003e\u003c/div\u003e\n\u003ch3\u003e3. Error Detection Codes\u003c/h3\u003e\n\u003cp\u003eThe implementation of complex multi-bit correction results in a degradation of performance, thereby favouring the use of error detection codes. A code with Hamming Distance \u003cem\u003eD\u003c/em\u003e is capable of detecting \u003cem\u003eD\u003c/em\u003e\u0026thinsp;\u0026minus;\u0026thinsp;1 errors and correcting (\u003cem\u003eD\u003c/em\u003e\u0026thinsp;\u0026minus;\u0026thinsp;1)/2 errors.\u003c/p\u003e\u003cdiv id=\"Sec6\" class=\"Section2\"\u003e\u003ch2\u003e3.1 \u003cem\u003eChecksum-XOR Based\u003c/em\u003e\u003c/h2\u003e\u003cp\u003eData (e.g., D\u003csub\u003e0\u003c/sub\u003e\u0026ndash;D\u003csub\u003e7\u003c/sub\u003e) is organized into a 2D matrix, with column checksums calculated as follows: CS_D\u003csub\u003e0\u003c/sub\u003e\u0026thinsp;=\u0026thinsp;D\u003csub\u003e0\u003c/sub\u003e XOR D\u003csub\u003e1\u003c/sub\u003e, and transmitted accordingly. Receivers perform checksum recalculation; a zero value indicates acceptance of data, while a non-zero value triggers retransmission. The system demonstrates efficiency; however, it encounters failures related to errors in even-numbered columns (see Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e).\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\u003ch2\u003e3.2 \u003cem\u003eTwo-Dimensional Parities with Duplication (2DPD)\u003c/em\u003e\u003c/h2\u003e\u003cp\u003e2DPD (Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e) attains a performance level of D\u0026thinsp;=\u0026thinsp;4, enabling the detection of 3-bit errors or the correction of 1-bit errors while also detecting 2-bit errors. Duplication allows for D\u0026thinsp;=\u0026thinsp;8, facilitating the detection of 7-bit errors and minimizing crosstalk. Encoding calculates the row and column parities in a two-dimensional matrix, transmitting a total of 2(K\u0026thinsp;+\u0026thinsp;C\u0026thinsp;+\u0026thinsp;R\u0026thinsp;+\u0026thinsp;1) bits. Decoding employs XOR operations for the generation of check bits and for the issuance of retransmission requests (REQ). If REQ equals 0, data is accepted; if not, retransmission will take place. The system experiences failure when encountering seven or more errors, resulting in elevated power and space costs.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003eNormalized word size of ECC coding schemes to transmit\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"5\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cthead\u003e\u003ctr\u003e\u003cth align=\"left\" colname=\"c1\"\u003e\u003cp\u003eScheme\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c2\"\u003e\u003cp\u003e64 bit\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c3\"\u003e\u003cp\u003e32 bit\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c4\"\u003e\u003cp\u003e16 bit\u003c/p\u003e\u003c/th\u003e\u003cth align=\"left\" colname=\"c5\"\u003e\u003cp\u003e8 bit\u003c/p\u003e\u003c/th\u003e\u003c/tr\u003e\u003c/thead\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eHamming code\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e\u003cp\u003e71\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e\u003cp\u003e38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e\u003cp\u003e21\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e\u003cp\u003e12\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eDual rail\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e\u003cp\u003e129\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e\u003cp\u003e65\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e\u003cp\u003e33\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e\u003cp\u003e17\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003eChecksum-xor\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e\u003cp\u003e68\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e\u003cp\u003e36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e\u003cp\u003e20\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e\u003cp\u003e10\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\"\u003e\u003cp\u003e2DPD\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e\u003cp\u003e162\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e\u003cp\u003e90\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e\u003cp\u003e50\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e\u003cp\u003e30\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003c/div\u003e\n\u003ch3\u003e4. NOVEL XOR GATES\u003c/h3\u003e\n\u003cdiv id=\"Sec9\" class=\"Section2\"\u003e\u003ch2\u003e4.1. \u003cem\u003eFULL SWING XOR GATE\u003c/em\u003e\u003c/h2\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a) presents the complete configuration of the XOR/XNOR gate implemented through double pass-transistor logic (DPL). The configuration is comprised of eight transistors. The output of these structures is fully operational; however, the main concern with this circuit is the use of two high power consumption NOT gates situated on the critical path. Increasing the dimensions of the transistors in NOT gates is necessary to achieve a reduction in critical path delay. This modification will lead to an increase in capacitance at the intermediate node. As a result, there will be a minor increase in both delay and power consumption. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b) illustrates the full-swing XOR/XNOR gate implemented using pass-transistor logic. This circuit is constructed utilizing six transistors. The delay and power performance surpass that of Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a). The issue with this circuit involves the utilization of a NOT gate within the critical path.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(c) illustrates the full-swing XOR-XNOR gate constructed using CPL logic. This configuration is implemented with a total of ten transistors. The PMOS transistors in this configuration are arranged in a cross-coupled structure connected to the outputs. The issue with this circuit involves the implementation of feedback through a cross-coupled structure at the outputs, which results in increased delay and short-circuit power. Additionally, NOT gates are present on the critical path. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(d) illustrates an additional XOR-XNOR circuit. The design incorporates eight transistors, as illustrated below. The critical path of the circuit exceeds that depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(c). The short circuit current will flow in the circuit when the input transitions from logic \"01\" to \"00\".\u003c/p\u003e\u003cp\u003eSix transistors form the full-swing XOR-XNOR gate in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e). The feedback transistors (N3 and P3) restore weak logic levels at the output nodes (XOR and XNOR) when inputs are \u0026ldquo;00\u0026rdquo; or \u0026ldquo;11.\u0026rdquo; The worst-case delay causes the output voltage to reach its final voltage in two phases. Short circuit current flows when the feedback mechanism is not fully activated. This circuit is sensitive to process, voltage, and temperature changes. Ten transistors form the full-swing XOR-XNOR gate in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(f). This setup resolves delayed response times. This circuit has full-swing output and great driving power. The feedback circuit adds parasitic capacitance to the XOR and XNOR gate output nodes. Power usage and delay rise slightly. Ten transistors form the full-swing XOR-XNOR gate in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(g). The circuit's power consumption increases when a NOT gate creates a large intermediate node capacitance. More electricity is used than in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(f).\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec10\" class=\"Section2\"\u003e\u003ch2\u003e4.2 \u003cem\u003eNON FULL SWING XOR CIRCUIT\u003c/em\u003e\u003c/h2\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) illustrates the non-full-swing XOR-XNOR gate, comprising four transistors. This circuit is characterized by its inability to achieve the final voltage value at the output. This circuit exhibits efficiency regarding power consumption and latency.\u003c/p\u003e\u003cp\u003eFigure 6(i) The new XOR-XNOR circuit mitigates the problems associated with previous XOR and XNOR circuits. The circuit configuration is characterized by little output capacitance, and the critical path lacks NOT gates. It consumes less electricity and functions at an exceptionally rapid velocity. The features of this circuit are its full-swing output and robust driving capacity.\u003c/p\u003e\u003c/div\u003e"},{"header":"Results and Conclusions","content":"\u003cp\u003eFigures \u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a) to 6(i) show how XOR gates implement regulating codes. Five XOR gates in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e), and Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) demonstrate ECC efficiency improvements. This work was realised using CADENCE VIRTUOSO tool in 45nm technology. The results are in Tables\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e\u0026ndash;\u003cspan refid=\"Tab7\" class=\"InternalRef\"\u003e7\u003c/span\u003e. Table\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows power, latency, and PDP performance data for 8, 16, and 32-bit Hamming code. Table\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows that Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) has the lowest Hamming Encoder PDP values for 8-bit (3.07) and 16-bit (11.8) configurations. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) displays the 32-bit configuration's lowest PDP (67.15). Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) shows the lowest Hamming Decoder PDP for 8-bit (10.14), while Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) shows the lowest for 16-bit (25.59) and 32-bit (78.2). In Hamming CODEC, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) shows the lowest CODEC PDP for 8-bit (13.6) and 16-bit (37.39) configurations, while Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) shows the lowest for 32-bit (129.09).\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab2\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePerformance measure of Hamming code in terms of Power, Delay and PDP for 8, 16, and 32-bit\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"9\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c5\" namest=\"c3\"\u003e\u003cp\u003eENCODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c8\" namest=\"c6\"\u003e\u003cp\u003eDECODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003eCODEC\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.319\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e15.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e5.05\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.82\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e24\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e19.68\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e24.73\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.318\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e9.65\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e3.07\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.81\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e10.53\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e13.6\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.365\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e11.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e4.35\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e10.14\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e14.49\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.297\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e12.5\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e3.72\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e14\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e10.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e14.08\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.319\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e33.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e10.79\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e29\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e26.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e36.89\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.922\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e41.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e38.54\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.85\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e58\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e49.3\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e87.84\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.559\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e21.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e11.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e32.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e25.59\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e37.39\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e25.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e18.58\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.77\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e34\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e26.18\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e44.76\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.64\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e16.64\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.73\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e26.28\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e42.92\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.934\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e45.77\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e72.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e59.85\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e105.62\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.23\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e88.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e108.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.88\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e99.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e87.92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e196.66\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.779\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e62.3\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e48.54\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.85\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e78.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e126.74\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.872\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e75.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e66.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e71.38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e137.48\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.831\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e80.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e67.15\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e79.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e61.94\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e129.09\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.885\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e155\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e137.18\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.91\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e112\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e101.92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e239.1\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab3\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 3\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePerformance measure of Dual rail code in terms of Power, Delay and PDP for 8, 16, and 32-bit\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"9\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c5\" namest=\"c3\"\u003e\u003cp\u003eENCODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c8\" namest=\"c6\"\u003e\u003cp\u003eDECODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003eCODEC\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.293\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e10.5\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e3.08\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.96\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e12\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e11.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e14.6\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.429\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e4.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.96\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e2.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e2.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e4.2\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.433\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e3.5\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e4.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e4.18\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e5.7\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.483\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e3.5\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.7\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e3.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e3.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e5.18\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.483\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e17.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e8.26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e14.3\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e22.56\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.445\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e8.99\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.97\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e22\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e21.34\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e30.33\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.392\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e7.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e2.87\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.97\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e4.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e4.27\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e7.14\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.112\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e9.01\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.01\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.96\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e9.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e9.03\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e10.04\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.152\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e9.07\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.93\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e7.64\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e7.11\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e8.49\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e33.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e16.13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e91.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e55.08\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e71.21\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.634\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e40.3\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e25.56\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.97\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e40\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e38.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e64.36\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.265\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e27.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e7.21\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.97\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e10.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e10.57\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e17.78\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.122\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e18.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e2.25\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e18\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e17.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e19.35\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.149\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e19.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e2.85\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.97\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e16.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e15.91\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e18.76\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e77.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e93.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.17\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e97.11\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e190.59\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab3\" class=\"InternalRef\"\u003e3\u003c/span\u003e presents the Power, Delay, and PDP performance for 8, 16, and 32-bit Dual rail codes. According to Table\u0026nbsp;\u003cspan refid=\"Tab3\" class=\"InternalRef\"\u003e3\u003c/span\u003e, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) consistently attains the lowest PDP across all bit sizes for dual rail encoders, whereas Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) demonstrates the highest efficiency for decoders. In the case of the Dual rail CODEC, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) consistently exhibits the lowest Power Delay Product (PDP). Utilize Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) for decoders and CODEC, and Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) for encoders in low-power, low-PDP applications. For low-latency applications, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) is optimal for encoders (16-bit and 32-bit), whereas Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) or e are suitable for decoders.\u003c/p\u003e\u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab4\" class=\"InternalRef\"\u003e4\u003c/span\u003e presents the performance of 8, 16, and 32-bit checksums in terms of power, latency, and PDP. The Checksum Encoder's minimum PDP for 8-bit, 16-bit, and 32-bit is presented in Table\u0026nbsp;\u003cspan refid=\"Tab4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) illustrates the lowest eight-bit PDP, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) depicts the lowest sixteen-bit PDP, and Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(j) represents the lowest thirty-two-bit PDP. The decoder efficiency is maximized in Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) and 6(i). Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) exhibits the lowest CODEC PDP among all bit sizes. Utilize Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) for the encoder and decoder in low-delay applications across all bit sizes. For low-power applications, refer to Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) for encoders and 8-bit/16-bit decoders, and (b) for 32-bit decoders. The efficiency of the CODEC and decoder (PDP) is maximized in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), although the encoder efficiency is superior in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b) or (h).\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab4\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 4\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePerformance measure of Checksum-XOR based code in terms of Power, Delay and PDP for 8, 16, and 32-bit\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"9\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c5\" namest=\"c3\"\u003e\u003cp\u003eENCODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c8\" namest=\"c6\"\u003e\u003cp\u003eDECODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003eCODEC\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.139\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e5.21\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e6.69\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.62\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e48.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e3.24\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e9.93\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.049\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e5.17\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e2.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.56\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e60.09\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e2.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e5.85\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.12\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e6.56\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e7.22\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.82\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e60.13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e5.38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e12.6\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e4.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e5.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.694\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e40\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e3.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e8.6\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.223\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e5.264\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e13.39\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.814\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e60.04\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e4.29\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e17.68\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.449\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e18.11\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e21.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.063\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e48.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e19.26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e40.86\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.215\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e15.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e17.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.711\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e80\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e10.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e27.94\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.593\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e47.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.397\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e80.12\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e29.03\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e76.55\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e10.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e31.55\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.82\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e65.72\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e8.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e40.15\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.697\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.16\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e55.76\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.458\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e80\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e29.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e85.16\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.683\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e40.3\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e32.86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.996\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e48.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e80.44\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e113.3\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.34\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e40.17\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e54.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.905\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e160\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e36.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e90.76\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e52.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e152.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.44\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e160.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e75.33\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e227.43\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.37\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e40.17\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e49.07\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.39\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e132.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e55.84\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e104.91\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.003\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e55.25\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e161.49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.625\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e161\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e145.04\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e306.53\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eThe performance metrics for 2DPD are shown in Table\u0026nbsp;\u003cspan refid=\"Tab5\" class=\"InternalRef\"\u003e5\u003c/span\u003e, with particular attention paid to power, delay, and PDP for 8, 16, and 32-bit configurations. Table\u0026nbsp;\u003cspan refid=\"Tab5\" class=\"InternalRef\"\u003e5\u003c/span\u003e shows that Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) consistently shows the lowest encoder PDP for all bit sizes. Across all bit sizes, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) shows the decoder PDP's maximum efficiency. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) consistently demonstrates the lowest CODEC PDP across all bit sizes. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) displays competitive results in terms of delay and power consumption, while Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) shows superior performance for both the encoder and the decoder in terms of delay and PDP. While decoders often show lower power consumption in novel designs, encoders show lower delays than decoders across a range of bit sizes. For 32-bit, decoder PDPs are higher than encoder PDPs due to higher delays; however, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) successfully mitigates this discrepancy. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h): It is a good option for applications that need low latency and energy efficiency because it performs optimally for delay (encoder and decoder) and PDP (encoder, decoder, and CODEC) across all bit sizes. Along with the decoder PDP for 16-bit, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) shows competitiveness in encoder delay and power, making it suitable for designs that place a high priority on power efficiency. For low-latency applications, it is recommended to use Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) for both the encoder and decoder for all bit sizes, and Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) as a reliable substitute for encoders only. For 8-bit and 16-bit decoders in low-power applications, see Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e); for encoders and 32-bit decoders, use Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) or Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i). For all components and bit sizes, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) is the best choice in terms of overall efficiency (PDP).\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab5\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 5\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePerformance measure of 2DPD code in terms of Power, Delay and PDP for 8, 16, and 32-bit\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"9\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c9\" colnum=\"9\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c5\" namest=\"c3\"\u003e\u003cp\u003eENCODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"3\" nameend=\"c8\" namest=\"c6\"\u003e\u003cp\u003eDECODER\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003eCODEC\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003eDELAY (ps)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003ePOWER (\u0026micro;W)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003ePDP (10^-18J)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.488\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.03\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e9.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.63\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e10.327\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e16.84\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e26.62\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.249\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e18.26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e4.55\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.98\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e5.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e5.26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e9.81\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.484\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.03\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e9.7\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.603\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e5.314\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e8.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e18.22\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.23\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e4.65\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e0.985\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e6.288\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e6.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e10.85\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e2.55\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e20.99\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e53.53\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.431\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e9.382\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e22.81\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e76.34\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.76\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e35.65\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e27.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.455\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e16.83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e41.32\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e68.42\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.39\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e26.51\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e10.34\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.26\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e8.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e11.02\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e21.36\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.76\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e35.65\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e27.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e1.429\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e8.66\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e12.38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e39.48\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e35.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e12.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.445\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e10.25\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e25.07\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e38.02\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e4.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e42.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e173.68\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e3.659\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e14.32\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e52.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e226.08\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.06\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e63.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e67.61\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e4.752\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e30.06\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e142.85\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e210.46\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.54\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e47.43\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e25.62\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.48\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e15.61\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e38.72\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e64.34\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.05\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e68.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e72.22\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2.86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e16.47\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e47.11\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e119.33\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e0.49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e64.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e31.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e4.678\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e14.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e66.95\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e98.47\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e5.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e75.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e418.31\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e6.958\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c7\"\u003e\u003cp\u003e25.57\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c8\"\u003e\u003cp\u003e177.92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c9\"\u003e\u003cp\u003e596.23\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab6\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 6\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePDP Efficiency (%) improvement of Hamming Code, Dual rail, Checksum, 2DPD CODEC using XOR gate shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"6\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"4\" nameend=\"c6\" namest=\"c3\"\u003e\u003cp\u003eImproved PDP Efficiency (%)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eHC\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003eDR\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003eCS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2DPD\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e45.01\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e71.24\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e41.09\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e63.15\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e6.15\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e26.32\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e53.58\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e46.16\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e3.41\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e18.92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e31.98\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e9.59\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e63.14\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e81.39\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e66.92\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e87.15\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e57.44\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e76.46\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e31.63\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e68.79\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e16.47\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e28.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e63.51\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e45.9\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e12.89\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e15.91\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e30.42\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e43.82\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e64.6\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e89.98\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e67.2\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e90.56\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e35.56\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e72.38\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e19.9\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e69.43\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e7.82\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e8.12\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e60.1\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e46.09\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e1.83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e5.23\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e13.49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e34.67\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e47\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e90.68\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e70.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e89.21\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eThe XOR gate implementation shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) exhibits notable enhancements in Power Delay Product (PDP) efficiency across various error-correcting code realizations, such as Hamming, Dual Rail, Checksum, and 2DPD codes, for configurations of 8-bit, 16-bit, and 32-bit. The enhancements are evaluated in comparison to various XOR gate implementations illustrated in Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(e), 6(i), along with a standard CMOS implementation. The results consistently demonstrate the enhanced performance of the Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) design, especially for Dual Rail and 2DPD codes, with efficiency improvements frequently surpassing 80% relative to the CMOS baseline.\u003c/p\u003e\u003cp\u003eThe Hamming code implementation utilizing the XOR gate as depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) demonstrates enhancements in PDP efficiency of 45.01%, 6.15%, 3.41%, and 63.14% for the 8-bit configuration when compared to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates improvements of 57.44%, 16.47%, 12.89%, and 64.60%. In contrast, the 32-bit configuration shows gains of 35.56%, 7.82%, 1.83%, and 47.00% when compared to the same respective baselines. The results demonstrate a strong performance across different bit widths, highlighting significant efficiency benefits compared to the CMOS implementation.\u003c/p\u003e\u003cp\u003eThe implementation of the Dual Rail code using the XOR gate as illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) demonstrates significant improvements in PDP efficiency. The 8-bit configuration demonstrates improvements of 71.24%, 26.32%, 18.92%, and 81.39% when compared to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(e), 6(i), and the CMOS baseline, respectively. The 16-bit configuration demonstrates increased gains of 76.46%, 28.89%, 15.91%, and 89.98%. In comparison, the 32-bit configuration records gains of 72.38%, 8.12%, 5.23%, and 90.68% relative to the same baselines. The results highlight the remarkable efficiency of the Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) design for Dual Rail codes, especially in comparison to CMOS, with enhancements nearing or surpassing 90%.\u003c/p\u003e\u003cp\u003eThe Checksum code utilizes the XOR gate realization depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), which demonstrates PDP efficiency enhancements of 41.09%, 53.58%, 31.98%, and 66.92% for the 8-bit configuration when compared to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates enhancements of 31.63%, 63.51%, 30.42%, and 67.20%. In contrast, the 32-bit configuration exhibits improvements of 19.90%, 60.10%, 13.49%, and 70.40% when compared to the same baselines. The results indicate consistent performance enhancements, with the most notable improvements recorded in comparison to Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) and CMOS.\u003c/p\u003e\u003cp\u003eThe implementation of the 2DPD code utilizing the XOR gate as depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) demonstrates enhancements in PDP efficiency of 63.15%, 46.16%, 9.59%, and 87.15% for the 8-bit configuration when compared to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(e), 6(i), and CMOS, respectively. The 16-bit configuration demonstrates improvements of 68.79%, 45.90%, 43.82%, and 90.56%. In comparison, the 32-bit configuration exhibits gains of 69.43%, 46.09%, 34.67%, and 89.21% relative to the same baselines. The results demonstrate that the implementation shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) exhibits superior performance, especially at higher bit widths and in comparison to the CMOS baseline, where the observed efficiency gains are among the highest recorded.\u003c/p\u003e\u003cp\u003e\u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab7\" border=\"1\"\u003e\u003ccaption language=\"En\"\u003e\u003cdiv class=\"CaptionNumber\"\u003eTable 7\u003c/div\u003e\u003cdiv class=\"CaptionContent\"\u003e\u003cp\u003ePDP Efficiency (%) improvement of Hamming Code, Dual rail, Checksum, 2DPD CODEC using XOR gate shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i)\u003c/p\u003e\u003c/div\u003e\u003c/caption\u003e\u003ccolgroup cols=\"7\"\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e\u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e\u003ctbody\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"1\" rowspan=\"2\"\u003e\u0026nbsp;\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\" morerows=\"1\" rowspan=\"2\"\u003e\u003cp\u003eType of Circuit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"5\" nameend=\"c7\" namest=\"c3\"\u003e\u003cp\u003eImproved PDP Efficiency (%)\u003c/p\u003e\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003eHC\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003eDR\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003eCS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e2DPD\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e8-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e43.07\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e64.53\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e13.4\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e59.25\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e-3.53\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e-23.34\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e-47.01\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e-10.61\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e2.83\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e9.13\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e31.75\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e40.46\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e61.84\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e77.04\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e51.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e85.79\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e16-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e51.14\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e72.01\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e1.74\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e44.44\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e-14.8\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e-18.91\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e-43.71\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e-78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e4.12\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e15.44\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e47.56\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e3.7\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e59.37\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e88.08\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e52.86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e83.19\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e\u003cp\u003e32-Bit\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e34.36\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e70.86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e7.42\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e53.22\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e-1.86\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e-5.52\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e-15.58\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e-53.05\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eFigure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e)\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e6.11\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e3.05\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e53.88\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e17.49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003ctr\u003e\u003ctd align=\"left\" colname=\"c2\"\u003e\u003cp\u003eCMOS\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c3\"\u003e\u003cp\u003e46.02\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c4\"\u003e\u003cp\u003e90.16\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c5\"\u003e\u003cp\u003e65.78\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colname=\"c6\"\u003e\u003cp\u003e83.49\u003c/p\u003e\u003c/td\u003e\u003ctd align=\"left\" colspan=\"1\" nameend=\"c7\" namest=\"c7\"\u003e\u0026nbsp;\u003c/td\u003e\u003c/tr\u003e\u003c/tbody\u003e\u003c/colgroup\u003e\u003c/table\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eWith configurations of 8-bit, 16-bit, and 32-bit widths, the Power-Delay Product (PDP) efficiency of the XOR gate implementation shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) was assessed across the realizations of the Hamming, Dual Rail, Checksum, and 2DPD error-correcting codes. Figures\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(h), and 6(e) compare the PDP efficiency to a baseline CMOS design and various XOR gate implementations. With benefits ranging from 1.74\u0026ndash;90.16%, the results show significant efficiency increases in the majority of comparisons, especially when compared to CMOS. In contrast to Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), the implementation continuously exhibits worse efficiency; performance gaps are indicated by negative values for all bit widths and coding schemes.\u003c/p\u003e\u003cp\u003eIn comparison to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(h), 6(e), and CMOS, the XOR gate realization in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) for the 8-bit configuration achieves PDP efficiency increases of 43.07%, -3.53%, 2.83%, and 61.84% for the Hamming code, respectively. The increases versus the identical baselines are 51.14%, -14.80%, 4.12%, and 59.37% in the 16-bit configuration and 34.36%, -1.86%, 6.11%, and 46.02% in the 32-bit setup. Although notable efficiency gains are seen versus CMOS and other configurations, the negative values against Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) show that it performs better than Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i).\u003c/p\u003e\u003cp\u003eSignificant PDP efficiency benefits are shown by the Dual Rail code implementation using the XOR gate in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i), especially when compared to CMOS. Comparing the 8-bit arrangement to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(h), 6(e), and CMOS, the improvements are 64.53%, -23.34%, 9.13%, and 77.04%, respectively. In comparison to the identical baselines, the 32-bit configuration achieves 70.86%, -5.52%, 3.05%, and 90.16%, while the 16-bit configuration displays increases of 72.01%, -18.91%, 15.44%, and 88.08%. Although Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) is still less efficient than Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), its strength is shown by the significant efficiency gains vs CMOS, particularly in the 32-bit arrangement.\u003c/p\u003e\u003cp\u003eIn comparison to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(h), 6(e), and CMOS, the XOR gate realization in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) offers PDP efficiency increases of 13.40%, -47.01%, 31.75%, and 51.36% for the 8-bit configuration for the Checksum code, respectively. Compared to the identical baselines, the 16-bit configuration improves by 1.74%, -43.71%, 47.56%, and 52.86%, whereas the 32-bit configuration improves by 7.42%, -15.58%, 53.88%, and 65.78%. Although there are still notable advances over Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) and CMOS, the notable decreases in efficiency relative to Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), especially in the 8-bit and 16-bit designs, suggest a performance difference.\u003c/p\u003e\u003cp\u003eIn comparison to Figs.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), 6(h), 6(e), and CMOS, the 2DPD code implementation using the XOR gate in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) yields PDP efficiency increases of 59.25%, -10.61%, 40.46%, and 85.79% for the 8-bit configuration, respectively. Compared to the identical baselines, the benefits for the 32-bit configuration are 53.22%, -53.05%, 17.49%, and 83.49%, whereas the gains for the 16-bit configuration are 44.44%, -78.00%, 3.70%, and 83.19%. Even though the 16-bit configuration has a large negative value compared to Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), which indicates a big performance gap, the design still proves to be effective in certain cases because it shows significant efficiency improvements over CMOS.\u003c/p\u003e"},{"header":"Conclusion","content":"\u003cp\u003eIn comparison to the realizations in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e), Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i), and CMOS, the XOR gate realization in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) consistently offers notable improvements in PDP (Power-Delay Product) efficiency across a range of bit sizes (8-bit, 16-bit, and 32-bit) and coding schemes (Hamming, Dual rail, Check sum, and 2DPD). The Dual rail and 2DPD codes show the most advantages, especially when compared to CMOS, where efficiency increases frequently surpass 80%. The improvements vary from 1.83\u0026ndash;90.68%.\u003c/p\u003e\u003cp\u003eIn comparison to the XOR gate realizations in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e), and CMOS, the XOR gate realization in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) offers enhanced PDP (Power-Delay Product) efficiency across a range of bit sizes (8-bit, 16-bit, and 32-bit) and coding schemes (Hamming, Dual rail, Check sum, and 2DPD), with efficiency gains ranging from 1.74\u0026ndash;90.16%. Remarkably, Dual rail and 2DPD codes show the biggest improvements over CMOS, frequently above 80%. With negative values ranging from \u0026minus;\u0026thinsp;1.86% to -78% across all coding schemes and bit sizes, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(i) consistently displays lower PDP efficiency than Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h), suggesting that Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(h) performs better in those situations.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eM. Mutyam et al., Fibonacci codes for cross talk avoidance. IEEE Trans. (VLSI) Syst. 20(10), 1899\u0026ndash;1903 (2012)\u003c/li\u003e\n\u003cli\u003eB.K. Kaushik, D. Agarwal, Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects. Elsevier Trans. Microelectron. J.44\u003cstrong\u003e,\u003c/strong\u003e 827\u0026ndash;833 (2013)\u003c/li\u003e\n\u003cli\u003eN. Jafarzadesh, M. Palesi, Data encoding techniques for reducing energy consumption in network-onchip. IEEE Trans. VLSI Syst. 22(3), 675\u0026ndash;685 (2014)\u003c/li\u003e\n\u003cli\u003eW.N. Flayyih, K. Samsudin, Crosstalk-aware multiple error detection scheme based on two dimensional parities for energy efficient network on chip. IEEE Trans. Circuits Syst. 1 \u003cstrong\u003e61\u003c/strong\u003e, 2034\u0026ndash;2047 (2014)\u003c/li\u003e\n\u003cli\u003eSundarrajan Rangachari, Jaiganesh Balakrishnan, and Nitin Chandrachoodan, \u0026lsquo;\u0026lsquo;Scenario-Aware Dynamic Power Reduction Using Bias Addition,\u0026rdquo; in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 2,February 2017, pp.450\u0026ndash;461.\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eYang, J., \u0026amp; Kumar, R. (2017). \u003c/strong\u003e\u003cem\u003eCrosstalk-Resistant Coding Techniques for Scalable NoC Interconnects. ACM Journal on Emerging Technologies in Computing Systems, 13(3), 38. \u003c/em\u003ehttps://doi.org/10.1145/3085592\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eAbdollahi, A., Fallah, F., \u0026amp; Pedram, M. (2017). \u003c/strong\u003e\u003cem\u003eEvaluation of 2-Dimensional Parity Techniques for Error Detection in SoC Memory Architectures.Microelectronics Reliability, 74, 146\u0026ndash;153. \u003c/em\u003ehttps://doi.org/10.1016/j.microrel.2017.05.016\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eKumar, M., \u0026amp; Chauhan, D. S. (2018). \u003c/strong\u003e\u003cem\u003eHigh Speed and Low Power XOR/XNOR Design Techniques: A Review. Microprocessors and Microsystems, 61, 1\u0026ndash;14. \u003c/em\u003ehttps://doi.org/10.1016/j.micpro.2018.04.002\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eChen, X., et al. (2018). \u003c/strong\u003e\u003cem\u003eDesign and Analysis of Error Control Schemes for Reliable Network-on-Chip Architectures.IEEE Transactions on Computers, 67(6), 855\u0026ndash;867. \u003c/em\u003ehttps://doi.org/10.1109/TC.2017.2780224\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eRahimi, A., et al. (2018). \u003c/strong\u003e\u003cem\u003eChecksum and Redundancy Coding for Fault Tolerance in Data-Intensive SoC Systems. IEEE Transactions on Computers, 67(9), 1322\u0026ndash;1335. \u003c/em\u003ehttps://doi.org/10.1109/TC.2018.2817121\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eNasri, M., \u0026amp; Torkestani, J. A. (2018). \u003c/strong\u003e\u003cem\u003eAdaptive Error Correction Technique for Crosstalk Reduction in VLSI Interconnects. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10), 3432\u0026ndash;3444. \u003c/em\u003ehttps://doi.org/10.1109/TCSI.2018.2829022\u003c/li\u003e\n\u003cli\u003eChennakesavulu, M., Jayachandra Prasad, T., Sumalatha, V., 2018. Improved Performance of Error Controlling Codes Using Pass Transistor Logic. Circ. Syst.Sig. Process. 37 (3), 1145\u0026ndash;1161. Springer publications.\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eSaxena, A., \u0026amp; Chauhan, D. S. (2019). \u003c/strong\u003e\u003cem\u003eDesign and Analysis of Low Power XOR Gate Using Novel 4T and 6T Logic Styles. Microelectronics Journal, 88, 1\u0026ndash;10. \u003c/em\u003ehttps://doi.org/10.1016/j.mejo.2019.04.001\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eTaghavi, M., \u0026amp; Alipour, M. (2020). \u003c/strong\u003e\u003cem\u003eAn Efficient ECC Architecture for Reliable Low-Power Network-on-Chip Communication. Integration, the VLSI Journal, 72, 125\u0026ndash;134. https://doi.org/10.1016/j.vlsi.2020.05.004\u003c/em\u003e\u003c/li\u003e\n\u003cli\u003e\u003cstrong\u003eKiani, M., \u0026amp; Pedram, M. (2021). \u003c/strong\u003e\u003cem\u003eDual-Rail Logic Design in Low-Swing Noise-Immune Digital Circuits. Integration, the VLSI Journal, 76, 45\u0026ndash;54. \u003c/em\u003ehttps://doi.org/10.1016/j.vlsi.2021.03.001\u003c/li\u003e\n\u003cli\u003eSharma, V., \u0026amp; Gupta, P. (2023). Hamming Codes and Their Applications in Modern Digital Systems. International Journal of Circuit Theory and Applications, 51(7), 1567\u0026ndash;1580.\u003c/li\u003e\n\u003cli\u003eSingh, P., \u0026amp; Kumar, S. (2023). Hybrid Error Correction Codes for Crosstalk-Resistant NoC Interconnects. IEEE Transactions on Very Large Scale Integration Systems, 31(6), 789\u0026ndash;801.\u003c/li\u003e\n\u003cli\u003eWang, Z., \u0026amp; Zhang, Q. (2023). Low-Power XOR Gate Designs for Error-Correcting Codes in SoC. IEEE Journal of Solid-State Circuits, 58(9), 2345\u0026ndash;2357. \u003c/li\u003e\n\u003cli\u003eChen, X., \u0026amp; Li, Y. (2023). Advances in Network-on-Chip Design for Low-Power SoC Applications. IEEE Transactions on Circuits and Systems, 70(5), 1234\u0026ndash;1246. \u003c/li\u003e\n\u003cli\u003eKumar, A., \u0026amp; Singh, R. (2024). Error Detection and Correction in Data Link Layer Protocols Using Checksum-XOR. Journal of Network and Computer Applications, 220, 103245.\u003c/li\u003e\n\u003cli\u003eZhang, H., \u0026amp; Liu, M. (2024). Fault-Tolerant Interconnect Designs for Network-on-Chip Systems. ACM Transactions on Embedded Computing Systems, 23(2), 89\u0026ndash;102. \u003c/li\u003e\n\u003cli\u003eLiu, T., \u0026amp; Chen, J. (2024). Impact of Coupling Capacitance on NoC Performance and Power Efficiency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(4), 1012\u0026ndash;1024.\u003c/li\u003e\n\u003cli\u003eGupta, R., \u0026amp; Sharma, A. (2024). Crosstalk Mitigation in NoC Using Error Detection and Correction Codes. Journal of VLSI Design, 45(3), 567\u0026ndash;579. \u003c/li\u003e\n\u003cli\u003eLee, S., \u0026amp; Kim, H. (2025). Novel XOR Gate Topologies for Low-Power VLSI Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 72(2), 345\u0026ndash;357.\u003c/li\u003e\n\u003cli\u003ePatel, N., \u0026amp; Desai, R. (2025). Dual Rail and 2DPD Codes for Enhanced Fault Tolerance in SoC Designs. Journal of Electronic Design and Automation, 50(1), 45\u0026ndash;58.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"Jawaharlal Nehru Technological University Anantapur","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"System on Chip, Data link layer protocols, Error Controlling Codes, XOR, Low-power design","lastPublishedDoi":"10.21203/rs.3.rs-7347519/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7347519/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eError correction codes (ECCs) are essential for maintaining data integrity in sophisticated digital systems, including System-on-Chip (SoC) architectures and Data Link Layer protocols. This work introduces a VLSI-optimized implementation of Hamming, Dual Rail, Checksum-XOR, and Two-Dimensional Parity with Duplication (2DPD) codes, highlighting their effectiveness in error detection and correction. The suggested method utilizes innovative XOR gate topologies realized in complementary metal-oxide-semiconductor (CMOS) technology to attain high-speed, low-power performance and improved throughput. The XOR gate implementation in Fig.\u0026nbsp;6(h) exhibits enhanced performance, attaining considerable increases in Power-Delay Product (PDP) efficiency. Hamming codes provide single-error rectification and double-error detection via strategic placement of parity bits, whereas Checksum-XOR improves error detection in protocols such as TCP and UDP. Dual Rail coding enhances fault tolerance in safety-critical System-on-Chip designs by utilizing signal redundancy, while 2DPD provides resilient error correction for memory arrays and specific network topologies. Experimental findings indicate that Fig.\u0026nbsp;6(h) attains PDP efficiency enhancements of up to 90.68% for Dual Rail and 90.56% for 2DPD codes relative to CMOS across 8-bit, 16-bit, and 32-bit configurations, demonstrating consistent superiority over other XOR gate designs depicted in Figs.\u0026nbsp;6(b), 6(e), and 6(i). Thorough trade-off evaluations of redundancy, computational complexity, and error-correction capacity substantiate the proposed designs, especially Fig.\u0026nbsp;6(h), as exceptionally appropriate for low-power, high-performance applications in contemporary digital systems.\u003c/p\u003e","manuscriptTitle":"Improved performance of Error Controlling Codes using novel XOR gates","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-08-12 11:32:05","doi":"10.21203/rs.3.rs-7347519/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"1d238505-6323-4225-aba1-fb5e2ca71452","owner":[],"postedDate":"August 12th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":52986851,"name":"Electronic Materials and Devices"}],"tags":[],"updatedAt":"2025-08-12T11:32:06+00:00","versionOfRecord":[],"versionCreatedAt":"2025-08-12 11:32:05","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7347519","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7347519","identity":"rs-7347519","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}