Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays

Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Physical Sciences - Article Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays Zhiyong Zhang, Jianshuo Zhou, Li Ding, Lin Xu, Xiaohan Cheng, and 6 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-2526224/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 02 Oct, 2025 Read the published version in Nature Electronics → Version 1 posted You are reading this latest preprint version Abstract The development of wireless communications is driving the need for compact radiofrequency (RF) devices with up to terahertz (THz) frequency and fabrication processes compatible with that of complementary-metal-oxide-semiconductor (CMOS) transistors. Aligned carbon nanotube (A-CNT) film is a promising candidate semiconductor that can be used to build both CMOS field-effect transistors (FETs) for digital integrated circuits (ICs) and radiofrequency (RF) transistors with frequencies beyond 1 THz for analogue ICs. Herein, we demonstrate the first MOS FET with a cut-off frequency beyond 1 THz on a high-quality A-CNT array film, and with a carrier mobility of 2,000 cm 2 V − 1 s − 1 and better scaling characteristics than all semiconductors, including GaAs and InP. The fabricated CNT MOS FETs present a record performance that includes an on-state current of 3.02 mA µm − 1 , a peak transconductance of 2.17 mS µm − 1 at a bias of − 1 V, and a saturation velocity of 3.5 × 10 7 cm s − 1 . Through optimising device structure and fabrication process, in particular the introduction of a Y-gate, a 35 nm-gate length A-CNT MOS FET is fabricated that shows extrinsic current-gain/power-gain and cut-off frequencies of up to 551 GHz/1024 GHz, representing the fastest MOS FET for RF applications. Furthermore, CNT-based mmWave band (30 GHz) RF amplifiers are demonstrated with a high gain of 21.4 dB. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Materials science/Materials for devices/Electronic devices Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Introduction The rapid development of information technologies is continuously increasing the requirements for electronic systems, which is promoting the improvement of semiconductor devices and integrated circuits (ICs). For example, as one of the most anticipated information technologies, sixth-generation (6G) wireless communication will enable more sophisticated applications, such as medical imaging, augmented reality and artificial-intelligence-based communication, and thus greatly raise requirements for electronic systems in terms of security, capacity and bandwidth 1 . This will result in critical challenges for the semiconductor community to supply radiofrequency (RF) devices with up to a terahertz (THz) frequency, digital ICs with more computing power, and system-on-chip (SoC) technology that integrates the above two kinds of devices. In conventional semiconductor technologies, digital ICs consist of silicon-based complementary-metal-oxide-semiconductor (CMOS) transistors, while high-end RF ICs are based on III–V compound semiconductor transistors, including heterojunction bipolar transistors (HBTs) and high-electron-mobility transistors (HEMTs). Although indium phosphide (InP)-based HBTs and HEMTs can work at THz frequencies, their incompatibility with CMOS technology limits the functional integration requirement of SoCs in 6G 2, 3 . On the other hand CMOS FETs are the most fundamental and dominating devices for any sophisticated ICs. The most desired strategy for future SoCs is thus to integrate analogue/RF and digital circuits in a MOS/CMOS process platform. Therefore, RF MOS FETs with cut-off frequencies beyond 1 THz will greatly contribute to the development of SoCs in 6G and other future information technologies. Unfortunately, THz MOS FETs have not yet been realized. The cut-off frequency of Si-based MOS FETs with an ultrascaled gate length reaches approximately 500 GHz but cannot be significantly improved by scaling down because of large parasitics 4 , 5 . High-electron-mobility two-dimensional electron gases (2DEGs) consisting of heterojunctions of III-V compound semiconductors are considered to have great potential for building THz MOS FETs owing to their high mobility and low parasitic of the semi-insulated substrate 6 – 8 . However, all reported MOS HEMTs have not exhibited the high frequency to match the high mobility of the material because the gate efficiency is relatively low in this kind of transistor whose active layer (deep in the material) is far from the gate insulator 6 , 9 and degraded mobility derived from interface scattering with the gate recess process 3 , 8 . In principle, free-standing 2DEGs with high carrier mobility are the most desirable semiconductor systems for building THz MOS FETs with a gate insulator of ultralow equivalent oxide thickness (EOT), which will facilitate great opportunities for low-dimensional semiconductors 10 – 12 . Among low-dimensional semiconducting materials, high-density and well aligned carbon nanotube (A-CNT) array films with ultrahigh semiconducting purity have shown great potential in building high-speed MOS FETs with up to terahertz frequencies mainly due to their high carrier mobility, saturation velocity and stability 13 – 17 . Different from the high-mobility 2DEG formed in the heterojunction of III-V compound semiconductors, the high-mobility carrier layer is free-standing in the A-CNT array film and can be used to construct MOS FETs with high gate efficiency and good compatibility in digital CMOS ICs. The RF properties of a transistor can be characterized by the current-gain cut-off frequency ( f T ), defined as the frequency at which the current gain becomes unity, and the power-gain cut-off frequency ( f MAX ), defined as the frequency at which the power gain becomes unity. Although RF transistors based on CNTs have been regarded as having great potential, the actual frequency performance had been at a very low level (extrinsic f T /f max <50 GHz) for a long time. Very recently, CNT RF MOS FETs have been significantly improved to exhibit extrinsic f T /f MAX up to almost 300 GHz, which mainly benefits from the breakthrough advancement of the semiconducting purity and density of A-CNT array materials. However, all reported A-CNT MOS FETs are still far from meeting the requirements of 6G, in particular the theoretical up to THz f T /f MAX 13,14 . In this work, we pushed the cut-off frequency of MOS FETs into the THz regime for the first time by synergistically optimizing the gate structure and fabrication process of MOS transistors on A-CNT array films. The fabricated transistors presented a record on-state current, peak transconductance and saturation velocity. By optimising both the device structure and fabrication process, in particular introducing a novel Y-gate structure, a 35 nm-gate length A-CNT FET showed an extrinsic f MAX of up to 1024 GHz, representing the fastest MOS FET for RF applications and showing great potential for constructing SoCs for 6G communications and other future electronics applications. Results And Discussion Top-gated MOS FETs are built on high-density (~ 200 CNTs/µm, Extended Data Fig. 1 ) A-CNT array films on high-resistivity (> 20 kΩ·cm) silicon substrates covered with 500 nm thermally grown SiO 2 (Methods). Atomic-layer-deposition (ALD)-grown HfO 2 film with an equivalent oxide thickness (EOT) of 1.44 nm is utilized as the gate dielectric to achieve high performance and excellent lateral scaling-down behaviour of MOS FET. Specifically, to improve the A-CNT/Pd interface at the contacts and the A-CNT/HfO 2 interface at the gate stack, the A-CNT film is pretreated by ultraviolet ozone (UVO) to reduce the organic molecules and residues during the preparation of the CNT array film before depositing the contact and gate insulator (Methods and Extended Data Fig. 2). As a result, the fabricated A-CNT MOS FETs (Fig. 1 a) exhibit typical p-type field-effect characteristics with ultrahigh DC performance, as shown in Fig. 1 b and 1 c. A typical transistor with a gate length ( L g ) of 80 nm exhibits (Fig. 1 b) an on-state current ( I on ) of 3.02 mA/µm and a peak transconductance ( g m ) of 2.17 mS/µm at a V ds of -1 V. The total linear resistance of the transistors at low bias is approximately 300 Ω·µm, as extracted from the data in Fig. 1 c, indicating that high-quality contact with a contact resistance below 150 Ω·µm is achieved here. It is also worth mentioning that the enhancement-mode MOS FETs developed here (with a threshold voltage of -0.45 V) are superior to the natural depletion-mode HEMTs and contribute to lower power dissipation in actual circuit applications 18 . Statistically, ten 80 nm-L g A-CNT MOS FETs are measured (Fig. 1 d) to yield an average I on and g m of 2.87 ± 0.11 mA/µm and 1.94 ± 0.12 mS/µm, respectively, showing that good uniformity is achieved with our developed material preparation method and device fabrication process. The high performance of A-CNT MOS FETs mainly stems from the improvement in the hole mobility of A-CNTs, even when they undergo transistor fabrication. The A-CNTs with a high density of over 200 CNTs/µm in our MOS FETs exhibit a carrier mobility of 2,000 cm 2 V − 1 s − 1 (Methods), which sets a record for the carrier mobility in high-density A-CNT array films (Fig. 1 e) 19 . The saturation velocity of holes in the A-CNT MOS FETs reaches up to 3.5 × 10 7 cm s − 1 (see the details in Methods), showing significant improvements on previously reported results 19 , 20 and conventional semiconductors 21 (Extended Data Fig. 3 ). We compare the DC performance of our A-CNT MOS FETs with that of reported FETs based on III-V semiconductors 9,23,29−30 , CNTs 17 , 19 , 22 and graphene 31 , as shown in Fig. 1 f, indicating the advantage of the DC performance of our A-CNT MOS FETs compared to that of other RF transistors. Specifically, the on-state current density ( I on ) of the A-CNT MOS FET exceeds that of all RF FETs except the best graphene FET, while the peak transconductance ( g m ) outperforms that of all nanomaterial-based RF FETs and is among the best reported for III-V compound semiconductor FETs. We note that there exists substantial room for further improvement in the g m of A-CNT MOS FETs, especially by improving the gate efficiency via lowering the interface trap density at the gate stack 17 . The high DC performance of CNT MOS FET provides a foundation for pursuing higher RF performance. However, elaborate designs of the gate structure and layout are necessary to reduce all kinds of parasitics and improve the RF performance of FETs 23 . Here, we introduce a Y-gate structure and air-bridge interconnection technique to lower parasitic capacitances and resistances (Fig. 2a) and promote the RF performance of A-CNT MOS FETs. The Y-gate, as an upgrade of the conventional T-gate, causes a significant increase in the cross-sectional area of the gate electrode and thus decrease in the gate resistance and suppress parasitic capacitances between the gate and source/drain. A multifinger gate is used to further decrease the gate parasitic resistance in ultrawide RF FETs. In addition, an air bridge, instead of a polymethyl methacrylate (PMMA) bridge 19 , is introduced to lower the parasitic capacitance at the necessary jumpers in interconnection lines (Extended Data Figs. 4 and 5 ). As a result, a 10-finger gate MOS FET based on the A-CNT array (Fig. 2b) with a total channel width ( W ch ) of 100 µm and a gate length ( L g ) of 35 nm exhibits a p-type transfer characteristics (Fig. 2c and 2d) with a linear resistance of approximately 10 Ω and I on / g m of ~ 175 mA/175 mS. The output resistance of the transistor gated at the peak transconductance point is approximately 20 Ω, which is near the 50 Ω-matching resistance of the RF measurement system. It is worth mentioning that the width-normalized I on and g m in such a wide transistor reach up to 1.75 mA/µm and 1.75 mS/µm respectively, reflecting the high uniformity of the A-CNT array films and device fabrication process. The frequency-dependent current and power gain retrieved from the S-parameters measured by a vector network analyser (Fig. 2e) on a 35 nm-L g A-CNT FET further shows cut-off f T and f MAX of up to 551 GHz and 1024 GHz (the corresponding intrinsic f T,INT and f MAX,INT reach 739 and 1142 GHz, respectively, as shown in Extended Data Fig. 6). On-wafer open and short patterns are used to subtract the effect of parasitic pad capacitances and inductances from the measured S-parameters (see the details in Methods). Here, pad de-embedding f T and f MAX are employed to estimate the RF performance potential of A-CNT transistors since they exclude the parasitic effects from pads and reflect the actual achievable performance in monolithic microwave integrated circuits (MMICs). A f MAX of over 1 THz is not only the record for nanomaterial-based RF transistors and MOS FETs on all semiconductors but also means that the A-CNT MOS FET can be used to build THz-band (300 GHz-30 THz) RF circuits (the working frequency is at least one-third 24 of f MAX ) for future 6G applications. We benchmark our A-CNT RF transistors with previously reported RF transistors using key RF metrics, including f T scaling-down behaviour (Fig. 3 a) and the comprehensive performance of f T and f MAX (Fig. 3 b). With L g ranging from 180 nm to 35 nm, A-CNT RF transistors exhibit a f T inversely proportional to L g (Fig. 3 a), indicating that A-CNT MOS FETs operate in the saturation regime 16 . At L g longer than 50 nm, the f T of A-CNT MOS FETs is higher than that of Si CMOS FETs and is among the best reported for III-V HEMT devices, benefiting from the high carrier mobility of A-CNT and III-V heterojunction materials. As L g is scaled below 50 nm, A-CNT MOS FETs begin to exhibit f T higher than all the values reported for RF FETs with the same gate length, indicating that the A-CNT MOS FET exhibits better scaling behaviour than III-V HEMT devices. Specifically, A-CNT MOS FETs have a scaling potential metric, f T × L g , of up to 19.29 GHz•µm, which exceeds that of InP HEMTs (15.25 GHz•µm), Si CMOS FETs (9.03 GHz•µm) and graphene FETs (6.76 GHz•µm), i.e. in the logarithmic coordinates of f T ~ L g , A-CNT MOS FETs exhibit a slope that is steeper than that of all HEMT transistors, and similar to that of the Si CMOS FETs, the later mainly originates from their high gate efficiency. The high f T × L g value and steep slope of log f T ~log( L g ) allow the A-CNT MOS FET to realize 1 THz of f T at a L g of 21 nm, which is far longer than that of InP HEMTs (13.5 nm) and other RF transistors (Fig. 3 a). As two equally critical metrics for RF transistors, both f T and f MAX are used to benchmark our A-CNT MOS FETs with other RF transistors (Fig. 3 b). Our champion A-CNT MOS FET outperforms all the previously reported MOS FETs based on Si and III-V semiconductors with regard to both f T and f MAX and is even comparable to the best HEMT and HBT transistors. Specifically, there are two very important and noteworthy points. First, the champion device is the first A-CNT MOS FET with a f MAX exceeding 1 THz, which is almost twice that of the other best MOS transistors. Second, the champion A-CNT MOS FET exhibits a value of \(\sqrt{{f}_{\text{T}}\times {f}_{\text{M}\text{A}\text{X}}}\) , which is indicative of the comprehensive RF performance of transistors, of over 0.7 THz, which is higher than that of almost all the reported RF transistors (shown in Fig. 3 b). The few exceptions are the best InP HEMT and HBT devices, 23 which were fabricated with a smaller gate length (25 nm) and more mature design and fabrication technologies. Further improvements in the device structure and process would advance A-CNT MOS FET beyond all HEMT and HBT devices owing to the enormous potential of free-standing and high-carrier-mobility low-dimensional semiconductors for enhancing RF performance. The breakthrough in f MAX is attributed to the concurrent optimization of the intrinsic property (dc) and parasitic effects (RF) of the A-CNT MOS EFT. Therefore, strenuous efforts have been made to optimize the gate structure in well-developed III-V devices to further lower the gate parasitic resistance by improving the gate cross-sectional area while reducing the fringe coupling capacitances between the gate and source/drain. T-gate has been the standard gate configuration for high-end RF FET devices 23 based on III-V semiconductors to boost f MAX over 1 THz. Although T-gate has been introduced into CNT RF FETs, the achieved f MAX is just over 100 GHz 22 , which is mainly due to the introduction of high parasitic resistances from the long access regions ( L a , distance from the gate foot to the S/D, Fig. 4a) without an effective doping method. Here, we utilize the transferred charges from CNT/Pd contacts at the source and drain to dope the access regions and to reduce the parasitic series resistance 17 , 19 . Specifically, L a is controlled to be approximately 30 nm, which is less than the charge transfer length from Pd to CNTs 25 , 26 , to ensure that the access region is in a low-resistance state. However, the scaling-down of L a results in larger overlap area between the gate cap and source/drain and thus larger parasitic capacitances of C gs / C gd . Our Y-gate is an improvement upon the T-gate for the A-CNT MOS EFT (see the details in Fig. 4a-4c) that is made to achieve a better balance between the access resistance and fringe capacitance for achieving higher f MAX . The fabricated Y-gate on our A-CNT MOS FET exhibits a larger (approximately 2 times) gate cross-sectional area (400 nm gate height and 370 nm gate cap) than our T-gate (with 320 nm gate height and 300 nm gate cap, see Extended Data Table 1), and much larger than that of the previously reported T-gate 22 for A-CNTs and even comparable to that of the best T-gate of HEMTs 23 (see the benchmarking in Fig. 4d). Moreover, compared with T-gate, our Y-gate presents a gradual gate foot (Fig. 4a-c), which contributes to the suppression of C gs / C gd (Fig. 4e). Therefore, the development of gate technology in CNT RF transistors has evolved from an ordinary gate 19 , 27 to T-gate 22 and now to Y-gate in this work, which boosts the f MAX of CNT MOS FETs beyond 1 THz. THz MOS FETs are suitable for constructing RF amplifiers with high gain and high operation frequency. Here, we develop 30 GHz CNT RF amplifiers based on our A-CNT MOS FETs using a load-pull test system (Extended Data Fig. 7). Our champion amplifier (marked by ca) based on a 50 nm- L g A-CNT MOS FET has a maximum power gain of 21.4 dB at 30 GHz (Fig. 5 a, left panel). According to the measured power gain vs . frequency relation (Fig. 5 a, right panel), the device can reasonably provide a power gain of 10–15 dB while working at 100–300 GHz, which is supposed to be the 6G operation spectrum 28 . In principle, the A-CNT MOS FET with 1 THz f MAX can be used to build RF amplifiers of up to 341 GHz for the THz regime with a gain of nearly 10 dB (one-third 24 of f MAX ). Therefore, the A-CNT MOS FETs reported herein are qualified as the core devices for communication applications from 5G (over 30 GHz) to 6G 2 8 (over 90 GHz) and THz regimes (over 300 GHz). We benchmark carbon-based RF amplifiers through frequency-dependent power gain, as shown in Fig. 5 b, showing that our device outperforms all of the reported carbon-based (including CNT and graphene) RF amplifiers, reaching the mmWave band for the first time. Furthermore, we directly compare the comprehensive RF performance of CNT amplifiers with those of commercial products, as shown in Fig. 5 c, which indicates that A-CNT-based amplifiers reach the preliminary level of commercial mmWave RF amplifiers, representing the possibility of industrialization in the near future with potential for building terahertz (0.3–3 THz) circuits for 5G and 6G communications. Notably, the excellent performance obtained by CNT RF devices is achieved at a bias as low as 1.2 V, indicating the advantage of a low supply voltage and compatibility with the supply voltage of digital ICs in SoCs. Conclusions In conclusion, we pushed the cut-off frequency of MOS FETs into the THz regime for the first time by synergistically optimizing the gate structure and fabrication process of MOS transistors on aligned CNTs array films with high purity and carrier mobilities of up to 2,000 cm 2 V − 1 s − 1 . The fabricated transistors present a record on-state current of 3.02 mA µm − 1 , a peak transconductance of 2.17 mS µm − 1 and a saturation velocity of 3.5 × 10 7 cm s − 1 . By introducing a carefully desired Y-gate structure, a 35 nm-gate length A-CNT FET shows an extrinsic f MAX of up to 1024 GHz, representing the fastest MOS FET for RF applications and showing great potential for constructing SoCs for 6G communications and other future electronics applications. 30 GHz mmWave CNT amplifiers with a power gain of 21.4 dB have been demonstrated for the first time. Declarations Data availability The data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request. Acknowledgement s This work is supported by the National Key Research & Development Program (Grant No. 2022YFB4401601-2) and Natural Science Foundation of China (61888102, 62171004 and 62225101). Author contributions L.D., Z.Z. and L.-M.P. proposed and supervised the project. J.Z. participated in all aspects of this work from device fabrication to characterization and data processing. L.X. performed mobility and saturation velocity simulations using a virtual source model. H.L. and M.Z. were involved in device fabrication. L.L. characterized the CNT materials. H.S. designed the multifinger structure of RF transistors. X.C., L.R. and Z.P. performed the small-signal model simulations, DC measurements and S-parameter measurements of RF transistors. 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L g =30 nm InAs Channel MOS FETs Exhibiting fmax=410 GHz and f T =357 GHz[J]. IEEE Electron Device Letters, 2018, 39(4): 472-475. (a) Si Power Amplifier (Product No. TGA4533-SM T/R) (Qorvo) (b) GaN Power Amplifier (Product No. TGA2595) (Qorvo) (c) GaAs Power Amplifier (Product No. MAAP-011139-DIE) (MACOM) (d) SiGe RF Amplifier (Product No. ADL5723ACPZN-R7) (ADI)s Chang, C. S., Chao, C. P., Chern, J. G. J. & Sun, J. Y. C. Advanced CMOS technology portfolio for RF IC applications. IEEE Trans. Electron Dev. 52, 1324–1334 (2005) Wei, W. et al. High frequency and noise performance of GFETs. In 2017 Int. Conference on Noise and Fluctuations (IEEE, 2017). Han, S. J., Garcia, A. V., Oida, S., Jenkins, K. A. & Haensch, W. Graphene radio frequency receiver integrated circuit. Nat. Commun. 5, 3086 (2014). Yu, C. et al. Improvement of the frequency characteristics of graphene field-effect transistors on SiC substrate. IEEE Electron Device Lett. 38, 1339–1342 (2017). Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat. Nanotechnol. 8, 180–186 (2013). Brady, G. J. et al. Polyfuorene-sorted, carbon nanotube array field-effect transistors with increased current density and high on/off ratio. ACS Nano 8, 11614–11621 (2014). Yu, C., et al. "Graphene amplifier MMIC on SiC substrate." IEEE Electron Device Letters 37.5 (2016): 684-687. Methods Preparation of high-purity semiconducting CNT solution Commercial arc-discharge CNT powder (2 mg/ml, purchased from Carbon Solution, Inc.) and 2 mg/ml conjugated poly[9-(1-octylonoyl)-9H-carbazole-2,7-diyl] (PCz) were dissolved in 500 mL toluene. Then, the mixed solution was dispersed with a 7 mm probe tip for 0.5 h at 650 W (Sonics VCX-800), followed by 2 h of 50000 g centrifugation (Sorvall LYNX6000-Thermo). A dynamic liquid phase filtration process was applied to the as-prepared PCz-wrapped CNT solution, followed by repeated rinsing off in 1,4-epoxybutane (THF). The filtered PCz-wrapped CNTs were redispersed in 1,1,2-trichloroethane target solvent for 5 min at 650 W (Sonics VCX-800). The above dispersion and centrifugation process were repeated to obtain the desired CNT purity. CNT deposition and alignment on a 4-inch wafer PCz-wrapped CNTs (160 mL) in 1,1,2-trichloroethane were added into a vessel with a geometric size of L/W/H=11 cm:1.5 cm:10 cm. A 4-inch high-resistance silicon wafer was clamped by a dip-coating mechanical apparatus and immersed in the as-prepared CNT solvent. Then, 50 μL C 4 H 8 O 2 (2-butene-1,4-diol) was dropped into the CNT solution to form a binary liquid interface for CNT deposition onto the wafer. Then, the 4-inch silicon wafer was withdrawn at a speed of 10 μm/s. After 3 h, the entire 4-inch wafer was covered with aligned CNT arrays. The aligned CNT films were repeatedly cleaned with toluene, THF and N,N-dimethylformamide (DMF) for at least 20 min for each solvent. The aligned CNT wafer was finally heated at 170 °C for 30 min. Pretreatment of CNTs before transistor fabrication. Annealing process . We removed the air in the tube furnace (Thermo Scientific Linderg/Blue M MoldathERM 1100 °C) using 1000 sccm argon and put the substrate covered by A-CNTs in the tube furnace to be annealed for 1 h. The annealing temperature was set at 500 °C, and the argon and hydrogen flow rates were 40 and 5 sccm, respectively. After the annealing process, we immediately repeatedly rinsed the substrate with A-CNTs in isopropanol (IPA). YOC (yttrium oxide cleaning) process . First, 2.5 nm yttrium was deposited on the A-CNTs followed by a 250 °C thermal oxidation (0.5 h). Then, the yttrium oxide layer was removed by immersion in HCl solution (volume ratio of 1:10) for approximately 10 min (to ensure that no yttrium oxide residues remained in the A-CNTs), followed by repeated rinsing in IPA to obtain pristine CNTs. This YOC process has been shown to be effective in removing excess polymer molecules from CNTs. Fabrication of CNT RF MOS FETs. The fabrication process flow is shown in Extended Data Fig. 9. T-gate and Y-gate structures with air gaps between the source and drain were utilized in CNT-based RF transistors. First, the channel area was defined by using yttrium oxide as the mask, followed by oxygen plasma etching. The mask was made as follows: Stripes were patterned by electron beam lithography, with deposition of yttrium of 5 nm. After lift-off, the chip was placed on a hot plate for thirty minutes at 250 °C, forming yttrium oxide. Then, we used a 20/10 nm thick palladium/gold (Pd/Au) double-layer of metal deposited by electron beam deposition (EBE) as the stacked contact electrode to form ohmic contact with the CNTs. This step was performed after etching the CNT films to make the CNT-contact interfaces cleaner without extra contamination. For the lower-level interconnect wires, Ti/Au stack films of 5/100 nm were deposited. Then, a HfO 2 film with a thickness of 4.8 nm (40 cycles of growth) was grown via atomic layer deposition at 105 °C as an oxide dielectric. T-gate (Y-gate) was patterned via a double layer (tri-layer) resist process, and then a Ti/Au stack film of 5/350 nm was deposited on the channel centre. Finally, the upper-level connection wires, air bridge and test pads were patterned, followed by depositing a Ti/Au stack film of 5/400 nm. Measurement of S-parameters. The AC performance of our devices was analysed in terms of S-parameters, from which the current gain ( H 21 ) and power gain ( G max ) were calculated. f T was defined as the frequency at which H 21 reached unity (0 dB), while f MAX was defined as the frequency at which G max reached 0 dB. A probe station (Cascade Summit 1100), semiconductor analysers (Keithley 4200 and Agilent B1500), ground-signal-ground (GSG) probes, coaxial cables and vector network analysers (Agilent N5247B) were used to measure the performance of the CNT-based RF transistors. First, the GSG probes and coaxial RF cables were calibrated using the off-wafer short-open-load-through (SOLT) standard procedure. The semiconductor analyser was used to provide a DC bias including V gs and V ds for CNT-based RF transistors. The gate and drain were defined as port ‘1’ and port ‘2’, respectively, and then two-port S-parameters ( S 11 , S 12 , S 21 , S 22 ) were measured using the VNA. De-embedding process. Due to the existence of parasitic effect, a de-embedding process was carried out to extract the extrinsic values of f T and extrinsic f MAX . Two structures were used for the de-embedding process of the CNT-based RF transistors. The extrinsic de-embedding structure was used to remove only the parasitic effect from the test pads. (Extended Data Figs. 10 and 11). The de-embedding extrinsic S-parameters were indicative of the performance in real applications and the upper limits of the material properties. The de-embedding process included the following: (a) The S-parameters of an RF transistor, open structure, and short structure were converted into Y-parameters using the equation shown in Table S1; (b) The de-embedding Y-parameters were calculated by $${Y}_{\text{De}-\text{embedding}}={\left(\frac{1}{{Y}_{\text{DUT}}-{Y}_{\text{OPEN}}}-\frac{1}{{Y}_{\text{SHORT}}-{Y}_{\text{OPEN}}}\right)}^{-1}$$ 2 where Y DUT , Y OPEN , and Y SHORT represented the Y-parameters of an RF transistor, open structure, and short structure; then, Y De−embedding to S De−embedding were converted using the equation shown in Table S1; (c) The current gain ( H 21 ) and power gain ( G max ) were calculated with S De−embedding ; then, the extrinsic values of f T and f MAX were extracted. (Extended Data Table 2) Modelling and Simulation of CNT high-frequency transistors. The small-signal equivalent circuit model for the de-embedding parts of the CNT RF transistor is shown in Extended Data Fig. 12. The whole device parameter extraction and simulation of CNT RF transistors included the following: (1) The de-embedding process was used to obtain the pad de-embedding S-parameters of CNT RF transistors. (2) The Y-parameters were converted into Z-parameters to extract R g . (3) The S-parameter simulation module of Advanced Design System (ADS) 2020 (Agilent Technologies) was used to import the pad de-embedding S-parameters and simulate them. (4) The equivalent circuit was designed using ADS. (5) The device parameters were tuned to fit the pad de-embedding experimental S-parameters, and the power gain was calculated and f MAX was extracted according to the simulated S-parameters. In contrast to the current gain- f relation, which drops by a -20 dB/dec slope, the power gain varies with f in a more complicated way. We used the pad de-embedding small-signal equivalent circuit model shown in Extended Data Fig. 12 to simulate the S-parameters and extract the f MAX of our high-frequency FETs. The corresponding simulation parameters are listed in Extended Data Table 3. The result of the champion device is shown in Extended Data Fig. 13. 30 GHz load-pull measurement. A load-pull test system was developed to measure the power gain performance of the CNT amplifier. It consisted of a probe station (MPI TS150-THZ), power amplifier (Maury MPA-26G5-40G-5), load-pull tuner (Maury MT985AL01), SUSS Z probe, coupler (Marki CA-40), isolator (Ditom D3I2004), signal generator (Agilent E8257D) and spectrum analyser (Agilent N9030A). DC bias sources (Agilent B2902A) were used to provide the supply voltage to the CNT amplifier. The output power of the amplifier was measured by a power metre (Agilent E4417A). The Bias-T at the input (output) was Keysight 11612B (Keysight 11612B). The measurement process was performed and controlled by an ATS 5.0 LoadPull controller. T-gate process. The copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) was used as the top layer, and PMMA with a molecular weight of 950k was used as the bottom layer. Although the T-gate structure for ACNT-based RF devices has been reported in published work 20 , 25 , it is far less mature than that of III–V-based devices 26 , mainly due to the large gate resistance caused by the small gate cap. It is worth pointing out that a T-gate with a large gate cap implying a longer access region (distance from gate foot to contact) may not be applicable for ACNT-based RF devices because a longer access region without gate control would increase the device series resistance due to the CNT doping-free mechanism 19 , 20 , 22 , 45 , indicating a lack of on-state doping for the access region in ACNT-based devices, which is totally different from conventional III–V-based devices. Fabrication process of the Y-gate. First, three photoresists with different sensitivities (copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) as the top layer, polymethyl methacrylate (PMMA) with a molecular weight of 50k as the middle layer, and PMMA with a molecular weight of 950k as the bottom layer) were spin-coated on the substrate and then exposed to an electron beam. Due to the different sensitivities of the different photoresists to exposure, a specific Y-shape was formed after development, followed by the deposition of metal by electron beam evaporation through the lift-off process to form the final shape of the Y-gate. Fabrication process of the air bridge. Two photoresists with different sensitivities (copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) as the top layer, PMMA with a 950 k molecular weight as the bottom layer) were spin-coated on the substrate and then exposed to an electron beam. Due to the different sensitivities of the photoresists to exposure, a specific bridge shape was formed after development, followed by the deposition of metal by electron beam evaporation through the lift-off process to form the final air bridge. P 1dB and P DC method. The one decibel gain compression point ( P 1dB ) is defined as the corresponding input power level when the linear power gain of the amplifier decreases by 1 dB. The DC power consumption ( P DC ) was calculated from the measured working condition ( V ds , I ds ) of the amplifier via P DC = V ds I ds . Accordingly, we obtained P DC and P 1dB . The results are shown in Extended Data Fig. 14. Calculation of the mobility of aligned CNTs using the VS model. In the VS model, the drain current can be described by the product of the mobile charge density and the carrier average velocity along the channel. According to the gradual channel approximation, the channel charge density per area is modelled as \(Q={C_{inv}}({V_{GSI}}+{V_{TH}})\) \({C_{g,eff}}={C_{ox}} \cdot {C_q}/({C_{ox}}+{C_q})\) where C g,eff is the effective gate capacitance, C ox is the insulator capacitance of a single CNT FET, and C q is the quantum capacitance of a single CNT in the channel area. Based on the capacitance model \(\begin{gathered} {C_{ox}}=\frac{{2\pi {\kappa _{ox}}{\varepsilon _0}}}{{{{\cosh }^{ - 1}}\left( {\frac{{2(r+{t_{ox}})}}{d}} \right)+{\lambda _0}\ln \left( {\frac{{2(r+{t_{ox}})+2d}}{{3d}}} \right)}} \hfill \\ \hfill \\ \end{gathered}\) \({\lambda _0}=({\kappa _{ox}} - {\kappa _{sub}})/({\kappa _{ox}}+{\kappa _{sub}})\) \(r=d/2\) where ε 0 is the vacuum permittivity, κ ox is the dielectric constant of the gate oxide, t ox is the thickness of the gate oxide and d is the diameter of the CNT. For this aligned CNT FET, a gate dielectric HfO 2 κ ox of 13, a thickness of HfO 2 t ox of 4.8 nm, an average diameter d of 1.5 nm and κ sub of 3.9 for the silicon substrate were used. Quantum capacitance C q can be calculated based on the nonequilibrium Green’s function formalism \({C_q}={c_{qa}}\sqrt {q \cdot {E_g}/({k_B}T)} +{c_{qb}}\) where c qa is 0.087 fF/µm, c qb is 0.16 fF/µm, q is the electron charge, k B is Boltzmann’s constant, bandgap E g is 0.85/ d eV, and T is temperature. The VS model transport equations are composed of two parts. All of the above formulations are only for a single CNT-based device. For CNT array FETs, we cannot simply extend the formula by multiplying the single CNT values by the CNT density due to the screening effect between CNTs. We have to make some corrections for C ox and C q . For the on-current of the CNT array-based FET, the drain current in the linear region is given by \({I_{D,LIN}}={C_{g,eff}}({V_{GS}} - {V_{T,LINN}}){V_{DS}}\frac{{{\mu _{CNT}}}}{{{L_g}}}\) and in the saturation region is \({I_{D,SAT}}={C_{g,eff}}({V_{GS}} - {V_{T,SAT}}){\nu _{sat}}\) where V GS and V DS are the gate and drain voltages versus the source, respectively, µ CNT is the apparent carrier mobility, and ν sat is the saturation velocity. V T, LIN and V T, SAT are the threshold voltages in the linear region and saturation region, respectively. The DIBL effect could impact the threshold voltage by \({V_{T,SAT}}={V_{T,LIN}} - \delta {V_{DS}}\) where δ is DIBL. The intrinsic bias is calculated by \(\begin{gathered} {V_{GS}}={V_{GS,M}} - {R_S}{I_{DS,M}} \hfill \\ {V_{DS}}={V_{DS,M}} - 2{R_S}{I_{DS,M}} \hfill \\ \end{gathered}\) where R S ( R D ) is the S/D contact resistance and V DS, M and I DS, M are the measurement results. Then, we can extract the carrier mobility µ CNT and saturation velocity ν sat by fitting the VS model to the transfer and output characteristics of our aligned CNT FETs. A comparison of the simulation results (lines) with the measured transfer curves (dots) of fabricated CNT FETs is shown in Extended Data Fig. 15. Additional Declarations There is NO Competing Interest. Supplementary Files JSZhouTHzRFMOSFETSI20230129.docx Extended Data for Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays Cite Share Download PDF Status: Published Journal Publication published 02 Oct, 2025 Read the published version in Nature Electronics → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-2526224","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Physical Sciences - Article","associatedPublications":[],"authors":[{"id":172486300,"identity":"020c8228-eae9-4ad2-afd5-a9943c88ddc2","order_by":0,"name":"Zhiyong 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lengths \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e = 140 nm and \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e = 80 nm. The scale bar is 100 nm. \u003cstrong\u003eb\u003c/strong\u003e, Transfer characteristic curve of the champion 80 nm-\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg \u003c/sub\u003etransistor with a \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e of -1.0 V. \u003cstrong\u003ec\u003c/strong\u003e, Output characteristic curve of the same transistor in b. \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e is swept from -3 V to 0 V with a step of 0.5 V. \u003cstrong\u003ed\u003c/strong\u003e, On-state current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e) and peak transconductance (\u003cem\u003eg\u003c/em\u003e\u003csub\u003em\u003c/sub\u003e) statistical bar graph of ten CNT transistors with \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e of 80 nm. \u003cstrong\u003ee,\u003c/strong\u003e Comparison of the mobility of this work and those reported for CNTs\u003csup\u003e19,47,48\u003c/sup\u003e. \u003cstrong\u003ef,\u003c/strong\u003e DC performance benchmarking of InP\u003csup\u003e9,23\u003c/sup\u003e, GaN\u003csup\u003e29\u003c/sup\u003e, GaAs\u003csup\u003e30\u003c/sup\u003e, graphene\u003csup\u003e31\u003c/sup\u003e and other CNT\u003csup\u003e17,19,22\u003c/sup\u003e-based transistors.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/ce18f4240a178c8c58735687.png"},{"id":35063179,"identity":"358e5bbd-f71d-4bd1-a399-5af9a5f3b5d4","added_by":"auto","created_at":"2023-03-30 21:44:15","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":640219,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eStructure, DC and RF performance characteristics of A-CNT MOS FETs. a\u003c/strong\u003e, Schematic and SEM images of a 10-finger CNT RF transistor with Y-gate and air-bridge.\u003cstrong\u003e b\u003c/strong\u003e, Channel region SEM images of a 10-finger CNT RF transistor with an effective channel width of 100 μm. \u003cstrong\u003ec\u003c/strong\u003e, Output and \u003cstrong\u003ed, \u003c/strong\u003etransfer characteristic curves of the A-CNT RF transistor. \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e is set to -1.0 V in \u003cstrong\u003ed\u003c/strong\u003e. \u003cstrong\u003ee\u003c/strong\u003e, Current gain and power gain versus frequency of the 35 nm-\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e champion RF transistor. The slope of the extension lines is −20 dB/dec.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/958d766da84a0380aa0b2ad7.png"},{"id":35063178,"identity":"ece4623c-55c1-48bb-ba8b-c6c4592f6d7d","added_by":"auto","created_at":"2023-03-30 21:44:15","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":39524,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eBenchmarking of the RF performance of our A-CNT MOS FETs to those of other materials transistors. a\u003c/strong\u003e, Current-gain cut-off frequency \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e versus \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e in this work compared to that of RF-CMOS\u003csup\u003e43\u003c/sup\u003e, graphene devices\u003csup\u003e44–46\u003c/sup\u003e, InP HEMT\u003csup\u003e23\u003c/sup\u003e, GaAs pHEMTs\u003csup\u003e33\u003c/sup\u003e and GaN HEMT\u003csup\u003e29\u003c/sup\u003e. The solid lines are employed to guide the trends.\u003cstrong\u003e b\u003c/strong\u003e, Comparison of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e versus \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e in this work to that reported for InP\u003csup\u003e23,34-37\u003c/sup\u003e, GaN\u003csup\u003e38\u003c/sup\u003e, InGaAs\u003csup\u003e40\u003c/sup\u003e, InAs\u003csup\u003e41\u003c/sup\u003e, SiGe\u003csup\u003e39\u003c/sup\u003e and silicon\u003csup\u003e43\u003c/sup\u003e-based devices.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/2c4ec4d7e9df2759b9d40603.png"},{"id":35063704,"identity":"2755def4-94ef-4bf7-bb10-ec2ddc4ed221","added_by":"auto","created_at":"2023-03-30 21:52:15","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":337811,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eCharacteristics of Y-Gate structure in A-CNT MOS FETs.\u003c/strong\u003e \u003cstrong\u003ea\u003c/strong\u003e, Schematic diagram of the cross-section of the device for the evolution from the T-gate structure to the Y-gate structure. \u003cstrong\u003eb\u003c/strong\u003eand \u003cstrong\u003ec\u003c/strong\u003e are SEM images of the T-gate and Y-gate with the same gate length of 35 nm. \u003cstrong\u003ed\u003c/strong\u003e, Comparison of the cross-sectional areas of the different gate structures in this work and previous works. \u003cstrong\u003ee,\u003c/strong\u003e Simulated capacitance results of devices with different gate structures at different channel lengths by CST Studio Suite.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/cb83fec5fb60b5d63ef56991.png"},{"id":35063181,"identity":"d3d6c270-08ea-4c9b-9df5-2004047ef463","added_by":"auto","created_at":"2023-03-30 21:44:15","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":97539,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003ePerformance of RF amplifiers based on A-CNT MOS FETs.\u003c/strong\u003e \u003cstrong\u003ea,\u003c/strong\u003e Left: power gain versus input power data for amplification tests of four devices at a frequency of 30 GHz. Right: power gain of four amplifiers and corresponding pad de-embedding power gain curves. The measurement frequency is 30 GHz. \u003cstrong\u003eb\u003c/strong\u003e, Power gain compared with other amplifiers based on different materials\u003csup\u003e19,27,42,49\u003c/sup\u003e. The red stars represent the best CNT RF transistors shown in a. \u003cstrong\u003ec\u003c/strong\u003e, Comprehensive RF performance including frequency, working voltage, gain, 1 dB compression point (\u003cem\u003eP\u003c/em\u003e\u003csub\u003e1dB\u003c/sub\u003e), and \u003cem\u003eP\u003c/em\u003e\u003csub\u003eDC\u003c/sub\u003e compared to that of RF amplifiers\u003csup\u003e42\u003c/sup\u003e made by Qorvo, MACOM, and ADI\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/f0cf0775c126ef0d0603f90e.png"},{"id":92696189,"identity":"e29c4a87-b8f7-4a1d-b4aa-b0e17ad40c75","added_by":"auto","created_at":"2025-10-03 07:06:31","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2450526,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/89e3bff8-c49d-4e8f-a4fc-fccd0fada8bf.pdf"},{"id":35064302,"identity":"72cfdaa9-bff4-467b-97bf-b73936208625","added_by":"auto","created_at":"2023-03-30 22:00:15","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":2589861,"visible":true,"origin":"","legend":"Extended Data for Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays","description":"","filename":"JSZhouTHzRFMOSFETSI20230129.docx","url":"https://assets-eu.researchsquare.com/files/rs-2526224/v1/da94f6552b8c7ba51e160bfc.docx"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays","fulltext":[{"header":"Introduction","content":"\u003cp\u003eThe rapid development of information technologies is continuously increasing the requirements for electronic systems, which is promoting the improvement of semiconductor devices and integrated circuits (ICs). For example, as one of the most anticipated information technologies, sixth-generation (6G) wireless communication will enable more sophisticated applications, such as medical imaging, augmented reality and artificial-intelligence-based communication, and thus greatly raise requirements for electronic systems in terms of security, capacity and bandwidth\u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e\u003c/sup\u003e. This will result in critical challenges for the semiconductor community to supply radiofrequency (RF) devices with up to a terahertz (THz) frequency, digital ICs with more computing power, and system-on-chip (SoC) technology that integrates the above two kinds of devices. In conventional semiconductor technologies, digital ICs consist of silicon-based complementary-metal-oxide-semiconductor (CMOS) transistors, while high-end RF ICs are based on III\u0026ndash;V compound semiconductor transistors, including heterojunction bipolar transistors (HBTs) and high-electron-mobility transistors (HEMTs). Although indium phosphide (InP)-based HBTs and HEMTs can work at THz frequencies, their incompatibility with CMOS technology limits the functional integration requirement of SoCs in 6G\u003csup\u003e2,\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e. On the other hand CMOS FETs are the most fundamental and dominating devices for any sophisticated ICs. The most desired strategy for future SoCs is thus to integrate analogue/RF and digital circuits in a MOS/CMOS process platform. Therefore, RF MOS FETs with cut-off frequencies beyond 1 THz will greatly contribute to the development of SoCs in 6G and other future information technologies. Unfortunately, THz MOS FETs have not yet been realized. The cut-off frequency of Si-based MOS FETs with an ultrascaled gate length reaches approximately 500 GHz but cannot be significantly improved by scaling down because of large parasitics\u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e,\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e. High-electron-mobility two-dimensional electron gases (2DEGs) consisting of heterojunctions of III-V compound semiconductors are considered to have great potential for building THz MOS FETs owing to their high mobility and low parasitic of the semi-insulated substrate\u003csup\u003e\u003cspan additionalcitationids=\"CR7\" citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e. However, all reported MOS HEMTs have not exhibited the high frequency to match the high mobility of the material because the gate efficiency is relatively low in this kind of transistor whose active layer (deep in the material) is far from the gate insulator\u003csup\u003e\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e,\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e\u003c/sup\u003e and degraded mobility derived from interface scattering with the gate recess process\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e,\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e. In principle, free-standing 2DEGs with high carrier mobility are the most desirable semiconductor systems for building THz MOS FETs with a gate insulator of ultralow equivalent oxide thickness (EOT), which will facilitate great opportunities for low-dimensional semiconductors\u003csup\u003e\u003cspan additionalcitationids=\"CR11\" citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e \u003cp\u003eAmong low-dimensional semiconducting materials, high-density and well aligned carbon nanotube (A-CNT) array films with ultrahigh semiconducting purity have shown great potential in building high-speed MOS FETs with up to terahertz frequencies mainly due to their high carrier mobility, saturation velocity and stability\u003csup\u003e\u003cspan additionalcitationids=\"CR14 CR15 CR16\" citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e\u003c/sup\u003e. Different from the high-mobility 2DEG formed in the heterojunction of III-V compound semiconductors, the high-mobility carrier layer is free-standing in the A-CNT array film and can be used to construct MOS FETs with high gate efficiency and good compatibility in digital CMOS ICs. The RF properties of a transistor can be characterized by the current-gain cut-off frequency (\u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e), defined as the frequency at which the current gain becomes unity, and the power-gain cut-off frequency (\u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e), defined as the frequency at which the power gain becomes unity. Although RF transistors based on CNTs have been regarded as having great potential, the actual frequency performance had been at a very low level (extrinsic f\u003csub\u003eT\u003c/sub\u003e/f\u003csub\u003emax\u003c/sub\u003e\u0026lt;50 GHz) for a long time. Very recently, CNT RF MOS FETs have been significantly improved to exhibit extrinsic \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e\u003cem\u003e/f\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e up to almost 300 GHz, which mainly benefits from the breakthrough advancement of the semiconducting purity and density of A-CNT array materials. However, all reported A-CNT MOS FETs are still far from meeting the requirements of 6G, in particular the theoretical up to THz \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e\u003cem\u003e/f\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e\u003csup\u003e13,14\u003c/sup\u003e.\u003c/p\u003e \u003cp\u003eIn this work, we pushed the cut-off frequency of MOS FETs into the THz regime for the first time by synergistically optimizing the gate structure and fabrication process of MOS transistors on A-CNT array films. The fabricated transistors presented a record on-state current, peak transconductance and saturation velocity. By optimising both the device structure and fabrication process, in particular introducing a novel Y-gate structure, a 35 nm-gate length A-CNT FET showed an extrinsic \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of up to 1024 GHz, representing the fastest MOS FET for RF applications and showing great potential for constructing SoCs for 6G communications and other future electronics applications.\u003c/p\u003e"},{"header":"Results And Discussion","content":"\u003cp\u003eTop-gated MOS FETs are built on high-density (~\u0026thinsp;200 CNTs/\u0026micro;m, Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e) A-CNT array films on high-resistivity (\u0026gt;\u0026thinsp;20 kΩ\u0026middot;cm) silicon substrates covered with 500 nm thermally grown SiO\u003csub\u003e2\u003c/sub\u003e (Methods). Atomic-layer-deposition (ALD)-grown HfO\u003csub\u003e2\u003c/sub\u003e film with an equivalent oxide thickness (EOT) of 1.44 nm is utilized as the gate dielectric to achieve high performance and excellent lateral scaling-down behaviour of MOS FET. Specifically, to improve the A-CNT/Pd interface at the contacts and the A-CNT/HfO\u003csub\u003e2\u003c/sub\u003e interface at the gate stack, the A-CNT film is pretreated by ultraviolet ozone (UVO) to reduce the organic molecules and residues during the preparation of the CNT array film before depositing the contact and gate insulator (Methods and Extended Data Fig.\u0026nbsp;2). As a result, the fabricated A-CNT MOS FETs (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ea) exhibit typical p-type field-effect characteristics with ultrahigh DC performance, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb and \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec. A typical transistor with a gate length (\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e) of 80 nm exhibits (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb) an on-state current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e) of 3.02 mA/\u0026micro;m and a peak transconductance (\u003cem\u003eg\u003c/em\u003e\u003csub\u003em\u003c/sub\u003e) of 2.17 mS/\u0026micro;m at a \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e of -1 V. The total linear resistance of the transistors at low bias is approximately 300 Ω\u0026middot;\u0026micro;m, as extracted from the data in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec, indicating that high-quality contact with a contact resistance below 150 Ω\u0026middot;\u0026micro;m is achieved here. It is also worth mentioning that the enhancement-mode MOS FETs developed here (with a threshold voltage of -0.45 V) are superior to the natural depletion-mode HEMTs and contribute to lower power dissipation in actual circuit applications\u003csup\u003e\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e\u003c/sup\u003e. Statistically, ten 80 nm-L\u003csub\u003eg\u003c/sub\u003e A-CNT MOS FETs are measured (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ed) to yield an average \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eg\u003c/em\u003e\u003csub\u003em\u003c/sub\u003e of 2.87\u0026thinsp;\u0026plusmn;\u0026thinsp;0.11 mA/\u0026micro;m and 1.94\u0026thinsp;\u0026plusmn;\u0026thinsp;0.12 mS/\u0026micro;m, respectively, showing that good uniformity is achieved with our developed material preparation method and device fabrication process. The high performance of A-CNT MOS FETs mainly stems from the improvement in the hole mobility of A-CNTs, even when they undergo transistor fabrication. The A-CNTs with a high density of over 200 CNTs/\u0026micro;m in our MOS FETs exhibit a carrier mobility of 2,000 cm\u003csup\u003e2\u003c/sup\u003eV\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003es\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e (Methods), which sets a record for the carrier mobility in high-density A-CNT array films (Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ee) \u003csup\u003e\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e. The saturation velocity of holes in the A-CNT MOS FETs reaches up to 3.5 \u0026times; 10\u003csup\u003e7\u003c/sup\u003e cm s\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e (see the details in Methods), showing significant improvements on previously reported results\u003csup\u003e\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e,\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e\u003c/sup\u003e and conventional semiconductors\u003csup\u003e\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e\u003c/sup\u003e (Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003e). We compare the DC performance of our A-CNT MOS FETs with that of reported FETs based on III-V semiconductors\u003csup\u003e9,23,29\u0026minus;30\u003c/sup\u003e, CNTs\u003csup\u003e\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e,\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e,\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e and graphene\u003csup\u003e\u003cspan citationid=\"CR31\" class=\"CitationRef\"\u003e31\u003c/span\u003e\u003c/sup\u003e, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ef, indicating the advantage of the DC performance of our A-CNT MOS FETs compared to that of other RF transistors. Specifically, the on-state current density (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e) of the A-CNT MOS FET exceeds that of all RF FETs except the best graphene FET, while the peak transconductance (\u003cem\u003eg\u003c/em\u003e\u003csub\u003em\u003c/sub\u003e) outperforms that of all nanomaterial-based RF FETs and is among the best reported for III-V compound semiconductor FETs. We note that there exists substantial room for further improvement in the g\u003csub\u003em\u003c/sub\u003e of A-CNT MOS FETs, especially by improving the gate efficiency via lowering the interface trap density at the gate stack\u003csup\u003e\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e\u003c/sup\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe high DC performance of CNT MOS FET provides a foundation for pursuing higher RF performance. However, elaborate designs of the gate structure and layout are necessary to reduce all kinds of parasitics and improve the RF performance of FETs\u003csup\u003e\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e. Here, we introduce a Y-gate structure and air-bridge interconnection technique to lower parasitic capacitances and resistances (Fig.\u0026nbsp;2a) and promote the RF performance of A-CNT MOS FETs. The Y-gate, as an upgrade of the conventional T-gate, causes a significant increase in the cross-sectional area of the gate electrode and thus decrease in the gate resistance and suppress parasitic capacitances between the gate and source/drain. A multifinger gate is used to further decrease the gate parasitic resistance in ultrawide RF FETs. In addition, an air bridge, instead of a polymethyl methacrylate (PMMA) bridge\u003csup\u003e\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e, is introduced to lower the parasitic capacitance at the necessary jumpers in interconnection lines (Extended Data Figs.\u0026nbsp;4 and \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e5\u003c/span\u003e). As a result, a 10-finger gate MOS FET based on the A-CNT array (Fig.\u0026nbsp;2b) with a total channel width (\u003cem\u003eW\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e) of 100 \u0026micro;m and a gate length (\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e) of 35 nm exhibits a p-type transfer characteristics (Fig.\u0026nbsp;2c and 2d) with a linear resistance of approximately 10 Ω and \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e/\u003cem\u003eg\u003c/em\u003e\u003csub\u003em\u003c/sub\u003e of ~\u0026thinsp;175 mA/175 mS. The output resistance of the transistor gated at the peak transconductance point is approximately 20 Ω, which is near the 50 Ω-matching resistance of the RF measurement system. It is worth mentioning that the width-normalized I\u003csub\u003eon\u003c/sub\u003e and g\u003csub\u003em\u003c/sub\u003e in such a wide transistor reach up to 1.75 mA/\u0026micro;m and 1.75 mS/\u0026micro;m respectively, reflecting the high uniformity of the A-CNT array films and device fabrication process. The frequency-dependent current and power gain retrieved from the S-parameters measured by a vector network analyser (Fig.\u0026nbsp;2e) on a 35 nm-L\u003csub\u003eg\u003c/sub\u003e A-CNT FET further shows cut-off \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of up to 551 GHz and 1024 GHz (the corresponding intrinsic \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT,INT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX,INT\u003c/sub\u003e reach 739 and 1142 GHz, respectively, as shown in Extended Data Fig.\u0026nbsp;6). On-wafer open and short patterns are used to subtract the effect of parasitic pad capacitances and inductances from the measured S-parameters (see the details in Methods). Here, pad de-embedding \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e are employed to estimate the RF performance potential of A-CNT transistors since they exclude the parasitic effects from pads and reflect the actual achievable performance in monolithic microwave integrated circuits (MMICs). A \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of over 1 THz is not only the record for nanomaterial-based RF transistors and MOS FETs on all semiconductors but also means that the A-CNT MOS FET can be used to build THz-band (300 GHz-30 THz) RF circuits (the working frequency is at least one-third\u003csup\u003e\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e\u003c/sup\u003e of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e) for future 6G applications.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eWe benchmark our A-CNT RF transistors with previously reported RF transistors using key RF metrics, including \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e scaling-down behaviour (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003ea) and the comprehensive performance of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003eb). With \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e ranging from 180 nm to 35 nm, A-CNT RF transistors exhibit a \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e inversely proportional to \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003ea), indicating that A-CNT MOS FETs operate in the saturation regime\u003csup\u003e\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e\u003c/sup\u003e. At \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e longer than 50 nm, the \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e of A-CNT MOS FETs is higher than that of Si CMOS FETs and is among the best reported for III-V HEMT devices, benefiting from the high carrier mobility of A-CNT and III-V heterojunction materials. As \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e is scaled below 50 nm, A-CNT MOS FETs begin to exhibit \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e higher than all the values reported for RF FETs with the same gate length, indicating that the A-CNT MOS FET exhibits better scaling behaviour than III-V HEMT devices. Specifically, A-CNT MOS FETs have a scaling potential metric, \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e\u0026times;\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e, of up to 19.29 GHz\u0026bull;\u0026micro;m, which exceeds that of InP HEMTs (15.25 GHz\u0026bull;\u0026micro;m), Si CMOS FETs (9.03 GHz\u0026bull;\u0026micro;m) and graphene FETs (6.76 GHz\u0026bull;\u0026micro;m), \u003cem\u003ei.e.\u003c/em\u003e in the logarithmic coordinates of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e ~\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e, A-CNT MOS FETs exhibit a slope that is steeper than that of all HEMT transistors, and similar to that of the Si CMOS FETs, the later mainly originates from their high gate efficiency. The high \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e\u0026times;\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e value and steep slope of log \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e ~log(\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e) allow the A-CNT MOS FET to realize 1 THz of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e at a L\u003csub\u003eg\u003c/sub\u003e of 21 nm, which is far longer than that of InP HEMTs (13.5 nm) and other RF transistors (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003ea).\u003c/p\u003e \u003cp\u003eAs two equally critical metrics for RF transistors, both \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e are used to benchmark our A-CNT MOS FETs with other RF transistors (Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003eb). Our champion A-CNT MOS FET outperforms all the previously reported MOS FETs based on Si and III-V semiconductors with regard to both \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e and is even comparable to the best HEMT and HBT transistors. Specifically, there are two very important and noteworthy points. First, the champion device is the first A-CNT MOS FET with a \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e exceeding 1 THz, which is almost twice that of the other best MOS transistors. Second, the champion A-CNT MOS FET exhibits a value of \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\sqrt{{f}_{\\text{T}}\\times {f}_{\\text{M}\\text{A}\\text{X}}}\\)\u003c/span\u003e\u003c/span\u003e, which is indicative of the comprehensive RF performance of transistors, of over 0.7 THz, which is higher than that of almost all the reported RF transistors (shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e3\u003c/span\u003eb). The few exceptions are the best InP HEMT and HBT devices,\u003csup\u003e\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e which were fabricated with a smaller gate length (25 nm) and more mature design and fabrication technologies. Further improvements in the device structure and process would advance A-CNT MOS FET beyond all HEMT and HBT devices owing to the enormous potential of free-standing and high-carrier-mobility low-dimensional semiconductors for enhancing RF performance.\u003c/p\u003e \u003cp\u003eThe breakthrough in \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e is attributed to the concurrent optimization of the intrinsic property (dc) and parasitic effects (RF) of the A-CNT MOS EFT. Therefore, strenuous efforts have been made to optimize the gate structure in well-developed III-V devices to further lower the gate parasitic resistance by improving the gate cross-sectional area while reducing the fringe coupling capacitances between the gate and source/drain. T-gate has been the standard gate configuration for high-end RF FET devices\u003csup\u003e\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e based on III-V semiconductors to boost \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e over 1 THz. Although T-gate has been introduced into CNT RF FETs, the achieved \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e is just over 100 GHz\u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e, which is mainly due to the introduction of high parasitic resistances from the long access regions (\u003cem\u003eL\u003c/em\u003e\u003csub\u003ea\u003c/sub\u003e, distance from the gate foot to the S/D, Fig.\u0026nbsp;4a) without an effective doping method. Here, we utilize the transferred charges from CNT/Pd contacts at the source and drain to dope the access regions and to reduce the parasitic series resistance\u003csup\u003e\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e,\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e. Specifically, \u003cem\u003eL\u003c/em\u003e\u003csub\u003ea\u003c/sub\u003e is controlled to be approximately 30 nm, which is less than the charge transfer length from Pd to CNTs\u003csup\u003e\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e, \u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e, to ensure that the access region is in a low-resistance state. However, the scaling-down of \u003cem\u003eL\u003c/em\u003e\u003csub\u003ea\u003c/sub\u003e results in larger overlap area between the gate cap and source/drain and thus larger parasitic capacitances of \u003cem\u003eC\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e/\u003cem\u003eC\u003c/em\u003e\u003csub\u003egd\u003c/sub\u003e. Our Y-gate is an improvement upon the T-gate for the A-CNT MOS EFT (see the details in Fig.\u0026nbsp;4a-4c) that is made to achieve a better balance between the access resistance and fringe capacitance for achieving higher \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e. The fabricated Y-gate on our A-CNT MOS FET exhibits a larger (approximately 2 times) gate cross-sectional area (400 nm gate height and 370 nm gate cap) than our T-gate (with 320 nm gate height and 300 nm gate cap, see Extended Data Table\u0026nbsp;1), and much larger than that of the previously reported T-gate\u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e for A-CNTs and even comparable to that of the best T-gate of HEMTs\u003csup\u003e\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e (see the benchmarking in Fig.\u0026nbsp;4d). Moreover, compared with T-gate, our Y-gate presents a gradual gate foot (Fig.\u0026nbsp;4a-c), which contributes to the suppression of \u003cem\u003eC\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e/\u003cem\u003eC\u003c/em\u003e\u003csub\u003egd\u003c/sub\u003e (Fig.\u0026nbsp;4e). Therefore, the development of gate technology in CNT RF transistors has evolved from an ordinary gate\u003csup\u003e\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e,\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e\u003c/sup\u003e to T-gate\u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e\u003c/sup\u003e and now to Y-gate in this work, which boosts the \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of CNT MOS FETs beyond 1 THz.\u003c/p\u003e \u003cp\u003eTHz MOS FETs are suitable for constructing RF amplifiers with high gain and high operation frequency. Here, we develop 30 GHz CNT RF amplifiers based on our A-CNT MOS FETs using a load-pull test system (Extended Data Fig.\u0026nbsp;7). Our champion amplifier (marked by ca) based on a 50 nm-\u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e A-CNT MOS FET has a maximum power gain of 21.4 dB at 30 GHz (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e5\u003c/span\u003ea, left panel). According to the measured power gain \u003cem\u003evs\u003c/em\u003e. frequency relation (Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e5\u003c/span\u003ea, right panel), the device can reasonably provide a power gain of 10\u0026ndash;15 dB while working at 100\u0026ndash;300 GHz, which is supposed to be the 6G operation spectrum\u003csup\u003e\u003cspan citationid=\"CR28\" class=\"CitationRef\"\u003e28\u003c/span\u003e\u003c/sup\u003e. In principle, the A-CNT MOS FET with 1 THz f\u003csub\u003eMAX\u003c/sub\u003e can be used to build RF amplifiers of up to 341 GHz for the THz regime with a gain of nearly 10 dB (one-third\u003csup\u003e\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e\u003c/sup\u003e of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e). Therefore, the A-CNT MOS FETs reported herein are qualified as the core devices for communication applications from 5G (over 30 GHz) to 6G\u003csup\u003e2\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e (over 90 GHz) and THz regimes (over 300 GHz). We benchmark carbon-based RF amplifiers through frequency-dependent power gain, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e5\u003c/span\u003eb, showing that our device outperforms all of the reported carbon-based (including CNT and graphene) RF amplifiers, reaching the mmWave band for the first time. Furthermore, we directly compare the comprehensive RF performance of CNT amplifiers with those of commercial products, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e5\u003c/span\u003ec, which indicates that A-CNT-based amplifiers reach the preliminary level of commercial mmWave RF amplifiers, representing the possibility of industrialization in the near future with potential for building terahertz (0.3\u0026ndash;3 THz) circuits for 5G and 6G communications. Notably, the excellent performance obtained by CNT RF devices is achieved at a bias as low as 1.2 V, indicating the advantage of a low supply voltage and compatibility with the supply voltage of digital ICs in SoCs.\u003c/p\u003e"},{"header":"Conclusions","content":"\u003cp\u003eIn conclusion, we pushed the cut-off frequency of MOS FETs into the THz regime for the first time by synergistically optimizing the gate structure and fabrication process of MOS transistors on aligned CNTs array films with high purity and carrier mobilities of up to 2,000 cm\u003csup\u003e2\u003c/sup\u003eV\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003es\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e. The fabricated transistors present a record on-state current of 3.02 mA \u0026micro;m\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e, a peak transconductance of 2.17 mS \u0026micro;m\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e and a saturation velocity of 3.5 \u0026times; 10\u003csup\u003e7\u003c/sup\u003e cm s\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e. By introducing a carefully desired Y-gate structure, a 35 nm-gate length A-CNT FET shows an extrinsic \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of up to 1024 GHz, representing the fastest MOS FET for RF applications and showing great potential for constructing SoCs for 6G communications and other future electronics applications. 30 GHz mmWave CNT amplifiers with a power gain of 21.4 dB have been demonstrated for the first time.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eData availability\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe data that support the plots within this paper and other findings of this study are available from the corresponding authors upon reasonable request.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAcknowledgement\u003c/strong\u003e\u003cstrong\u003es\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThis work is supported by the National Key Research \u0026amp; Development Program (Grant No. 2022YFB4401601-2) and Natural Science Foundation of China (61888102, 62171004 and 62225101).\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eAuthor contributions\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eL.D., Z.Z. and L.-M.P. proposed and supervised the project. J.Z. participated in all aspects of this work from device fabrication to characterization and data processing. L.X. performed mobility and saturation velocity simulations using a virtual source model. H.L. and M.Z. were involved in device fabrication. L.L. characterized the CNT materials. H.S. designed the multifinger structure of RF transistors. X.C., L.R. and Z.P. performed the small-signal model simulations, DC measurements and S-parameter measurements of RF transistors. J.Z., L.D., Z.Z. and L.-M.P. analysed the data and cowrote the manuscript. All authors discussed the results and commented on the manuscript.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCompeting interests\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors declare no competing financial interest.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eExtended Data\u0026nbsp;\u003c/strong\u003eThe online version contains extended data available at https://doi.org/\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCorrespondence and requests for materials\u003c/strong\u003e should be addressed to L.D., Z.Z. or L.-M.P.\u003c/p\u003e"},{"header":"References","content":"\u003col class=\"decimal_type\"\u003e\n \u003cli\u003eDang, S., Amin, O., Shihada, B. \u0026amp; Alouini, M.-S. What should 6G be? Nat. Electron. 3, 20\u0026ndash;29 (2020).\u003c/li\u003e\n \u003cli\u003eSaleh, R. et al. System-on-chip: reuse and integration. Proc. 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IEEE, 2018: 39.4. 1-39.4. 4.\u003c/li\u003e\n \u003cli\u003eWu J, Fang Y, Markman B, et al. \u003cem\u003eL\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e=30 nm InAs Channel MOS FETs Exhibiting fmax=410 GHz and f\u003csub\u003eT\u003c/sub\u003e=357 GHz[J]. IEEE Electron Device Letters, 2018, 39(4): 472-475.\u003c/li\u003e\n \u003cli\u003e(a) Si Power Amplifier (Product No. TGA4533-SM T/R) (Qorvo) (b) GaN Power Amplifier (Product No. TGA2595) (Qorvo) (c) GaAs Power Amplifier (Product No. MAAP-011139-DIE) (MACOM) (d) SiGe RF Amplifier (Product No. ADL5723ACPZN-R7) (ADI)s\u003c/li\u003e\n \u003cli\u003eChang, C. S., Chao, C. P., Chern, J. G. J. \u0026amp; Sun, J. Y. C. Advanced CMOS technology portfolio for RF IC applications. IEEE Trans. Electron Dev. 52, 1324\u0026ndash;1334 (2005)\u003c/li\u003e\n \u003cli\u003eWei, W. et\u0026nbsp;al. High frequency and noise performance of GFETs. In 2017 Int. Conference on Noise and Fluctuations (IEEE, 2017).\u003c/li\u003e\n \u003cli\u003eHan, S. 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ACS Nano 8, 11614\u0026ndash;11621 (2014).\u003c/li\u003e\n \u003cli\u003eYu, C., et al. \u0026quot;Graphene amplifier MMIC on SiC substrate.\u0026quot; IEEE Electron Device Letters 37.5 (2016): 684-687.\u003c/li\u003e\n\u003c/ol\u003e"},{"header":"Methods","content":"\u003cp\u003e\u003cstrong\u003ePreparation of high-purity semiconducting CNT solution\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eCommercial arc-discharge CNT powder (2 mg/ml, purchased from Carbon Solution, Inc.) and 2 mg/ml conjugated poly[9-(1-octylonoyl)-9H-carbazole-2,7-diyl] (PCz) were dissolved in 500 mL toluene. Then, the mixed solution was dispersed with a 7 mm probe tip for 0.5 h at 650 W (Sonics VCX-800), followed by 2 h of 50000 g centrifugation (Sorvall LYNX6000-Thermo). A dynamic liquid phase filtration process was applied to the as-prepared PCz-wrapped CNT solution, followed by repeated rinsing off in 1,4-epoxybutane (THF). The filtered PCz-wrapped CNTs were redispersed in 1,1,2-trichloroethane target solvent for 5 min at 650 W (Sonics VCX-800). The above dispersion and centrifugation process were repeated to obtain the desired CNT purity.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCNT deposition and alignment on a 4-inch wafer\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003ePCz-wrapped CNTs (160 mL) in 1,1,2-trichloroethane were added into a vessel with a geometric size of L/W/H=11 cm:1.5 cm:10 cm. A 4-inch high-resistance silicon wafer was clamped by a dip-coating mechanical apparatus and immersed in the as-prepared CNT solvent. Then, 50 \u0026mu;L C\u003csub\u003e4\u003c/sub\u003eH\u003csub\u003e8\u003c/sub\u003eO\u003csub\u003e2\u003c/sub\u003e (2-butene-1,4-diol) was dropped into the CNT solution to form a binary liquid interface for CNT deposition onto the wafer. Then, the 4-inch silicon wafer was withdrawn at a speed of 10 \u0026mu;m/s. After 3 h, the entire 4-inch wafer was covered with aligned CNT arrays. The aligned CNT films were repeatedly cleaned with toluene, THF and N,N-dimethylformamide (DMF) for at least 20 min for each solvent. The aligned CNT wafer was finally heated at 170 \u0026deg;C for 30 min.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ePretreatment of CNTs before transistor fabrication.\u003c/strong\u003e\u003cbr\u003e\u003cem\u003eAnnealing process\u003c/em\u003e. We removed the air in the tube furnace (Thermo Scientific Linderg/Blue M MoldathERM 1100 \u0026deg;C) using 1000 sccm argon and put the substrate covered by A-CNTs in the tube furnace to be annealed for 1 h. The annealing temperature was set at 500 \u0026deg;C, and the argon and hydrogen flow rates were 40 and 5 sccm, respectively. After the annealing process, we immediately repeatedly rinsed the substrate with A-CNTs in isopropanol (IPA).\u003c/p\u003e\n\u003cp\u003e\u003cem\u003eYOC (yttrium oxide cleaning) process\u003c/em\u003e. First, 2.5 nm yttrium was deposited on the A-CNTs followed by a 250 \u0026deg;C thermal oxidation (0.5 h). Then, the yttrium oxide layer was removed by immersion in HCl solution (volume ratio of 1:10) for approximately 10 min (to ensure that no yttrium oxide residues remained in the A-CNTs), followed by repeated rinsing in IPA to obtain pristine CNTs. This YOC process has been shown to be effective in removing excess polymer molecules from CNTs.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFabrication of CNT RF MOS FETs.\u0026nbsp;\u003c/strong\u003eThe fabrication process flow is shown in\u0026nbsp;Extended Data Fig. 9.\u0026nbsp;T-gate and Y-gate structures with air gaps between the source and drain were utilized in CNT-based RF transistors. First, the channel area was defined by using yttrium oxide as the mask, followed by oxygen plasma etching. The mask was made as follows: Stripes were patterned by electron beam lithography, with deposition of yttrium of 5 nm. After lift-off, the chip was placed on a hot plate for thirty minutes at 250 \u0026deg;C, forming yttrium oxide. Then, we used a 20/10 nm thick palladium/gold (Pd/Au) double-layer of metal deposited by electron beam deposition (EBE) as the stacked contact electrode to form ohmic contact with the CNTs. This step was performed after etching the CNT films to make the CNT-contact interfaces\u0026nbsp;cleaner without extra contamination. For the lower-level interconnect wires, Ti/Au stack films of 5/100 nm were deposited. Then, a HfO\u003csub\u003e2\u003c/sub\u003e film with a thickness of 4.8 nm (40 cycles of growth) was grown via atomic layer deposition at 105 \u0026deg;C as an oxide dielectric. T-gate (Y-gate) was patterned via a double layer (tri-layer) resist process, and then a Ti/Au stack film of 5/350 nm was deposited on the channel centre. Finally, the upper-level connection wires, air bridge and test pads were patterned, followed by depositing a Ti/Au stack film of 5/400 nm.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eMeasurement of S-parameters.\u0026nbsp;\u003c/strong\u003eThe AC performance of our devices was analysed in terms of S-parameters, from which the current gain (\u003cem\u003eH\u003c/em\u003e\u003csub\u003e21\u003c/sub\u003e) and power gain (\u003cem\u003eG\u003c/em\u003e\u003csub\u003emax\u003c/sub\u003e) were calculated. \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e was defined as the frequency at which \u003cem\u003eH\u003c/em\u003e\u003csub\u003e21\u003c/sub\u003e reached unity (0 dB), while \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e was defined as the frequency at which \u003cem\u003eG\u003c/em\u003e\u003csub\u003emax\u003c/sub\u003e reached 0 dB. A probe station (Cascade Summit 1100), semiconductor analysers (Keithley 4200 and Agilent B1500), ground-signal-ground (GSG) probes, coaxial cables and vector network analysers (Agilent N5247B) were used to measure the performance of the CNT-based RF transistors. First, the GSG probes and coaxial RF cables were calibrated using the off-wafer short-open-load-through (SOLT) standard procedure. The semiconductor analyser was used to provide a DC bias including \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e for CNT-based RF transistors. The gate and drain were defined as port \u0026lsquo;1\u0026rsquo; and port \u0026lsquo;2\u0026rsquo;, respectively, and then two-port S-parameters (\u003cem\u003eS\u003c/em\u003e\u003csub\u003e11\u003c/sub\u003e, \u003cem\u003eS\u003c/em\u003e\u003csub\u003e12\u003c/sub\u003e, \u003cem\u003eS\u003c/em\u003e\u003csub\u003e21\u003c/sub\u003e, \u003cem\u003eS\u003c/em\u003e\u003csub\u003e22\u003c/sub\u003e) were measured using the VNA.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eDe-embedding process.\u0026nbsp;\u003c/strong\u003eDue to the existence of parasitic effect, a de-embedding process was carried out to extract the extrinsic values of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and extrinsic \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e. Two structures were used for the de-embedding process of the CNT-based RF transistors. The extrinsic de-embedding structure was used to remove only the parasitic effect from the test pads. (Extended Data Figs. 10 and 11). The de-embedding extrinsic S-parameters were indicative of the performance in real applications and the upper limits of the material properties. The de-embedding process included the following: (a) The S-parameters of an RF transistor, open structure, and short structure were converted into Y-parameters using the equation shown in Table S1; (b) The de-embedding Y-parameters were calculated by\u003c/p\u003e\n\u003cdiv class=\"Equation\" id=\"Equ1\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e$${Y}_{\\text{De}-\\text{embedding}}={\\left(\\frac{1}{{Y}_{\\text{DUT}}-{Y}_{\\text{OPEN}}}-\\frac{1}{{Y}_{\\text{SHORT}}-{Y}_{\\text{OPEN}}}\\right)}^{-1}$$\u003c/div\u003e\n \u003cdiv class=\"EquationNumber\"\u003e2\u003c/div\u003e\n\u003c/div\u003e\n\u003cp\u003ewhere \u003cem\u003eY\u003c/em\u003e\u003csub\u003eDUT\u003c/sub\u003e, \u003cem\u003eY\u003c/em\u003e\u003csub\u003eOPEN\u003c/sub\u003e, and \u003cem\u003eY\u003c/em\u003e\u003csub\u003eSHORT\u003c/sub\u003e represented the Y-parameters of an RF transistor, open structure, and short structure; then, \u003cem\u003eY\u003c/em\u003e\u003csub\u003eDe\u0026minus;embedding\u003c/sub\u003e to \u003cem\u003eS\u003c/em\u003e\u003csub\u003eDe\u0026minus;embedding\u003c/sub\u003e were converted using the equation shown in Table S1; (c) The current gain (\u003cem\u003eH\u003c/em\u003e\u003csub\u003e21\u003c/sub\u003e) and power gain (\u003cem\u003eG\u003c/em\u003e\u003csub\u003emax\u003c/sub\u003e) were calculated with \u003cem\u003eS\u003c/em\u003e\u003csub\u003eDe\u0026minus;embedding\u003c/sub\u003e; then, the extrinsic values of \u003cem\u003ef\u003c/em\u003e\u003csub\u003eT\u003c/sub\u003e and \u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e were extracted. (Extended Data Table 2)\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eModelling and Simulation of CNT high-frequency transistors.\u003c/strong\u003e The small-signal equivalent circuit model for the de-embedding parts of\u0026nbsp;the CNT RF transistor is shown in\u0026nbsp;Extended Data Fig.\u0026nbsp;12. The whole device\u0026nbsp;parameter\u0026nbsp;extraction and simulation of CNT RF transistors\u0026nbsp;included the following: (1) The de-embedding process was used to\u0026nbsp;obtain\u0026nbsp;the pad de-embedding S-parameters of CNT RF transistors. (2) The Y-parameters were converted into Z-parameters to extract \u003cem\u003eR\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e.\u0026nbsp;(3) The S-parameter\u0026nbsp;simulation\u0026nbsp;module\u0026nbsp;of Advanced Design System (ADS) 2020 (Agilent Technologies) was used to import the pad de-embedding S-parameters and simulate them. (4) The equivalent circuit was designed using ADS. (5) The device parameters were tuned to fit the pad de-embedding experimental S-parameters, and the\u0026nbsp;power gain was calculated and\u0026nbsp;\u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e was extracted according to the simulated S-parameters.\u003c/p\u003e\n\u003cp\u003eIn contrast to the current gain-\u003cem\u003ef\u003c/em\u003e relation, which drops by a -20 dB/dec slope, the power gain varies with \u003cem\u003ef\u003c/em\u003e in a more complicated way. We used the pad de-embedding small-signal equivalent circuit model shown in\u0026nbsp;Extended Data Fig.\u0026nbsp;12\u0026nbsp;to simulate the S-parameters and extract the\u0026nbsp;\u003cem\u003ef\u003c/em\u003e\u003csub\u003eMAX\u003c/sub\u003e of our high-frequency FETs. The corresponding simulation parameters are listed in Extended Data Table 3. The result of the champion device is shown in Extended Data Fig. 13.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e30 GHz load-pull\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003emeasurement.\u0026nbsp;\u003c/strong\u003eA load-pull test system was developed to measure the power gain performance of the CNT amplifier. It consisted of a probe station (MPI TS150-THZ), power amplifier (Maury MPA-26G5-40G-5), load-pull tuner (Maury MT985AL01), SUSS Z probe, coupler (Marki CA-40), isolator (Ditom D3I2004), signal generator (Agilent E8257D) and spectrum analyser (Agilent N9030A). DC bias sources (Agilent B2902A) were used to provide the supply voltage to the CNT amplifier. The output power of the amplifier was measured by a power metre (Agilent E4417A). The Bias-T at the input (output) was Keysight 11612B (Keysight 11612B). The measurement process was performed and controlled by an ATS 5.0 LoadPull controller.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eT-gate process.\u003c/strong\u003e The copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) was used as the top layer, and PMMA with a molecular weight of 950k was used as the bottom layer. Although the T-gate structure for ACNT-based RF devices has been reported in published work\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e\u003c/sup\u003e, it is far less mature than that of III\u0026ndash;V-based devices\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e, mainly due to the large gate resistance caused by the small gate cap. It is worth pointing out that a T-gate with a large gate cap implying a longer access region (distance from gate foot to contact) may not be applicable for ACNT-based RF devices because a longer access region without gate control would increase the device series resistance due to the CNT doping-free mechanism\u003csup\u003e\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e,\u003cspan class=\"CitationRef\"\u003e45\u003c/span\u003e\u003c/sup\u003e, indicating a lack of on-state doping for the access region in ACNT-based devices, which is totally different from conventional III\u0026ndash;V-based devices.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFabrication process of the Y-gate.\u0026nbsp;\u003c/strong\u003eFirst, three photoresists with different sensitivities (copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) as the top layer, polymethyl methacrylate (PMMA) with a molecular weight of 50k as the middle layer, and PMMA with a molecular weight of 950k as the bottom layer) were spin-coated on the substrate and then exposed to an electron beam. Due to the different sensitivities of the different photoresists to exposure, a specific Y-shape was formed after development, followed by the deposition of metal by electron beam evaporation through the lift-off process to form the final shape of the Y-gate.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFabrication process of the air bridge.\u0026nbsp;\u003c/strong\u003eTwo photoresists with different sensitivities (copolymer of methyl methacrylate and methacrylic acid P(MMA-MAA) as the top layer, PMMA with a 950 k molecular weight as the bottom layer) were spin-coated on the substrate and then exposed to an electron beam. Due to the different sensitivities of the photoresists to exposure, a specific bridge shape was formed after development, followed by the deposition of metal by electron beam evaporation through the lift-off process to form the final air bridge.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e\u003cem\u003eP\u003c/em\u003e\u003c/strong\u003e\u003cstrong\u003e\u003csub\u003e1dB\u003c/sub\u003e\u003c/strong\u003e\u003cstrong\u003e\u0026nbsp;and \u003cem\u003eP\u003c/em\u003e\u003csub\u003eDC\u003c/sub\u003e method.\u0026nbsp;\u003c/strong\u003eThe one decibel gain compression point (\u003cem\u003eP\u003c/em\u003e\u003csub\u003e1dB\u003c/sub\u003e) is defined as the corresponding input power level when the linear power gain of the amplifier decreases by 1 dB. The DC power consumption (\u003cem\u003eP\u003c/em\u003e\u003csub\u003eDC\u003c/sub\u003e) was calculated from the measured working condition (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e,\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e) of the amplifier via P\u003csub\u003eDC\u003c/sub\u003e = \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e. Accordingly, we obtained \u003cem\u003eP\u003c/em\u003e\u003csub\u003eDC\u003c/sub\u003e and \u003cem\u003eP\u003c/em\u003e\u003csub\u003e1dB\u003c/sub\u003e. The results are shown in Extended Data Fig. 14.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCalculation of the mobility of aligned CNTs using the \u003cem\u003eVS\u0026nbsp;\u003c/em\u003emodel.\u0026nbsp;\u003c/strong\u003eIn the VS model, the drain current can be described by the product of the mobile charge density and the carrier average velocity along the channel. According to the gradual channel approximation, the channel charge density per area is modelled as\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\(Q={C_{inv}}({V_{GSI}}+{V_{TH}})\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({C_{g,eff}}={C_{ox}} \\cdot {C_q}/({C_{ox}}+{C_q})\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eg,eff\u003c/em\u003e\u003c/sub\u003e is the effective gate capacitance, \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e is the insulator capacitance of a single CNT FET, and \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eq\u003c/em\u003e\u003c/sub\u003e is the quantum capacitance of a single CNT in the channel area. Based on the capacitance model\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003c/span\u003e \u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003c/span\u003e \u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\(\\begin{gathered} {C_{ox}}=\\frac{{2\\pi {\\kappa _{ox}}{\\varepsilon _0}}}{{{{\\cosh }^{ - 1}}\\left( {\\frac{{2(r+{t_{ox}})}}{d}} \\right)+{\\lambda _0}\\ln \\left( {\\frac{{2(r+{t_{ox}})+2d}}{{3d}}} \\right)}} \\hfill \\\\ \\hfill \\\\ \\end{gathered}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({\\lambda _0}=({\\kappa _{ox}} - {\\kappa _{sub}})/({\\kappa _{ox}}+{\\kappa _{sub}})\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e \u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\(r=d/2\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003e\u0026epsilon;\u003c/em\u003e\u003csub\u003e\u003cem\u003e0\u003c/em\u003e\u003c/sub\u003e is the vacuum permittivity, \u003cem\u003e\u0026kappa;\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e is the dielectric constant of the gate oxide, \u003cem\u003et\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e is the thickness of the gate oxide and d is the diameter of the CNT. For this aligned CNT FET, a gate dielectric HfO\u003csub\u003e2\u003c/sub\u003e \u003cem\u003e\u0026kappa;\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e of 13, a thickness of HfO\u003csub\u003e2\u003c/sub\u003e \u003cem\u003et\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e of 4.8 nm, an average diameter \u003cem\u003ed\u003c/em\u003e of 1.5 nm and \u003cem\u003e\u0026kappa;\u003c/em\u003e\u003csub\u003e\u003cem\u003esub\u003c/em\u003e\u003c/sub\u003e of 3.9 for the silicon substrate were used. Quantum capacitance \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eq\u003c/em\u003e\u003c/sub\u003e can be calculated based on the nonequilibrium Green\u0026rsquo;s function formalism\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({C_q}={c_{qa}}\\sqrt {q \\cdot {E_g}/({k_B}T)} +{c_{qb}}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003ec\u003c/em\u003e\u003csub\u003e\u003cem\u003eqa\u003c/em\u003e\u003c/sub\u003e is 0.087 fF/\u0026micro;m, \u003cem\u003ec\u003c/em\u003e\u003csub\u003e\u003cem\u003eqb\u003c/em\u003e\u003c/sub\u003e is 0.16 fF/\u0026micro;m, \u003cem\u003eq\u003c/em\u003e is the electron charge, \u003cem\u003ek\u003c/em\u003e\u003csub\u003e\u003cem\u003eB\u003c/em\u003e\u003c/sub\u003e is Boltzmann\u0026rsquo;s constant, bandgap \u003cem\u003eE\u003c/em\u003e\u003csub\u003e\u003cem\u003eg\u003c/em\u003e\u003c/sub\u003e is 0.85/\u003cem\u003ed\u003c/em\u003e eV, and \u003cem\u003eT\u003c/em\u003e is temperature.\u003c/p\u003e\n\u003cp\u003eThe \u003cem\u003eVS\u003c/em\u003e model transport equations are composed of two parts. All of the above formulations are only for a single CNT-based device. For CNT array FETs, we cannot simply extend the formula by multiplying the single CNT values by the CNT density due to the screening effect between CNTs. We have to make some corrections for \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eox\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eC\u003c/em\u003e\u003csub\u003e\u003cem\u003eq\u003c/em\u003e\u003c/sub\u003e. For the on-current of the CNT array-based FET, the drain current in the linear region is given by\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({I_{D,LIN}}={C_{g,eff}}({V_{GS}} - {V_{T,LINN}}){V_{DS}}\\frac{{{\\mu _{CNT}}}}{{{L_g}}}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003eand in the saturation region is\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({I_{D,SAT}}={C_{g,eff}}({V_{GS}} - {V_{T,SAT}}){\\nu _{sat}}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eGS\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS\u003c/em\u003e\u003c/sub\u003e are the gate and drain voltages versus the source, respectively, \u003cem\u003e\u0026micro;\u003c/em\u003e\u003csub\u003e\u003cem\u003eCNT\u003c/em\u003e\u003c/sub\u003e is the apparent carrier mobility, and \u003cem\u003e\u0026nu;\u003c/em\u003e\u003csub\u003e\u003cem\u003esat\u003c/em\u003e\u003c/sub\u003e is the saturation velocity. \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eT, LIN\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eT, SAT\u003c/em\u003e\u003c/sub\u003e are the threshold voltages in the linear region and saturation region, respectively. The DIBL effect could impact the threshold voltage by\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\({V_{T,SAT}}={V_{T,LIN}} - \\delta {V_{DS}}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003e\u0026delta;\u003c/em\u003e is DIBL. The intrinsic bias is calculated by\u003c/p\u003e\n\u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\(\\begin{gathered} {V_{GS}}={V_{GS,M}} - {R_S}{I_{DS,M}} \\hfill \\\\ {V_{DS}}={V_{DS,M}} - 2{R_S}{I_{DS,M}} \\hfill \\\\ \\end{gathered}\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003ewhere \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eS\u003c/em\u003e\u003c/sub\u003e (\u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eD\u003c/em\u003e\u003c/sub\u003e) is the S/D contact resistance and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS, M\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eDS, M\u003c/em\u003e\u003c/sub\u003e are the measurement results. Then, we can extract the carrier mobility \u003cem\u003e\u0026micro;\u003c/em\u003e\u003csub\u003e\u003cem\u003eCNT\u003c/em\u003e\u003c/sub\u003e and saturation velocity \u003cem\u003e\u0026nu;\u003c/em\u003e\u003csub\u003e\u003cem\u003esat\u003c/em\u003e\u003c/sub\u003e by fitting the \u003cem\u003eVS model\u003c/em\u003e to the transfer and output characteristics of our aligned CNT FETs.\u003c/p\u003e\n\u003cp\u003eA comparison of the simulation results (lines) with the measured transfer curves (dots) of fabricated CNT FETs is shown in Extended Data Fig. 15.\u003c/p\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nature-portfolio","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"","title":"Nature Portfolio","twitterHandle":"","acdcEnabled":false,"dfaEnabled":false,"editorialSystem":"ejp","reportingPortfolio":"","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-2526224/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-2526224/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe development of wireless communications is driving the need for compact radiofrequency (RF) devices with up to terahertz (THz) frequency and fabrication processes compatible with that of complementary-metal-oxide-semiconductor (CMOS) transistors. Aligned carbon nanotube (A-CNT) film is a promising candidate semiconductor that can be used to build both CMOS field-effect transistors (FETs) for digital integrated circuits (ICs) and radiofrequency (RF) transistors with frequencies beyond 1 THz for analogue ICs. Herein, we demonstrate the first MOS FET with a cut-off frequency beyond 1 THz on a high-quality A-CNT array film, and with a carrier mobility of 2,000 cm\u003csup\u003e\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e V\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e s\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e and better scaling characteristics than all semiconductors, including GaAs and InP. The fabricated CNT MOS FETs present a record performance that includes an on-state current of 3.02 mA \u0026micro;m\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e, a peak transconductance of 2.17 mS \u0026micro;m\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e at a bias of \u0026minus;\u0026thinsp;1 V, and a saturation velocity of 3.5 \u0026times; 10\u003csup\u003e7\u003c/sup\u003e cm s\u003csup\u003e\u0026minus;\u0026thinsp;1\u003c/sup\u003e. Through optimising device structure and fabrication process, in particular the introduction of a Y-gate, a 35 nm-gate length A-CNT MOS FET is fabricated that shows extrinsic current-gain/power-gain and cut-off frequencies of up to 551 GHz/1024 GHz, representing the fastest MOS FET for RF applications. Furthermore, CNT-based mmWave band (30 GHz) RF amplifiers are demonstrated with a high gain of 21.4 dB.\u003c/p\u003e","manuscriptTitle":"Terahertz metal-oxide-semiconductor transistors based on aligned carbon nanotube arrays","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2023-03-30 21:44:10","doi":"10.21203/rs.3.rs-2526224/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nature-electronics","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"natelectron","sideBox":"Learn more about [Nature Electronics](http://www.nature.com/natelectron/)","snPcode":"","submissionUrl":"","title":"Nature Electronics","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature Research","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"6369313e-1a37-42c6-b363-63d07ffe4c50","owner":[],"postedDate":"March 30th, 2023","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":18870108,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":18870109,"name":"Physical sciences/Materials science/Materials for devices/Electronic devices"},{"id":18870110,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices"}],"tags":[],"updatedAt":"2025-10-03T07:06:25+00:00","versionOfRecord":{"articleIdentity":"rs-2526224","link":"https://doi.org/10.1038/s41928-025-01463-6","journal":{"identity":"nature-electronics","isVorOnly":false,"title":"Nature Electronics"},"publishedOn":"2025-10-02 04:00:00","publishedOnDateReadable":"October 2nd, 2025"},"versionCreatedAt":"2023-03-30 21:44:10","video":"","vorDoi":"10.1038/s41928-025-01463-6","vorDoiUrl":"https://doi.org/10.1038/s41928-025-01463-6","workflowStages":[]},"version":"v1","identity":"rs-2526224","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-2526224","identity":"rs-2526224","version":["v1"]},"buildId":"WrCJVZZCHTDjtuVLN7oU0","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}