A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS

A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS G. Prathiba, N. Vasu Nithyanandam This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7704931/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract ADCs transform analog sensor readings into digital data that Microcontrollers and Processors may use in control algorithms for the majority of applications, such as Robotics, Industrial Instrumentation, Automation and Internet of Things (IOT) devices. Several methods were suggested to convert the analog signal to a discrete signal the analog signal's inaccuracy prevented a successful conversion. High resolution Flash ADC is constructed using MOSFET devices in reliable VLSI circuits to reduce power dissipation. A Novel 1.5 GS/s Clock Gating (CG) Flash ADC was proposed in this study and it involves a low switching power Clock Gating NOR-LTE comparator used to avoid the occurrence of race condition by minimizing the clock skew and jitter, an Adaptive Priority Encoder and Inverted AND Gate Bubble Error Controller. Execution of the suggested CG Flash ADC takes place on a 0.18µm Tanner EDA tool with 0.8V power supply. The observed minimum and maximum power consumption is 10.63mW and 15.45mW at -20°C and + 60°C respectively that is equal to 30% variations compared to the conventional method. The measured values of SNDR and SFDR of the proposed 5-bit 1.5GS/s CG-FADC are 29.45 dB and 32.63 dB, with a resulting ENOB of 4.59 bits. Low switching power CMOS Clock Gating - NOR-LTE comparator Inverted AND Gate Bubble Error Controller Adaptive priority encoder Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 1. Introduction 1.1 Analog to Digital Converters (ADCs) Analog-to-Digital Converters (ADCs) are essential in the field of IOT devices and applications, because they allow systems to handle analog data from the real world. Continuous analog signals, including audio inputs or sensor readings, are converted by ADCs into discrete/digital formats that are comprehensible and analyzed for many applications, including data acquisition systems, control systems, image and video analysis, audio and speech processing. There are many fascinating new innovations in the CMOS VLSI domain, not everyone is a good fit. Only those with an interest in electronics can get interested in VLSI design, testing, and verification, which can be done in real time with high quality. Small microchips with a variety of functions, such as multiplexers, encoders, and flip flops, are made using CMOS VLSI design. With lower costs and low power dissipation line regulation factors, VLSI design minimizes the area of the circuit for both analog and digital circuits. A Very Large-Scale Integration (VLSI) chip has become widely employed in the modern world in a variety of industries. The ICs are regenerated and employed in the VLSI domain due to numerous social necessities, including process geometric requirements and product development. The majority of signals in nature are analog, which must be converted into digital signals. In order to convert analog signals to digital signals, ADC is preferred [ 1 ] [ 2 ]. Compared to other ADCs like Successive Approximation ADC, Sigma-Delta ADC, Dual Slope converters, Sub ranges and Two-Step ADC, Interpolating and Folding ADC, etc., Flash ADC is mostly used for high speed requirements [ 3 ]. Flash ADC was chosen because of it’s simple architecture, parallel functionality, and non-linearity. It uses a comparator and a thermometer to binary encoder as its main digital conversion components [ 4 ]. The need for comparators directly relates to the resolution. Due to the increased number of comparators, this approach's main drawback is that it uses more power and area [ 5 ]. Reduced comparators count results in decreased resolution quality. The trade-off between area and resolution quality is thus present. It takes a parallel connection of 2 N -1 comparators to create an N-bit FADC with high-resolution quality,it uses comparators to relate an analog voltage signal (V in ) with a reference voltage (V ref ). To get the entire output voltage swing, the gain boosters are fed discrete signals from the comparator [ 6 ]. Flash ADC designs these days needs architecture having high speed operation and less power consumption [ 7 ]. Various architectures of ADC have been proposed by researchers now days with different resolutions, sampling rates, power consumptions and temperature ranges. These ADCs are used in different applications for mobile communication devices to measure equipment [ 8 ]. Since the performance parameters like sampling rate, resolution, and power consumption of an ADC is basically determined by its architecture, one single ADC type cannot cover all applications.As a result, selecting the appropriate ADC for each unique application is crucial. One of the commonly used ADC is flash type ADC because of the better trade off between its performance metrics [ 9 ]. A stochastic flash ADC [ 10 ] have used the random comparator offset to set the trip points and the comparators are no longer sized for small offset, they can be shrunk down into digital cells. The used comparators are implemented as digital cells produce a large variation of comparator offset. A digitally controlled bulk voltage trimming offset calibration technique for compensating preamplifier and comparator offsets in flash ADCs [ 11 ]. It calibrates offset by adjusting bulk voltages of the ADC preamplifier input pair and avoids introducing additional capacitive loading by calibration devices to improve ADC speed. An asynchronous binary-search ADC [ 12 ] with reference range prediction used to reduce the cost of implementation. An original bit-binary-search ADC requires comparators while one only needs ones. A combined AC/DC-coupled output averaging technique for input amplifier design of flash ADC. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging technique used to minimize the offset-induced ADC nonlinearities [ 13 ]. A fully integrated 5-bit flash-type single-flux quantum (SFQ) ADC consists of error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators. 10-bit dual-channel pipelined flash successive approximation register (SAR) based ADC [ 14 ] consists of two channels for high operating speed, and each channel adopts a pipelined flash–SAR architecture for low power and a small area. This flash–SAR ADC in the second stage composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. A periodic comparator used to minimize its phase-dependent nonlinearities and using differential “quasi-one-junction” SQUID (DQOS) quantization for low-inductance clocking scheme [ 15 ]. 1.2 Related works Hafeez et al. [ 16 ] discussed two essential components of the Flash ADC and integrated within this architecture. Switched-capacitor positive feedback (SCPF) comparators used to reduce hardware utilization with replacement for conventional comparators structure. The SCPF comparator tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision.. Zahrai et al. [ 17 ] has presented a hybrid flash-TI ADC with four interleaved CABS ADCs. A flash ADC used to resolve the most significant bits (MSBs), whereas a TI ADC resolves the least significant bits (LSBs). The fast MSB conversion by the flash ADC together with sub-ranging helps to reduce the number of interleaved ADCs, which results in higher input bandwidth (BW). This paper uses a CABS ADC in TI architecture to take advantage of its high-speed low-power performance, which further reduces the number of interleaved slices in given process technology. Prathiba et al. [ 18 ] suggested a Self Calibrated Flash ADC with 3.77-bit ENOB and 0.321pJ/conv. -step Figure of Merit for the supply voltage 1.5V. A Direct Bubble Error Controller (DBEC) block is utilized following a series of low-leakage power comparators called a Sleep Transistor based NAND LTE (ST-NAND-LTE) comparator in order to remove the source of bubble code faults. When compared to the traditional comparator methodology, this method reduces power by 93.12% and delays by 66.35%. For wire line receivers, Wang et al. [ 19 ] have introduced a 4GS/s single channel folding flash ADC with time-interleaved. Depending on the link loss and modulation scheme, the ADC's resolution can be scaled to provide power savings. While the LSBs are determined by a 5-bit full flash where each comparator can be separately enabled and disabled, the MSB is determined by a 1-bit folding stage. The ADC with a VGA at 6-bit resolution uses 34.4mW from a 0.9V supply to obtain an SNDR of 30.7dB and an SFDR of 40.6dB at Nyquist frequency, resulting in a FOM of 303fJ/conv-step. Wu et al. [ 20 ] introduced a different class of ADC architecture that non-uniformly samples the analog input and shifts from conventional voltage quantization to a hybrid quantization paradigm wherein both voltage and time quantization are utilized. In this architecture, the sampling rate adapts to the input frequency, which maintains an alias free spectrum and enables an anti-aliasing (AA) filtering in the digital domain to relax the analog AA filter. Prathiba et al. [ 21 ] suggested a structure includes the Successive Approximation Register (SAR) control logic, the Low Voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier. The Reduced Switching Capacitance DAC array reduces the switching energy by 93% and the pre-amplifier in the comparator structure is frequently used to reduce DC offset voltage and kickback noise without significantly lowering the Signal-to-Noise Ratio (SNR), whereas the latch is required for comparison. Ahmed et al. [ 22 ] proposed a comparator generates inherent embedded threshold voltage and it using the variable threshold voltage generation method for producing the reference voltage for the flash ADC design.There are several advantages to using an optimized comparator, including the elimination of the need for a front-end track and hold circuit and a reference resistor ladder.This reduces both layout area and power consumption and makes it appropriate for SoC ADC implementation. The modified CMOS inverter based comparator achieves average power consumption of 1.46µW with propagation delay of 53.8ps. Couto-pinto et al. [ 23 ] introduced a flash ADC with the relaxation of detailed comparator requirements, and ensured monotonic characteristic and lead to less area and lower power consumption when compared to a conventional flash ADC. The invented technique leads to an 8-bit OST ADC with an ENOB of 4.5-bit, while a conventional 6-bit topology for the same performance would require comparators employing much larger transistors increasing the ADC die area and power. Fahmy et al. [ 24 ] discussed an all-digital programmable and reconfigurable stochastic ADC. This ADC directly benefits from scaling by using only digital gates and relying on increased mismatch between minimum sized transistors. The programmability and reconfigurability are achieved by dividing the design into 8 channels. Each channel mean is independently set using a 10-bit control word and an analog reference voltage that is digitally created. The output of each channel literalized using Gaussian linear interpolation. Yoshioka et al. [ 25 ] proposed a binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. A prototype sub-ranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. Prathiba et al. [ 26 ] proposed a 4-bit low-power and high-speed Clocked Flash ADC (C-FADC) that involves a low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE). By reducing the propagation delay, the clock network in the comparator reduces skew and jitter. The Binary Encoder converts the bubble-free code into binary code after the ABF logic circuit has identified and corrected fourth order bubble error in the thermometer code. Caldwell et al. [ 27 ] have demonstrated a reconfigurable continuous-time low-pass modulator for direct-conversion receivers. The speed and linearity of the flash ADC and DAC improved, and the flash calibration, reference shuffling, and a dynamic element matching scheme that reduces distortion in the DAC. Third-order multi-stage multi-path feed forward amplifiers with low flicker noise and high-bandwidth helped improve the power-efficiency of the modulator. To create an N-bit clock gating FADC, a parallel connection of 2 N -1 comparators with high-resolution quality is required to link an analog voltage signal (V in ) with a reference voltage (V ref ). To obtain the full output voltage swing, the gain boosters are fed discrete signals from the comparator. The thermometer code is the output of gain booster circuits. If the value one is shown above zero in a thermometer code, a bubble error is presented. By using Inverted AND Gate Bubble Error Controller (IAG-BEC), these bubble errors are reduced. The Clock Gating NOR-LTE comparator (CG-NOR-LTE), IAG-BEC (Inverted AND Gate Bubble Error Controller) and Adaptive Priority Encoder (APE) are used in the proposed Clock Gating Flash ADC (CG-FADC) to minimize the area and power consumption while maintaining high resolution quality. In this manuscript, a 5-bit 1.5GS/s CG-Flash-ADC is simulated in 0.18 µm Complementary MOS technology at a supply voltage of 0.8V. Power consumption is then recorded at different temperatures by varying the width of the channel and supply voltage. Results show that the power consumption reduced to significant level as the supply voltage decreases. Temperature variation is also recorded, and it shows for lower supply voltage the variation in power consumption is less as compared to higher supply voltage. Furthermore, the simulated work is then compared with the latest existing flash-ADC designs. This paper is organised as follows: The CG-FADC and its functionalities are introduced and explains how the study was founded in Section 1. In section 2, a brand-new CG-FADC is suggested. Sections 3 present simulation results and discussion. Segment 4 illustrates the ending section. 2. Clock Gating- Flash ADC CG-Flash ADC is suggested as a solution to the drawbacks of earlier research, and it is made for real time applications. To achieve high speed and accuracy, the suggested approach uses an Adaptive Priority Encoder (APE) and a low switching power CG-NOR-LTE comparator. The proposed CG-Flash-ADC design consists three key functionalities are CG-NOR-LTE comparator, Inverted AND Gate Bubble Error Controller (IAG-BEC), and an Adaptive Priority Encoder. Figure 1 shows the blocks in Clock Gating Flash ADC. The analog electrical signal is transformed into thermometer code (TE 01 to TE 31 ) via the CG-NOR-LTE comparator. While converting the analog signals to the thermometer code several bubble errors may occur and this can be corrected by IAG-BEC corrector. The APE (Adaptive Priority Encoder) transforms the corrected thermometer code (B 0 to B 31 ) into S 0 to S 4 binary outputs. There are three factors can create the bubble errors in the conventional comparator techniques. The first factor is device mismatch and comparator offset Voltage. In the thermometer code, bubbles occur when a "1" appears before a "0" due to variations in the offset voltages caused by different comparators structure. Making the devices larger physically is a basic strategy to enhance matching. The influence of random changes is lessened by larger devices, which often show better matching qualities. Include a two-stage strategy with two operating stages as well to lessen the offset brought on by mismatch. The suggested comparator design is superior at minimizing offset from device mismatch. This involves minimizing offset brought on by employing a two-stage (Clock and Clockbar) strategy with two operational phases. The second factor is clock skew and third factor is clock jitter. All high performance processor architectures today need clock generation and distribution circuitry. Bubble errors may be produced by comparator outputs that are delayed or impacted by changes in the clock signal's timing causes skew and jitter. The clock distribution network on a tiny chip consists of only a wire and perhaps an inverter. Clock skew is the result of changes in the RC delay of the wire resistance and gate load on real chips, which causes the clock to reach various elements at different times. Buffers are used by most chips to equalize the delay. Minimizes skew without completely eliminating it. Clock skew is a spatial variation in temporally comparable clock edges. Positive and negative clock skews are the two types of clock skews that are examined and evaluated and it is shown in Figure. 2(a) and (b). The clock and data flow travel in the same direction when there is a positive clock skew, and in the opposite way when there is a negative clock skew. If δ (delay) is greater than 0 in the positive clock skew, the comparator circuit performs better, but it is challenging to reach the hold time (T h ). When the hold time is not reached, the race condition occurs. If δ (delay) is less than zero in the negative clock skew, the comparator circuit performance is deteriorated; however, it is simple to reach the hold time (T h ), and race circumstances are avoided. Temporal variations in consecutive clock signal edges are caused by clock jitter. Jitter and skew both have an impact on the effective cycle time and it is displayed in Figure. 2(c) and (d). Assuming jitter tracks in the same direction, only skew has an impact on the race margin. The suggested CG-NOR-LTE comparator, the clock and clockbar technique distribute the clock signal to all the elements at same time and the buffer circuit add in the output of CG-NOR-LTE comparator. 2.1 Proposed CG-NOR-LTE Comparator The comparator is a critical component of the flash ADC for analog-to-digital conversion. The number of comparators used varies according to the resolution of the flash ADC. For an N-bit resolution flash ADC, the comparator count increases by 2 N -1. If the resolution of the ADC grows, so does the use of comparator count in the ADC is increased then the area and switching power also increased. In order to overcome the area and switching power problem in the flash ADC, the suggested comparator examines the area, processing delay and switching power factor. A typical flash ADC uses a group of resistors from the ladder circuit to produce a comparator reference voltage, which can be overcome by the low switching CG-NOR-LTE comparator technique. The conventional comparator technique consumes more switching power because the reference potential generated by the group of resistors in the circuit. A compact and low switching power CG-NOR-LTE comparator is proposed in this study. The suggested low switching power CG-NOR-LTE comparator compares the analog input voltage to an internally created reference voltage before producing a binary output. It is composed of a single CMOS-NOR-LTE comparator and two sets of NMOS and PMOS transistors that are controlled by the clock and clockbar signals. The internally generated reference voltage, which is produced by varying the transistor widths with constant V g1 and V g2 values, is compared to the input voltage by the CG-NOR-LTE comparator. The proposed CG-NOR-LTE Comparator schematic illustration is shown in Fig. 3 . It uses two sets of CMOS transistors P5, N5 and P6, N6 wired in parallel, as well as one CMOS NOR-LTE logic inverter with P2, P3, P4 and N2, N3. N4 transistors act as comparator. Each pair pulls the NOR-LTE logic inverter circuits up and down. The PMOS (P5, P6) and NMOS (N5, N6) transistors are guided by the two operational phases are clock and clockbar pulse. When the clock input is high, the transistors P5 and N5 to activate the NOR-LTE inverter logic produce an output is low. Similarly, the low clock input the transistors P6 and N6 to activate the NOR-LTE inverter logic generate an output is high. The length (L) and width (W) of PMOS and NMOS are adjusted to produce the required switching voltage. The transistors P7 and N7 are act as a buffer circuit, which is connected at the output of NOR-LTE comparator used to minimize the processing delay. The switching voltage of the comparator is depending on the threshold voltages of PMOS and NMOS transistors, which is used in the inverter circuit. The threshold voltage should not be altered too much in order to lower the design power usage. On the other hand, channel noise can impact the output and produce a nonlinear switching pattern even if the transistor length is kept extremely short to get a high speed. Consequently, the transistor width is utilized to produce various switching voltages, while the transistor length (L) is fixed at a nominal value. The signal rise or fall time at the gate terminal's output decreases as the transistor width (W) grows since it increases the transistor current drive capability. As transistor size rises, active devices active area and layout area may also increased. The transistor specifications and their values for the suggested CG-NOR-LTE comparator are displayed in Table 1 .To determine whether the output of the comparator is high or low, V in is compared to V ref . The NOR-LTE Comparator that is controlled by clock signals is combined to create a CG-NOR-LTE comparator. 2 N -1comparators can be used to run the N bit flash ADC. 31 comparators can be used to create a 5-bit flash ADC. The threshold voltage, which may be used as a reference value, is varied by changing the transistor sizes. Table 1 Transistor parameters of CG-NORT-LTE comparator S.NO Transistor Parameter Value (µm) 1 PMOS Width (W p ) Max 5.6 2 PMOS Width (W p ) Min 0.2 3 NMOS Width (W n ) Max 4 4 NMOS Width (W n ) Min 1.12 5 L p =L n 0.18 2.2. Inverted AND Gate (ING) Bubble Error Controller As the sampling rate and input frequency rises, the dynamic noise from clock skew (delay) and aperture jitter significantly worsens. Device mismatch is a major source of error due to process variance, in addition to dynamic disturbances. Input offset voltages are the name given to these error sources, which have the potential to seriously impair encoder performance. A logical "1" may show up above a logical "0" in the thermometer code at the output of parallel comparators when the input-referred offset voltage is greater than 0.5 LSB. It refers to this as a "bubble." The ADC's operating speed is decreased with the potential to include more bubble errors in the thermometer code. The bubble error correction circuit could be incorporated into the suggested CG-FADC to increase speed and accuracy. Figure. 4 display the Inverted AND Gate Bubble Error Controller (IAG-BEC). An Inverted AND Gate Bubble Error Controller (IAG-BEC) is designed using one 2 input inverted AND gate, one 3 input inverted AND gate, one 4 inputs inverted AND gate and twenty seven counts of 5 inputs inverted AND gate. The input bubble error code is corrected by using IAG-BEC circuit by generating One-Hot Code. Based on the priority an Adaptive Priority Encoder generates the binary code from the input One-Hot Code. 2.3 Adaptive Priority Encoder (APE) Adaptive Priority Encoder is a circuit shown in Fig. 5 , which compresses multiple binary inputs into a minor number of outputs. The APE output is the binary depiction of the unique number starting from zero of the most important input bits. They often help to regulate interrupt requests by acting on the highest priority encoder. It is designed using two Priority Encoder (PE-1 and PE-2), each can accept 16 inputs and provides 4 outputs in binary representation. The Priority Encoder (PE-1 and PE-2) are constructed using 4 inputs OR gates and then the output of PE-1 and PE-2 given as input of 2 input OR gate to get Binary code S 0 to S 4 from thermometer code which reduces the transistor count by 18.47% compared to the conventional structure. Based on highest priority, the enable signal of the APE selects the inputs and transfers it to the corresponding output binary code. An Adaptive Priority Encoder is preferred to achieve high speed over the existing encoders such as Fat tree encoder, MUX based encoder and Priority encoder. The Truth Table of encoder is exposed in Table 2 . TE 31 to TE 1 indicate the inputs, B 31 to B 1 are one hot code and S 5 to S 0 indicate the outputs of Priority Encoder where the 31-bit thermometer codes are converted into 5-bit binary code. The 5-bit binary code output is from 00000's to 11111's. In order to attain high speed over the current encoders, the priority encoder is recommended. The Priority Encoder is an alternative type of combinational circuit compared to the binary encoder, excluding that it produces an output code depending on the highest prioritized input. The output binary code S 4 to S 0 is obtained by Eq. (1) to (5). $$\:{\varvec{S}}_{4}={\varvec{B}}_{16}+{\varvec{B}}_{17}+{\varvec{B}}_{18}+{\varvec{B}}_{19}+{\varvec{B}}_{20}+{\varvec{B}}_{21}+{\varvec{B}}_{22}+{\varvec{B}}_{23}+{\varvec{B}}_{24}+{\varvec{B}}_{25}+{\varvec{B}}_{26}+{\varvec{B}}_{27}+{\varvec{B}}_{28}+{\varvec{B}}_{29}+{\varvec{B}}_{30}+{\varvec{B}}_{31}\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\left(1\right)$$ $$\:{\varvec{S}}_{3}={\varvec{B}}_{8}+{\varvec{B}}_{9}+{\varvec{B}}_{10}+{\varvec{B}}_{11}+{\varvec{B}}_{12}+{\varvec{B}}_{13}+{\varvec{B}}_{14}+{\varvec{B}}_{15}+{\varvec{B}}_{24}+{\varvec{B}}_{25}+{\varvec{B}}_{26}+{\varvec{B}}_{27}+{\varvec{B}}_{28}+{\varvec{B}}_{29}+{\varvec{B}}_{30}+{\varvec{B}}_{31}\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\left(2\right)$$ $$\:{\varvec{S}}_{2}={\varvec{B}}_{4}+{\varvec{B}}_{5}+{\varvec{B}}_{6}+{\varvec{B}}_{7}+{\varvec{B}}_{12}+{\varvec{B}}_{13}+{\varvec{B}}_{14}+{\varvec{B}}_{15}+{\varvec{B}}_{20}+{\varvec{B}}_{21}+{\varvec{B}}_{22}+{\varvec{B}}_{23}+{\varvec{B}}_{28}+{\varvec{B}}_{29}+{\varvec{B}}_{30}+{\varvec{B}}_{31}\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\left(3\right)$$ $$\:{\varvec{S}}_{1}={\varvec{B}}_{2}+{\varvec{B}}_{3}+{\varvec{B}}_{6}+{\varvec{B}}_{7}+{\varvec{B}}_{10}+{\varvec{B}}_{11}+{\varvec{B}}_{14}+{\varvec{B}}_{15}+{\varvec{B}}_{18}+{\varvec{B}}_{19}+{\varvec{B}}_{22}+{\varvec{B}}_{23}+{\varvec{B}}_{26}+{\varvec{B}}_{27}+{\varvec{B}}_{30}+{\varvec{B}}_{31}\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\left(4\right)$$ Table 2. Truth Table of encoder Thermometer code (TE 31 to TE 1 ) One hot code(B 31 to B 1 ) Priority Encoder output (S 4 to S 0 ) 1111111111111111110111111111111 0111110111111111111111111111111 0010111111111111111111111111111 . . . 0000000000000000000000000000011 0000000000000000000000000000001 0000000000000000000000000000000 10000000000000000000000000000000 0100000000000000000000000000000 0010000000000000000000000000000 . . . 00000000000000000000000000000100 00000000000000000000000000000010 0000000000000000000000000000001 11111 11110 11101 . . . 00010 00001 00000 3. RESULTS AND DISCUSSION The 5-bit 1.5GS/s CG-FADC schematic design was implemented in 0.18 µm CMOS Technology using S-Edit (Tanner EDA Tool) and simulated using T-Spice. 3.1 Simulation Result of CG-NOR-LTE Comparator Table 3 shows the power consumption and processing delay for various comparators. The proposed CG-NOR-LTE comparator consumes the reduced power compared to CMOS-LTE comparator; CMOS-NOR-LTE comparator and CMOS-NAND-LTE comparator are 95.66%, 93.58% and 91.78% and the processing delay reduced by 89.65%, 86.95% and 83.33% respectively. The power consumption and processing delay analysis for various comparators is displayed in Figure. 6. The output response of the suggested CG-NOR-LTE comparator is displayed in Figure.7. Table 3 Power consumption and Processing delay for various Comparator Techniques S.No Comparator Technique Power consumption(mW) Processing Delay(µs) 1 CMOS-LTE comparator 5.53 2.9 2 CMOS-NOR-LTE comparator 3.74 2.3 3 CMOS-NAND-LTE comparator 2.92 1.8 4 CG-NOR-LTE comparator 0.24 0.3 3.2 Simulation Result of Adaptive Priority Encoder (APE) Table 4 shows the power dissipation and transistor count for different encoding schemes. The suggested Adaptive Priority Encoder (APE) dissipates the power minimized by 74.47%, 62.35% and 58.24% compared to Fat Tree Encoder, MUX based Encoder and Priority Encoder. Figure 8 shows the Analysis of power dissipation and Transistor count for different Encoding schemes. From this chart it is observed that the Transistor count of the recommended Adaptive Priority Encoder utilizes the Transistor count reduced by 33.62%, 27.88% and 18.47% compared to Fat Tree Encoder, MUX based Encoder and Priority Encoder. Table 4 Power dissipation and Transistor count for different encoding schemes S.No Encoding schemes Power dissipation(µW) Transistor count 1 Fat Tree Encoder 12.3 226 2 MUX based Encoder 8.34 208 3 Priority Encoder 7.52 184 4 Adaptive Priority Encoder 3.14 150 3.3 Simulation Result of CG-FADC This section of the manuscript does power analysis. With a supply voltage of 0.8 volts, 0.18µm CMOS technology based on SPICE simulates Clock Gating flash-ADC. The first step in the investigation is to determine the flash-ADC's power consumption by adjusting the supply voltage and width. The detailed record of power consumption at various temperatures and NMOS and PMOS channel widths are considered for analysis. To observe changes in power consumption, the NMOS channel width is adjusted from 1.12µm to 4µm, the PMOS channel width is adjusted from 4.5µm to 0.13µm and then the temperature is adjusted at each channel width. The temperature fluctuates between − 20°C and 60°C. This 5-Bit CG-Flash-ADC is emulated at a sampling rate of 1.5 GS/s. The power consumption at different temperatures, channel width, and supply voltages is recorded at this sampling rate. The Table 5 shows that the power consumption is lower for NMOS and PMOS channels with a width of 1.12µm and 0.2µm respectively, and that it is as low as 10.63mW at -20°C. This power consumption rises as the temperature rises from − 20° to + 60°. At 60°C, the high power usage of 15.45mW is measured. The highest power consumption is measured at + 60° C for the NMOS and PMOS channel widths 4µm and 5.6µm respectively. This occurs because the resistance of the MOS device changes with width, which raises the power consumption. Figure. 9 shows the various power consumptions measured from 0.2µm to 5.6µm PMOS channel width for different temperature. Table 5 Power consumption with various temperature and different channel width of CG-Flash-ADC NMOS width(µm) PMOS width(µm) Temperature(°C) -20° -10° 0° 10° 20° 30° 40° 50° 60° 1.12 0.2 10.63 11.72 12.80 12.96 13.11 13.45 14.22 14.86 15.45 1.86 0.8 13.26 13.89 14.31 14.22 14.85 15.22 15.76 16.53 17.22 2.00 1.4 14.28 14.99 15.16 16.45 16.73 17.14 17.68 18.22 19.76 2.62 2.0 16.92 17.12 17.83 18.21 18.94 19.45 20.23 20.94 21.13 3.14 2.6 20.35 20.78 21.23 22.35 22.68 23.16 23.79 24.56 25.69 3.5 3.2 22.77 23.62 24.12 25.77 26.23 27.35 28.94 29.37 30.54 3.8 3.8 25.61 27.49 28.54 29.28 28.58 29.27 30.56 31.69 32.83 4 4.4 28.42 31.56 32.11 33.52 34.41 35.35 36.75 37.54 38.25 4 5.0 30.56 32.41 33.67 34.13 34.98 36.97 37.97 38.69 39.88 4 5.6 32.41 33.52 34.75 35.54 36.87 37.12 38.55 40.49 43.61 The variation in the power consumption is observed and recorded in the Table 6 . It is possible to reduce power consumption by lowering the supply voltage, however doing so comes at the sacrifice of speed. The maximum power consumption is observed by 15.45mW for 1.5V supply voltage at -20° C and the minimum power consumption is achieved by 10.63mW for 0.8V supply voltage at + 60° C, which provides 31% power variations. Similarly, for 0.9V to 1.4V supply voltage the pattern follows the same increasing pattern. But at 1.5V supply voltage the increment in the power consumption starts saturating and a variation of only 3.7% is recorded. However, at 1.5V supply voltage the pattern changes and power consumption start decreasing with temperature. At -20°C 112.7mW of power consumption is recorded which will decrease to 108.5mW at + 60°C. Figure 10 shows this decreasing pattern of power consumption graphically and Fig. 11 (a and b) shows that the maximum DNL and INL are − 0.65/+0.45 LSB and − 0.67/+0.47 LSB, respectively. Table 6 Various power consumption with different supply voltages and temperature Supply voltage(Volts) Temperature(°C) -20° -10° 0° 10° 20° 30° 40° 50° 60° 1.5 112.7 112.1 111.8 111.2 110.6 110.3 109.7 109.1 108.5 1.4 93.73 94.25 94.78 94.97 95.24 95.72 95.93 96.21 96.78 1.3 82.35 82.63 83.12 83.68 83.97 84.31 84.65 84.87 85.12 1.2 70.22 70.69 71.44 71.82 72.35 72.54 72.88 73.26 73.59 1.1 53.14 53.42 53.75 54.03 54.18 54.42 54.74 55.18 55.64 1.0 35.83 36.24 36.41 36.98 37.29 37.76 38.26 38.22 38.47 0.9 21.41 21.96 22.42 22.67 22.93 23.16 23.35 23.58 23.91 0.8 10.63 11.72 12.80 12.96 13.11 13.45 14.22 14.86 15.45 3.4 Corner outcomes of CG-FADC Aspects of NMOS and PMOS variable behavior, such as the required Slow Fast (SF) or Fast Slow (FS) regions, can be reflected in corner outcomes. To assess the effectiveness of the NMOS and PMOS, experiments were conducted at the SS, TT, SF, FS, and FF process corners. Simulations were run for various supply voltages (0.8 V to 1.5 V) at temperatures between − 20°C and + 60°C. The SNDR and SFDR with process corner modifications are shown in Fig. 12 (a and b). For both the SNDR and SFDR, the FF corner performs best at all temperatures, peaking between 30 to -10 ◦C. The FS corner varies significantly with temperature and performs the worst at all temperatures. While most corners operate slightly worse at high temperatures, peak performance happens at room temperature 30 to -20 ◦C. The behavior of TT and SF corners is very constant over the temperature range. More temperature variation is seen in corners FF, SS, and FS. 3.5 Performance metrics and results comparison of CG-FADC Table 7 summarizes the performance metrics of the proposed 5-bit 1.5Gs/s CG-FADC architecture. The CG-FADC results for INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are − 0.67 /+0.47 and − 0.45 /+0.65 LSB, respectively obtained with the Maximum Resolution Bandwidth (MRB) of 500MHz. The twelfth harmonic limited the measured SFDR (Spurious Free Dynamic Range) of 32.63 dB Full Scale (FS), and the SNDR obtained from an FFT was 29.45 dB, as shown in Fig. 13 .With a 0.8 V supply, the ADC achieves a 4.59 ENOB (Effective Number of Bits) at 1.5 GS/s while consuming 10.63mW of power. The PDP (Power Delay Product) improves efficiency without significantly compromising execution speed. The trade-off between the circuit's speed performance and efficiency can be clearly evaluated using the PDP. The intentional PDP indicates that the CG-FADC arrives at 132.8 pJ _ ns/conv.-step while considering the conversion speed. Table 7 Performance Metrics of CG –FADC S.No Parameters Observed Values 1 Technology (µm) 0.18 2 Supply voltage (V) 0.8 3 Resolution (bit) 5 4 Processing delay (µS) 12.5 5 Maximum sampling rate (GS/s) 1.5 6 Power consumption (mW) 10.63 7 ENOB (bits) 4.59 8 SNDR (dB) 29.45 9 SFDR (dB) 32.63 10 DNL (LSB) -0.45 /+0.65 11 INL (LSB) -0.67 /+0.47 12 FOM pJ/conv.-step 0.44 13 PDP (pJ _ ns/conv.-step) 132.8 The performance comparison between the recommended CG-ADC and other announced Flash ADCs is displayed in Table 8 . It is demonstrated that a superior trade-off between speed, power, MRB, and FOM in Flash ADC architectures, as well as excellent unique execution, could be achieved by the intended Flash ADC. The demonstrated work has a Maximum Resolution Bandwidth (MRB) of 500 MHz is lower than the authors [ 5 , 6 , 12 , 20 , 25 ] and consumes 10.63mW less power than references [ 5 , 6 , 7 , 19 , 20 , 24 ]. Table 8 Parameters Comparison of the proposed SC -FADC with other Flash ADCs Parameters Speed (GS/s) Process (nm) Resolution (bits) ENOB Supply (v) Power (mW) MRB (MHz) SNDR (dB) SFDR (dB) DNL/INL (± LSB) FOM (pJ/ Conv-step) This work 1.5 180 5 4.59 0.8 10.63 500 29.45 32.63 -0.45/+0.65 -0.67/+0.47 0.44 [ 5 ] 1.2G 90 7 6.05 1.6 204m 750 38.17 46.6 0.70/0.64 - [ 6 ] 1.25G 90 8 6.91 1 207m 600 43.36 57.36 1.3/1.1 1.4 [ 7 ] 4G 180 4 3.48 1.8 530m 100 - - -0.14/+0.15 -0.20/+0.24 - [ 12 ] 0.8G 65 5 4.40 1 1.97m 700 26.92 35.90 0.56/0.62 116 [ 19 ] 4G 16 6 4.8 0.9 34.4m - 30.7 40.6 -0.75 / 0.54 -1.03 / 0.19 303 [ 20 ] - 65 4 3.9 1 30m 600 56 59.9 0.41/0.43 - [ 24 ] 140M 130 8 - 0.7 17.3m 140 34.9 45.4 - - [ 25 ] 1 65 7 5.88 1 8.11m 1228 36.2 46.2 -0.44/+0.54 -1.01/+1.07 125 4. Conclusion The suggested work presents a Clock Gating Flash ADC (CG-FADC) is fabricated in 0.18µm CMOS VLSI Technology. Using an Adaptive Priority Encoder (APE) and low switching power Clock Gating- NOR-LTE comparator, the prospective design achieves a maximum conversion rate 1.5GS/s with the MRB of 500MHz. The power-hungry resistive ladder and complex encoder structure have been removed by employing various techniques. Based on this CG-FADC technique, the Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR) and Signal-to-Noise and Distortion Ratio (SNDR) are obtained at 4.59, 29.45 dB and 32.63 dB respectively. The prototype ADC draws only 10.63mW of energy from the 0.8-V supply at a sampling frequency of 500 GHz with DNL is -0.45/+0.65 LSB and INL is -0.67/+0.47 LSB and has a FOM of 0.44 pJ/Conversion-step. The main contribution of this design is to reduce the power consumption, propagation delay and area, which can also be employed for low-power CMOS VLSI Integrated circuit designs, such as robotics, instrumentation and measurement, industrial automation, and Internet of Things (IOT) devices. Declarations 5. Competing interests The authors state that they have no competing interests. 6. Conflicts of Interest The authors declare no conflicts of interest 7. Consent for publication Not applicable 8. Ethics Approval and consent to participate Not applicable 9 . Funding This research work does not have any external funding 10 . Data Availability Statement Data are contained within the article. 1 1 . Author’s Contribution G. Prathiba, and N. Vasu Nithyanandam have developed an innovative idea, designed a new architecture Clock Gating Flash-ADC (CG-FADC) uses CG-NOR-LTE comparator and Adaptive Priority Encoder (APE). G. Prathiba constructs and develops the graphical response for a CG-NOR-LTE comparator, Inverted AND Gate Bubble Error Controller (IAG-BEC) and an Adaptive Priority Encoder (APE). N. Vasu Nithyanandam is reviewing the schematic, simulation output of CG-FADC and corrects the text with alignment. Authors are studied and approved the completed work. Acknowledgments Not applicable 13. Clinical trial number Not applicable References Chun-Cheng Huang and Jieh-Tsorng Wu, "A background comparator calibration technique for flash analog-to-digital converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 9, pp. 1732-1740, 2005. S. Buchner, T. Meehan, A. Campbell, K. Clark and D. McMorrow, "Characterization of single-event upsets in a flash analog-to-digital converter (AD9058)", IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2358-2364, 2000. P. M. Figueiredo and J. C. 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Chen, "A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter", IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2335-2349, 2017. G. Prathiba and M.Santhi, “A New Structure of 8-Bit 60 MS/s SAR-ADC Using a Reduced Switching Capacitor-DAC Array”,Journal of Circuits, Systems, and Computers, Vol. 31, No. 3, 2250053 (1-26 pages), 2022. G. Ahmed and R. Baghel, "Performance evaluation of a new single-ended comparator for low-power high-speed flash ADC", International Journal of Electronics Letters, vol. 5, no. 2, pp. 199-211, 2016. A. Couto-Pinto, J. Fernandes, M. Piedade and M. Silva, "A Flash ADC Tolerant to High Offset Voltage Comparators", Circuits, Systems, and Signal Processing, vol. 36, no. 3, pp. 1150-1168, 2016. A. Fahmy, J. Liu, T. Kim and N. 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09:04:31","extension":"html","order_by":30,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":133666,"visible":true,"origin":"","legend":"","description":"","filename":"earlyproof.html","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/9e8d635ab138968c562ab667.html"},{"id":93570369,"identity":"d2d2fa17-c81b-4bd1-9335-b57341f99e1f","added_by":"auto","created_at":"2025-10-15 08:56:29","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":50034,"visible":true,"origin":"","legend":"\u003cp\u003eBlocks in Clock Gating Flash ADC\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/1ec8c92f773917c0f3035185.png"},{"id":93571545,"identity":"763e6d55-2189-40e6-b61b-6335559e39fc","added_by":"auto","created_at":"2025-10-15 09:04:29","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":46007,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Positive Clock Skew (b) Negative Clock Skew \u0026nbsp;(c) Clock Jitter (d) Combined effect of clock skew and clock Jitter\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/258695c0e0848c5fcb994e72.png"},{"id":93573677,"identity":"0b0790b6-ea6e-4a85-8463-0c1333c51626","added_by":"auto","created_at":"2025-10-15 09:12:29","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":24551,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic Diagram of CG-NOR-LTE Comparator\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/c8454339b6ef6c69a55924ad.png"},{"id":93570370,"identity":"70985263-e2d5-4568-b308-f6beda43479d","added_by":"auto","created_at":"2025-10-15 08:56:29","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":24929,"visible":true,"origin":"","legend":"\u003cp\u003eInverted AND Gate Bubble Error Controller (IAG-BEC)\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/da442684b402e5f67267f844.png"},{"id":93573678,"identity":"402fdf66-38f4-467c-8adf-55160f4116be","added_by":"auto","created_at":"2025-10-15 09:12:29","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":22846,"visible":true,"origin":"","legend":"\u003cp\u003eAdaptive Priority Encoder (31 : 5)\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/f3d66ad0329820c3fb0a8479.png"},{"id":93570375,"identity":"a70db10e-e450-4dd1-ba8b-5a7a44463015","added_by":"auto","created_at":"2025-10-15 08:56:29","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":14151,"visible":true,"origin":"","legend":"\u003cp\u003eAnalysis of power consumption and processing delay for various comparators\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/611b31b1f5b8425bde62791f.png"},{"id":93570379,"identity":"2d4937b7-b627-4c0b-b979-d7f5b407dec8","added_by":"auto","created_at":"2025-10-15 08:56:29","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":42911,"visible":true,"origin":"","legend":"\u003cp\u003eOutput response of CG-NOR-LTE comparator\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/230171054658e842304bd3c3.png"},{"id":93571549,"identity":"d4dfc966-ced8-4652-aa62-43b94cbef586","added_by":"auto","created_at":"2025-10-15 09:04:29","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":11699,"visible":true,"origin":"","legend":"\u003cp\u003eAnalysis of power dissipation and Transistor count for different Encoding schemes\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/4ac6283a8203918af0d32cca.png"},{"id":93571551,"identity":"e511a4ac-63ed-4aab-8e99-1c50cb3c6c96","added_by":"auto","created_at":"2025-10-15 09:04:29","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":58026,"visible":true,"origin":"","legend":"\u003cp\u003eVarious Power consumptions measured from 0.2µm to 5.6µm \u0026nbsp;PMOS channel width for different temperature\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/c0cf370b60b40dc506cf4e48.png"},{"id":93571552,"identity":"db325d80-8b6c-43a7-bd63-ba9965865788","added_by":"auto","created_at":"2025-10-15 09:04:29","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":33775,"visible":true,"origin":"","legend":"\u003cp\u003eVarious power consumption with different supply voltages and temperature\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/2a001311942867ed761c6e87.png"},{"id":93570388,"identity":"7e321d15-61a0-41fe-9b29-22212c19ceb9","added_by":"auto","created_at":"2025-10-15 08:56:29","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":29591,"visible":true,"origin":"","legend":"\u003cp\u003e(a) INL (b) DNL of CG-FADC\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/1eb8a1e1cc1a124efc7108e8.png"},{"id":93570410,"identity":"02c3726b-bbf7-4c73-b4d4-a4341b824e7c","added_by":"auto","created_at":"2025-10-15 08:56:31","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":50460,"visible":true,"origin":"","legend":"\u003cp\u003e(a) SNDR(dB) and (b) SFDR(dB) of the proposed CG-FADC - Corner outcomes (TT, SS, FF, FS, SF)\u003c/p\u003e\n\u003cp\u003ewith Temperatures (−20 ◦C to 60 ◦C).\u003c/p\u003e","description":"","filename":"12.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/b0ac4744630c392c093b4b1e.png"},{"id":93571559,"identity":"15313d74-b446-4884-81f4-cc8e6519e510","added_by":"auto","created_at":"2025-10-15 09:04:30","extension":"png","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":65277,"visible":true,"origin":"","legend":"\u003cp\u003eFFT Spectrum with Maximum Resolution Bandwidth (MRB) 500MHz\u003c/p\u003e","description":"","filename":"13.png","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/f0f12e85c490284c95a13eac.png"},{"id":95526516,"identity":"fcf8a73b-9404-4aa8-90e9-b6f0dd7e88b6","added_by":"auto","created_at":"2025-11-10 10:07:10","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1568621,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7704931/v1/0607a494-482d-4dd0-8cc6-e2cf035be456.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS","fulltext":[{"header":"1. Introduction","content":"\u003cdiv id=\"Sec2\" class=\"Section2\"\u003e\u003ch2\u003e1.1 Analog to Digital Converters (ADCs)\u003c/h2\u003e\u003cp\u003eAnalog-to-Digital Converters (ADCs) are essential in the field of IOT devices and applications, because they allow systems to handle analog data from the real world. Continuous analog signals, including audio inputs or sensor readings, are converted by ADCs into discrete/digital formats that are comprehensible and analyzed for many applications, including data acquisition systems, control systems, image and video analysis, audio and speech processing. There are many fascinating new innovations in the CMOS VLSI domain, not everyone is a good fit. Only those with an interest in electronics can get interested in VLSI design, testing, and verification, which can be done in real time with high quality. Small microchips with a variety of functions, such as multiplexers, encoders, and flip flops, are made using CMOS VLSI design. With lower costs and low power dissipation line regulation factors, VLSI design minimizes the area of the circuit for both analog and digital circuits. A Very Large-Scale Integration (VLSI) chip has become widely employed in the modern world in a variety of industries. The ICs are regenerated and employed in the VLSI domain due to numerous social necessities, including process geometric requirements and product development.\u003c/p\u003e\u003cp\u003eThe majority of signals in nature are analog, which must be converted into digital signals. In order to convert analog signals to digital signals, ADC is preferred [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e] [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. Compared to other ADCs like Successive Approximation ADC, Sigma-Delta ADC, Dual Slope converters, Sub ranges and Two-Step ADC, Interpolating and Folding ADC, etc., Flash ADC is mostly used for high speed requirements [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. Flash ADC was chosen because of it\u0026rsquo;s simple architecture, parallel functionality, and non-linearity. It uses a comparator and a thermometer to binary encoder as its main digital conversion components [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. The need for comparators directly relates to the resolution. Due to the increased number of comparators, this approach's main drawback is that it uses more power and area [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. Reduced comparators count results in decreased resolution quality. The trade-off between area and resolution quality is thus present. It takes a parallel connection of 2\u003csup\u003eN\u003c/sup\u003e-1 comparators to create an N-bit FADC with high-resolution quality,it uses comparators to relate an analog voltage signal (V\u003csub\u003ein\u003c/sub\u003e) with a reference voltage (V\u003csub\u003eref\u003c/sub\u003e). To get the entire output voltage swing, the gain boosters are fed discrete signals from the comparator [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e].\u003c/p\u003e\u003cp\u003eFlash ADC designs these days needs architecture having high speed operation and less power consumption [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]. Various architectures of ADC have been proposed by researchers now days with different resolutions, sampling rates, power consumptions and temperature ranges. These ADCs are used in different applications for mobile communication devices to measure equipment [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. Since the performance parameters like sampling rate, resolution, and power consumption of an ADC is basically determined by its architecture, one single ADC type cannot cover all applications.As a result, selecting the appropriate ADC for each unique application is crucial. One of the commonly used ADC is flash type ADC because of the better trade off between its performance metrics [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]. A stochastic flash ADC [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e] have used the random comparator offset to set the trip points and the comparators are no longer sized for small offset, they can be shrunk down into digital cells. The used comparators are implemented as digital cells produce a large variation of comparator offset. A digitally controlled bulk voltage trimming offset calibration technique for compensating preamplifier and comparator offsets in flash ADCs [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]. It calibrates offset by adjusting bulk voltages of the ADC preamplifier input pair and avoids introducing additional capacitive loading by calibration devices to improve ADC speed.\u003c/p\u003e\u003cp\u003eAn asynchronous binary-search ADC [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e] with reference range prediction used to reduce the cost of implementation. An original bit-binary-search ADC requires comparators while one only needs ones. A combined AC/DC-coupled output averaging technique for input amplifier design of flash ADC. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging technique used to minimize the offset-induced ADC nonlinearities [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e]. A fully integrated 5-bit flash-type single-flux quantum (SFQ) ADC consists of error correction and a bit-interleaving circuit are integrated with complementary quasi-one-junction SQUID (CQOS) comparators. 10-bit dual-channel pipelined flash successive approximation register (SAR) based ADC [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e] consists of two channels for high operating speed, and each channel adopts a pipelined flash\u0026ndash;SAR architecture for low power and a small area. This flash\u0026ndash;SAR ADC in the second stage composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. A periodic comparator used to minimize its phase-dependent nonlinearities and using differential \u0026ldquo;quasi-one-junction\u0026rdquo; SQUID (DQOS) quantization for low-inductance clocking scheme [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e].\u003c/p\u003e\u003c/div\u003e\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\u003ch2\u003e1.2 Related works\u003c/h2\u003e\u003cp\u003eHafeez et al. [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e] discussed two essential components of the Flash ADC and integrated within this architecture. Switched-capacitor positive feedback (SCPF) comparators used to reduce hardware utilization with replacement for conventional comparators structure. The SCPF comparator tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision.. Zahrai et al. [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e] has presented a hybrid flash-TI ADC with four interleaved CABS ADCs. A flash ADC used to resolve the most significant bits (MSBs), whereas a TI ADC resolves the least significant bits (LSBs). The fast MSB conversion by the flash ADC together with sub-ranging helps to reduce the number of interleaved ADCs, which results in higher input bandwidth (BW). This paper uses a CABS ADC in TI architecture to take advantage of its high-speed low-power performance, which further reduces the number of interleaved slices in given process technology.\u003c/p\u003e\u003cp\u003ePrathiba et al. [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e] suggested a Self Calibrated Flash ADC with 3.77-bit ENOB and 0.321pJ/conv. -step Figure of Merit for the supply voltage 1.5V. A Direct Bubble Error Controller (DBEC) block is utilized following a series of low-leakage power comparators called a Sleep Transistor based NAND LTE (ST-NAND-LTE) comparator in order to remove the source of bubble code faults. When compared to the traditional comparator methodology, this method reduces power by 93.12% and delays by 66.35%. For wire line receivers, Wang et al. [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e] have introduced a 4GS/s single channel folding flash ADC with time-interleaved. Depending on the link loss and modulation scheme, the ADC's resolution can be scaled to provide power savings. While the LSBs are determined by a 5-bit full flash where each comparator can be separately enabled and disabled, the MSB is determined by a 1-bit folding stage. The ADC with a VGA at 6-bit resolution uses 34.4mW from a 0.9V supply to obtain an SNDR of 30.7dB and an SFDR of 40.6dB at Nyquist frequency, resulting in a FOM of 303fJ/conv-step.\u003c/p\u003e\u003cp\u003eWu et al. [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e] introduced a different class of ADC architecture that non-uniformly samples the analog input and shifts from conventional voltage quantization to a hybrid quantization paradigm wherein both voltage and time quantization are utilized. In this architecture, the sampling rate adapts to the input frequency, which maintains an alias free spectrum and enables an anti-aliasing (AA) filtering in the digital domain to relax the analog AA filter. Prathiba et al. [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e] suggested a structure includes the Successive Approximation Register (SAR) control logic, the Low Voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier. The Reduced Switching Capacitance DAC array reduces the switching energy by 93% and the pre-amplifier in the comparator structure is frequently used to reduce DC offset voltage and kickback noise without significantly lowering the Signal-to-Noise Ratio (SNR), whereas the latch is required for comparison.\u003c/p\u003e\u003cp\u003eAhmed et al. [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e] proposed a comparator generates inherent embedded threshold voltage and it using the variable threshold voltage generation method for producing the reference voltage for the flash ADC design.There are several advantages to using an optimized comparator, including the elimination of the need for a front-end track and hold circuit and a reference resistor ladder.This reduces both layout area and power consumption and makes it appropriate for SoC ADC implementation. The modified CMOS inverter based comparator achieves average power consumption of 1.46\u0026micro;W with propagation delay of 53.8ps. Couto-pinto et al. [\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e] introduced a flash ADC with the relaxation of detailed comparator requirements, and ensured monotonic characteristic and lead to less area and lower power consumption when compared to a conventional flash ADC. The invented technique leads to an 8-bit OST ADC with an ENOB of 4.5-bit, while a conventional 6-bit topology for the same performance would require comparators employing much larger transistors increasing the ADC die area and power.\u003c/p\u003e\u003cp\u003eFahmy et al. [\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e] discussed an all-digital programmable and reconfigurable stochastic ADC. This ADC directly benefits from scaling by using only digital gates and relying on increased mismatch between minimum sized transistors. The programmability and reconfigurability are achieved by dividing the design into 8 channels. Each channel mean is independently set using a 10-bit control word and an analog reference voltage that is digitally created. The output of each channel literalized using Gaussian linear interpolation. Yoshioka et al. [\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e] proposed a binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. A prototype sub-ranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency.\u003c/p\u003e\u003cp\u003ePrathiba et al. [\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e] proposed a 4-bit low-power and high-speed Clocked Flash ADC (C-FADC) that involves a low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE). By reducing the propagation delay, the clock network in the comparator reduces skew and jitter. The Binary Encoder converts the bubble-free code into binary code after the ABF logic circuit has identified and corrected fourth order bubble error in the thermometer code. Caldwell et al. [\u003cspan citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e] have demonstrated a reconfigurable continuous-time low-pass modulator for direct-conversion receivers. The speed and linearity of the flash ADC and DAC improved, and the flash calibration, reference shuffling, and a dynamic element matching scheme that reduces distortion in the DAC. Third-order multi-stage multi-path feed forward amplifiers with low flicker noise and high-bandwidth helped improve the power-efficiency of the modulator.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eTo create an N-bit clock gating FADC, a parallel connection of 2\u003csup\u003eN\u003c/sup\u003e-1 comparators with high-resolution quality is required to link an analog voltage signal (V\u003csub\u003ein\u003c/sub\u003e) with a reference voltage (V\u003csub\u003eref\u003c/sub\u003e). To obtain the full output voltage swing, the gain boosters are fed discrete signals from the comparator. The thermometer code is the output of gain booster circuits. If the value one is shown above zero in a thermometer code, a bubble error is presented. By using Inverted AND Gate Bubble Error Controller (IAG-BEC), these bubble errors are reduced. The Clock Gating NOR-LTE comparator (CG-NOR-LTE), IAG-BEC (Inverted AND Gate Bubble Error Controller) and Adaptive Priority Encoder (APE) are used in the proposed Clock Gating Flash ADC (CG-FADC) to minimize the area and power consumption while maintaining high resolution quality.\u003c/p\u003e\u003cp\u003eIn this manuscript, a 5-bit 1.5GS/s CG-Flash-ADC is simulated in 0.18 \u0026micro;m Complementary MOS technology at a supply voltage of 0.8V. Power consumption is then recorded at different temperatures by varying the width of the channel and supply voltage. Results show that the power consumption reduced to significant level as the supply voltage decreases. Temperature variation is also recorded, and it shows for lower supply voltage the variation in power consumption is less as compared to higher supply voltage. Furthermore, the simulated work is then compared with the latest existing flash-ADC designs. This paper is organised as follows: The CG-FADC and its functionalities are introduced and explains how the study was founded in Section 1. In section 2, a brand-new CG-FADC is suggested. Sections \u003cspan refid=\"Sec8\" class=\"InternalRef\"\u003e3\u003c/span\u003e present simulation results and discussion. Segment 4 illustrates the ending section.\u003c/p\u003e\u003c/div\u003e"},{"header":"2. Clock Gating- Flash ADC","content":"\u003cp\u003eCG-Flash ADC is suggested as a solution to the drawbacks of earlier research, and it is made for real time applications. To achieve high speed and accuracy, the suggested approach uses an Adaptive Priority Encoder (APE) and a low switching power CG-NOR-LTE comparator. The proposed CG-Flash-ADC design consists three key functionalities are CG-NOR-LTE comparator, Inverted AND Gate Bubble Error Controller (IAG-BEC), and an Adaptive Priority Encoder. Figure \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e shows the blocks in Clock Gating Flash ADC. The analog electrical signal is transformed into thermometer code (TE\u003csub\u003e01\u003c/sub\u003e to TE\u003csub\u003e31\u003c/sub\u003e) via the CG-NOR-LTE comparator. While converting the analog signals to the thermometer code several bubble errors may occur and this can be corrected by IAG-BEC corrector. The APE (Adaptive Priority Encoder) transforms the corrected thermometer code (B\u003csub\u003e0\u003c/sub\u003e to B\u003csub\u003e31\u003c/sub\u003e) into S\u003csub\u003e0\u003c/sub\u003e to S\u003csub\u003e4\u003c/sub\u003e binary outputs. There are three factors can create the bubble errors in the conventional comparator techniques. The first factor is device mismatch and comparator offset Voltage. In the thermometer code, bubbles occur when a \u0026quot;1\u0026quot; appears before a \u0026quot;0\u0026quot; due to variations in the offset voltages caused by different comparators structure. Making the devices larger physically is a basic strategy to enhance matching. The influence of random changes is lessened by larger devices, which often show better matching qualities. Include a two-stage strategy with two operating stages as well to lessen the offset brought on by mismatch. The suggested comparator design is superior at minimizing offset from device mismatch. This involves minimizing offset brought on by employing a two-stage (Clock and Clockbar) strategy with two operational phases.\u003c/p\u003e\n\u003cp\u003eThe second factor is clock skew and third factor is clock jitter. All high performance processor architectures today need clock generation and distribution circuitry. Bubble errors may be produced by comparator outputs that are delayed or impacted by changes in the clock signal\u0026apos;s timing causes skew and jitter. The clock distribution network on a tiny chip consists of only a wire and perhaps an inverter. Clock skew is the result of changes in the RC delay of the wire resistance and gate load on real chips, which causes the clock to reach various elements at different times. Buffers are used by most chips to equalize the delay. Minimizes skew without completely eliminating it. Clock skew is a spatial variation in temporally comparable clock edges.\u003c/p\u003e\n\u003cp\u003ePositive and negative clock skews are the two types of clock skews that are examined and evaluated and it is shown in Figure. 2(a) and (b). The clock and data flow travel in the same direction when there is a positive clock skew, and in the opposite way when there is a negative clock skew. If \u0026delta; (delay) is greater than 0 in the positive clock skew, the comparator circuit performs better, but it is challenging to reach the hold time (T\u003csub\u003eh\u003c/sub\u003e). When the hold time is not reached, the race condition occurs. If \u0026delta; (delay) is less than zero in the negative clock skew, the comparator circuit performance is deteriorated; however, it is simple to reach the hold time (T\u003csub\u003eh\u003c/sub\u003e), and race circumstances are avoided. Temporal variations in consecutive clock signal edges are caused by clock jitter. Jitter and skew both have an impact on the effective cycle time and it is displayed in Figure. 2(c) and (d). Assuming jitter tracks in the same direction, only skew has an impact on the race margin. The suggested CG-NOR-LTE comparator, the clock and clockbar technique distribute the clock signal to all the elements at same time and the buffer circuit add in the output of CG-NOR-LTE comparator.\u003c/p\u003e\n\u003cdiv id=\"Sec5\" class=\"Section2\"\u003e\n \u003ch2\u003e2.1 Proposed CG-NOR-LTE Comparator\u003c/h2\u003e\n \u003cp\u003eThe comparator is a critical component of the flash ADC for analog-to-digital conversion. The number of comparators used varies according to the resolution of the flash ADC. For an N-bit resolution flash ADC, the comparator count increases by 2\u003csup\u003eN\u003c/sup\u003e-1. If the resolution of the ADC grows, so does the use of comparator count in the ADC is increased then the area and switching power also increased. In order to overcome the area and switching power problem in the flash ADC, the suggested comparator examines the area, processing delay and switching power factor. A typical flash ADC uses a group of resistors from the ladder circuit to produce a comparator reference voltage, which can be overcome by the low switching CG-NOR-LTE comparator technique. The conventional comparator technique consumes more switching power because the reference potential generated by the group of resistors in the circuit. A compact and low switching power CG-NOR-LTE comparator is proposed in this study.\u003c/p\u003e\n \u003cp\u003eThe suggested low switching power CG-NOR-LTE comparator compares the analog input voltage to an internally created reference voltage before producing a binary output. It is composed of a single CMOS-NOR-LTE comparator and two sets of NMOS and PMOS transistors that are controlled by the clock and clockbar signals. The internally generated reference voltage, which is produced by varying the transistor widths with constant \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eg1\u003c/em\u003e\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eg2\u003c/em\u003e\u003c/sub\u003e values, is compared to the input voltage by the CG-NOR-LTE comparator. The proposed CG-NOR-LTE Comparator schematic illustration is shown in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e. It uses two sets of CMOS transistors P5, N5 and P6, N6 wired in parallel, as well as one CMOS NOR-LTE logic inverter with P2, P3, P4 and N2, N3. N4 transistors act as comparator. Each pair pulls the NOR-LTE logic inverter circuits up and down. The PMOS (P5, P6) and NMOS (N5, N6) transistors are guided by the two operational phases are clock and clockbar pulse. When the clock input is high, the transistors P5 and N5 to activate the NOR-LTE inverter logic produce an output is low. Similarly, the low clock input the transistors P6 and N6 to activate the NOR-LTE inverter logic generate an output is high. The length (L) and width (W) of PMOS and NMOS are adjusted to produce the required switching voltage. The transistors P7 and N7 are act as a buffer circuit, which is connected at the output of NOR-LTE comparator used to minimize the processing delay.\u003c/p\u003e\n \u003cp\u003eThe switching voltage of the comparator is depending on the threshold voltages of PMOS and NMOS transistors, which is used in the inverter circuit. The threshold voltage should not be altered too much in order to lower the design power usage. On the other hand, channel noise can impact the output and produce a nonlinear switching pattern even if the transistor length is kept extremely short to get a high speed. Consequently, the transistor width is utilized to produce various switching voltages, while the transistor length (L) is fixed at a nominal value. The signal rise or fall time at the gate terminal\u0026apos;s output decreases as the transistor width (W) grows since it increases the transistor current drive capability. As transistor size rises, active devices active area and layout area may also increased. The transistor specifications and their values for the suggested CG-NOR-LTE comparator are displayed in Table \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e.To determine whether the output of the comparator is high or low, \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003ein\u003c/em\u003e\u003c/sub\u003e is compared to \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eref\u003c/em\u003e\u003c/sub\u003e. The NOR-LTE Comparator that is controlled by clock signals is combined to create a CG-NOR-LTE comparator. 2\u003csup\u003eN\u003c/sup\u003e-1comparators can be used to run the N bit flash ADC. 31 comparators can be used to create a 5-bit flash ADC. The threshold voltage, which may be used as a reference value, is varied by changing the transistor sizes.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab1\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eTransistor parameters of CG-NORT-LTE comparator\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eS.NO\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eTransistor Parameter\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eValue (\u0026micro;m)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ePMOS Width (W\u003csub\u003ep\u003c/sub\u003e) Max\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5.6\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ePMOS Width (W\u003csub\u003ep\u003c/sub\u003e) Min\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.2\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNMOS Width (W\u003csub\u003en\u003c/sub\u003e) Max\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eNMOS Width (W\u003csub\u003en\u003c/sub\u003e) Min\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.12\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eL\u003csub\u003ep\u003c/sub\u003e=L\u003csub\u003en\u003c/sub\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.18\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec6\" class=\"Section2\"\u003e\n \u003ch2\u003e2.2. Inverted AND Gate (ING) Bubble Error Controller\u003c/h2\u003e\n \u003cp\u003eAs the sampling rate and input frequency rises, the dynamic noise from clock skew (delay) and aperture jitter significantly worsens. Device mismatch is a major source of error due to process variance, in addition to dynamic disturbances. Input offset voltages are the name given to these error sources, which have the potential to seriously impair encoder performance. A logical \u0026quot;1\u0026quot; may show up above a logical \u0026quot;0\u0026quot; in the thermometer code at the output of parallel comparators when the input-referred offset voltage is greater than 0.5 LSB. It refers to this as a \u0026quot;bubble.\u0026quot; The ADC\u0026apos;s operating speed is decreased with the potential to include more bubble errors in the thermometer code. The bubble error correction circuit could be incorporated into the suggested CG-FADC to increase speed and accuracy. Figure. 4 display the Inverted AND Gate Bubble Error Controller (IAG-BEC).\u003c/p\u003e\n \u003cp\u003eAn Inverted AND Gate Bubble Error Controller (IAG-BEC) is designed using one 2 input inverted AND gate, one 3 input inverted AND gate, one 4 inputs inverted AND gate and twenty seven counts of 5 inputs inverted AND gate. The input bubble error code is corrected by using IAG-BEC circuit by generating One-Hot Code. Based on the priority an Adaptive Priority Encoder generates the binary code from the input One-Hot Code.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec7\" class=\"Section2\"\u003e\n \u003ch2\u003e2.3 Adaptive Priority Encoder (APE)\u003c/h2\u003e\n \u003cp\u003eAdaptive Priority Encoder is a circuit shown in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e, which compresses multiple binary inputs into a minor number of outputs. The APE output is the binary depiction of the unique number starting from zero of the most important input bits. They often help to regulate interrupt requests by acting on the highest priority encoder. It is designed using two Priority Encoder (PE-1 and PE-2), each can accept 16 inputs and provides 4 outputs in binary representation. The Priority Encoder (PE-1 and PE-2) are constructed using 4 inputs OR gates and then the output of PE-1 and PE-2 given as input of 2 input OR gate to get Binary code S\u003csub\u003e0\u003c/sub\u003e to S\u003csub\u003e4\u003c/sub\u003e from thermometer code which reduces the transistor count by 18.47% compared to the conventional structure. Based on highest priority, the enable signal of the APE selects the inputs and transfers it to the corresponding output binary code.\u003c/p\u003e\n \u003cp\u003eAn Adaptive Priority Encoder is preferred to achieve high speed over the existing encoders such as Fat tree encoder, MUX based encoder and Priority encoder. The Truth Table of encoder is exposed in Table \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e. TE\u003csub\u003e31\u003c/sub\u003e to TE\u003csub\u003e1\u003c/sub\u003e indicate the inputs, B\u003csub\u003e31\u003c/sub\u003e to B\u003csub\u003e1\u003c/sub\u003e are one hot code and S\u003csub\u003e5\u003c/sub\u003e to S\u003csub\u003e0\u003c/sub\u003e indicate the outputs of Priority Encoder where the 31-bit thermometer codes are converted into 5-bit binary code. The 5-bit binary code output is from 00000\u0026apos;s to 11111\u0026apos;s. In order to attain high speed over the current encoders, the priority encoder is recommended. The Priority Encoder is an alternative type of combinational circuit compared to the binary encoder, excluding that it produces an output code depending on the highest prioritized input. The output binary code S\u003csub\u003e4\u003c/sub\u003e to S\u003csub\u003e0\u003c/sub\u003e is obtained by Eq. (1) to (5).\u003c/p\u003e\n \u003cdiv id=\"Equa\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equa\" name=\"EquationSource\"\u003e$$\\:{\\varvec{S}}_{4}={\\varvec{B}}_{16}+{\\varvec{B}}_{17}+{\\varvec{B}}_{18}+{\\varvec{B}}_{19}+{\\varvec{B}}_{20}+{\\varvec{B}}_{21}+{\\varvec{B}}_{22}+{\\varvec{B}}_{23}+{\\varvec{B}}_{24}+{\\varvec{B}}_{25}+{\\varvec{B}}_{26}+{\\varvec{B}}_{27}+{\\varvec{B}}_{28}+{\\varvec{B}}_{29}+{\\varvec{B}}_{30}+{\\varvec{B}}_{31}\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\left(1\\right)$$\u003c/div\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Equb\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equb\" name=\"EquationSource\"\u003e$$\\:{\\varvec{S}}_{3}={\\varvec{B}}_{8}+{\\varvec{B}}_{9}+{\\varvec{B}}_{10}+{\\varvec{B}}_{11}+{\\varvec{B}}_{12}+{\\varvec{B}}_{13}+{\\varvec{B}}_{14}+{\\varvec{B}}_{15}+{\\varvec{B}}_{24}+{\\varvec{B}}_{25}+{\\varvec{B}}_{26}+{\\varvec{B}}_{27}+{\\varvec{B}}_{28}+{\\varvec{B}}_{29}+{\\varvec{B}}_{30}+{\\varvec{B}}_{31}\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\left(2\\right)$$\u003c/div\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Equc\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equc\" name=\"EquationSource\"\u003e$$\\:{\\varvec{S}}_{2}={\\varvec{B}}_{4}+{\\varvec{B}}_{5}+{\\varvec{B}}_{6}+{\\varvec{B}}_{7}+{\\varvec{B}}_{12}+{\\varvec{B}}_{13}+{\\varvec{B}}_{14}+{\\varvec{B}}_{15}+{\\varvec{B}}_{20}+{\\varvec{B}}_{21}+{\\varvec{B}}_{22}+{\\varvec{B}}_{23}+{\\varvec{B}}_{28}+{\\varvec{B}}_{29}+{\\varvec{B}}_{30}+{\\varvec{B}}_{31}\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\left(3\\right)$$\u003c/div\u003e\n \u003c/div\u003e\n \u003cdiv id=\"Equd\" class=\"Equation\"\u003e\n \u003cdiv class=\"mathdisplay\" id=\"FileID_Equd\" name=\"EquationSource\"\u003e$$\\:{\\varvec{S}}_{1}={\\varvec{B}}_{2}+{\\varvec{B}}_{3}+{\\varvec{B}}_{6}+{\\varvec{B}}_{7}+{\\varvec{B}}_{10}+{\\varvec{B}}_{11}+{\\varvec{B}}_{14}+{\\varvec{B}}_{15}+{\\varvec{B}}_{18}+{\\varvec{B}}_{19}+{\\varvec{B}}_{22}+{\\varvec{B}}_{23}+{\\varvec{B}}_{26}+{\\varvec{B}}_{27}+{\\varvec{B}}_{30}+{\\varvec{B}}_{31}\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\:\\left(4\\right)$$\u003c/div\u003e\n \u003c/div\u003e\n \u003cp\u003eTable 2. Truth Table of encoder\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Taba\" border=\"1\" class=\"fr-table-selection-hover\"\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eThermometer code (TE\u003csub\u003e31\u003c/sub\u003e to TE\u003csub\u003e1\u003c/sub\u003e)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eOne hot code(B\u003csub\u003e31\u003c/sub\u003e to B\u003csub\u003e1\u003c/sub\u003e)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePriority Encoder output\u003c/p\u003e\n \u003cp\u003e(S\u003csub\u003e4\u003c/sub\u003e to S\u003csub\u003e0\u003c/sub\u003e)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1111111111111111110111111111111\u003c/p\u003e\n \u003cp\u003e0111110111111111111111111111111\u003c/p\u003e\n \u003cp\u003e0010111111111111111111111111111\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e0000000000000000000000000000011\u003c/p\u003e\n \u003cp\u003e0000000000000000000000000000001\u003c/p\u003e\n \u003cp\u003e0000000000000000000000000000000\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e10000000000000000000000000000000\u003c/p\u003e\n \u003cp\u003e0100000000000000000000000000000\u003c/p\u003e\n \u003cp\u003e0010000000000000000000000000000\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e00000000000000000000000000000100\u003c/p\u003e\n \u003cp\u003e00000000000000000000000000000010\u003c/p\u003e\n \u003cp\u003e0000000000000000000000000000001\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e11111\u003c/p\u003e\n \u003cp\u003e11110\u003c/p\u003e\n \u003cp\u003e11101\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e.\u003c/p\u003e\n \u003cp\u003e00010\u003c/p\u003e\n \u003cp\u003e00001\u003c/p\u003e\n \u003cp\u003e00000\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"3. RESULTS AND DISCUSSION","content":"\u003cp\u003eThe 5-bit 1.5GS/s CG-FADC schematic design was implemented in 0.18 \u0026micro;m CMOS Technology using S-Edit (Tanner EDA Tool) and simulated using T-Spice.\u003c/p\u003e\n\u003cdiv id=\"Sec9\" class=\"Section2\"\u003e\n \u003ch2\u003e3.1 Simulation Result of CG-NOR-LTE Comparator\u003c/h2\u003e\n \u003cp\u003eTable\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e shows the power consumption and processing delay for various comparators. The proposed CG-NOR-LTE comparator consumes the reduced power compared to CMOS-LTE comparator; CMOS-NOR-LTE comparator and CMOS-NAND-LTE comparator are 95.66%, 93.58% and 91.78% and the processing delay reduced by 89.65%, 86.95% and 83.33% respectively. The power consumption and processing delay analysis for various comparators is displayed in Figure. 6. The output response of the suggested CG-NOR-LTE comparator is displayed in Figure.7.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab3\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 3\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003ePower consumption and Processing delay for various Comparator Techniques\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eS.No\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eComparator Technique\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePower consumption(mW)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eProcessing Delay(\u0026micro;s)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eCMOS-LTE comparator\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5.53\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.9\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eCMOS-NOR-LTE comparator\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.74\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.3\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eCMOS-NAND-LTE comparator\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.92\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eCG-NOR-LTE comparator\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.24\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.3\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec10\" class=\"Section2\"\u003e\n \u003ch2\u003e3.2 Simulation Result of Adaptive Priority Encoder (APE)\u003c/h2\u003e\n \u003cp\u003eTable \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e shows the power dissipation and transistor count for different encoding schemes. The suggested Adaptive Priority Encoder (APE) dissipates the power minimized by 74.47%, 62.35% and 58.24% compared to Fat Tree Encoder, MUX based Encoder and Priority Encoder. Figure\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e shows the Analysis of power dissipation and Transistor count for different Encoding schemes. From this chart it is observed that the Transistor count of the recommended Adaptive Priority Encoder utilizes the Transistor count reduced by 33.62%, 27.88% and 18.47% compared to Fat Tree Encoder, MUX based Encoder and Priority Encoder.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab4\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 4\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003ePower dissipation and Transistor count for different encoding schemes\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eS.No\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eEncoding schemes\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePower dissipation(\u0026micro;W)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eTransistor count\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eFat Tree Encoder\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12.3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e226\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eMUX based Encoder\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e8.34\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e208\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ePriority Encoder\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7.52\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e184\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eAdaptive Priority Encoder\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.14\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e150\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec11\" class=\"Section2\"\u003e\n \u003ch2\u003e3.3 Simulation Result of CG-FADC\u003c/h2\u003e\n \u003cp\u003eThis section of the manuscript does power analysis. With a supply voltage of 0.8 volts, 0.18\u0026micro;m CMOS technology based on SPICE simulates Clock Gating flash-ADC. The first step in the investigation is to determine the flash-ADC\u0026apos;s power consumption by adjusting the supply voltage and width. The detailed record of power consumption at various temperatures and NMOS and PMOS channel widths are considered for analysis. To observe changes in power consumption, the NMOS channel width is adjusted from 1.12\u0026micro;m to 4\u0026micro;m, the PMOS channel width is adjusted from 4.5\u0026micro;m to 0.13\u0026micro;m and then the temperature is adjusted at each channel width. The temperature fluctuates between \u0026minus;\u0026thinsp;20\u0026deg;C and 60\u0026deg;C. This 5-Bit CG-Flash-ADC is emulated at a sampling rate of 1.5 GS/s. The power consumption at different temperatures, channel width, and supply voltages is recorded at this sampling rate.\u003c/p\u003e\n \u003cp\u003eThe Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e shows that the power consumption is lower for NMOS and PMOS channels with a width of 1.12\u0026micro;m and 0.2\u0026micro;m respectively, and that it is as low as 10.63mW at -20\u0026deg;C. This power consumption rises as the temperature rises from \u0026minus;\u0026thinsp;20\u0026deg; to +\u0026thinsp;60\u0026deg;. At 60\u0026deg;C, the high power usage of 15.45mW is measured. The highest power consumption is measured at +\u0026thinsp;60\u0026deg; C for the NMOS and PMOS channel widths 4\u0026micro;m and 5.6\u0026micro;m respectively. This occurs because the resistance of the MOS device changes with width, which raises the power consumption. Figure. 9 shows the various power consumptions measured from 0.2\u0026micro;m to 5.6\u0026micro;m PMOS channel width for different temperature.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab5\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 5\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003ePower consumption with various temperature and different channel width of CG-Flash-ADC\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\" rowspan=\"2\"\u003e\n \u003cp\u003eNMOS width(\u0026micro;m)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\" rowspan=\"2\"\u003e\n \u003cp\u003ePMOS width(\u0026micro;m)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\" colspan=\"9\"\u003e\n \u003cp\u003eTemperature(\u0026deg;C)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e-20\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e-10\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e10\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e20\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e30\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e40\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e50\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e60\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e10.63\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e11.72\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12.80\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12.96\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.11\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.45\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.86\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e15.45\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.86\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e0.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.26\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.89\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.31\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.85\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e15.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e15.76\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e16.53\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e17.22\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.00\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e1.4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.28\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.99\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e15.16\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e16.45\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e16.73\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e17.14\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e17.68\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e18.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e19.76\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2.62\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e16.92\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e17.12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e17.83\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e18.21\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e18.94\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e19.45\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e20.23\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e20.94\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e21.13\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3.14\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e2.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e20.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e20.78\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e21.23\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.68\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.16\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.79\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e24.56\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e25.69\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.77\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.62\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e24.12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e25.77\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e26.23\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e27.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e28.94\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e29.37\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e30.54\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e3.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e25.61\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e27.49\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e28.54\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e29.28\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e28.58\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e29.27\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e30.56\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e31.69\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e32.83\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4.4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e28.42\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e31.56\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e32.11\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e33.52\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e34.41\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e35.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.75\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e37.54\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.25\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5.0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e30.56\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e32.41\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e33.67\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e34.13\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e34.98\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.97\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e37.97\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.69\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e39.88\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e32.41\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e33.52\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e34.75\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e35.54\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.87\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e37.12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.55\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e40.49\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e43.61\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eThe variation in the power consumption is observed and recorded in the Table \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e. It is possible to reduce power consumption by lowering the supply voltage, however doing so comes at the sacrifice of speed. The maximum power consumption is observed by 15.45mW for 1.5V supply voltage at -20\u0026deg; C and the minimum power consumption is achieved by 10.63mW for 0.8V supply voltage at +\u0026thinsp;60\u0026deg; C, which provides 31% power variations. Similarly, for 0.9V to 1.4V supply voltage the pattern follows the same increasing pattern. But at 1.5V supply voltage the increment in the power consumption starts saturating and a variation of only 3.7% is recorded. However, at 1.5V supply voltage the pattern changes and power consumption start decreasing with temperature. At -20\u0026deg;C 112.7mW of power consumption is recorded which will decrease to 108.5mW at +\u0026thinsp;60\u0026deg;C. Figure\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e shows this decreasing pattern of power consumption graphically and Fig. 11 (a and b) shows that the maximum DNL and INL are \u0026minus;\u0026thinsp;0.65/+0.45 LSB and \u0026minus;\u0026thinsp;0.67/+0.47 LSB, respectively.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab6\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 6\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eVarious power consumption with different supply voltages and temperature\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\" rowspan=\"2\"\u003e\n \u003cp\u003eSupply\u003c/p\u003e\n \u003cp\u003evoltage(Volts)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\" colspan=\"9\"\u003e\n \u003cp\u003eTemperature(\u0026deg;C)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e-20\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e-10\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e0\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e10\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e20\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e30\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e40\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e50\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003e60\u0026deg;\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e112.7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e112.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e111.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e111.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e110.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e110.3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e109.7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e109.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e108.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e93.73\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e94.25\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e94.78\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e94.97\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e95.24\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e95.72\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e95.93\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e96.21\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e96.78\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e82.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e82.63\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e83.12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e83.68\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e83.97\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e84.31\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e84.65\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e84.87\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e85.12\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e70.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e70.69\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e71.44\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e71.82\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e72.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e72.54\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e72.88\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e73.26\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e73.59\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e53.14\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e53.42\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e53.75\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e54.03\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e54.18\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e54.42\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e54.74\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e55.18\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e55.64\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e35.83\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.24\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.41\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e36.98\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e37.29\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e37.76\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.26\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e38.47\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.9\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e21.41\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e21.96\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.42\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.67\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e22.93\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.16\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.35\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.58\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e23.91\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e10.63\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e11.72\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12.80\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e12.96\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.11\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e13.45\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.22\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e14.86\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e15.45\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec12\" class=\"Section2\"\u003e\n \u003ch2\u003e3.4 Corner outcomes of CG-FADC\u003c/h2\u003e\n \u003cp\u003eAspects of NMOS and PMOS variable behavior, such as the required Slow Fast (SF) or Fast Slow (FS) regions, can be reflected in corner outcomes. To assess the effectiveness of the NMOS and PMOS, experiments were conducted at the SS, TT, SF, FS, and FF process corners. Simulations were run for various supply voltages (0.8 V to 1.5 V) at temperatures between \u0026minus;\u0026thinsp;20\u0026deg;C and +\u0026thinsp;60\u0026deg;C.\u003c/p\u003e\n \u003cp\u003eThe SNDR and SFDR with process corner modifications are shown in Fig. 12 (a and b). For both the SNDR and SFDR, the FF corner performs best at all temperatures, peaking between 30 to -10 ◦C. The FS corner varies significantly with temperature and performs the worst at all temperatures. While most corners operate slightly worse at high temperatures, peak performance happens at room temperature 30 to -20 ◦C. The behavior of TT and SF corners is very constant over the temperature range. More temperature variation is seen in corners FF, SS, and FS.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec13\" class=\"Section2\"\u003e\n \u003ch2\u003e3.5 Performance metrics and results comparison of CG-FADC\u003c/h2\u003e\n \u003cp\u003eTable \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e summarizes the performance metrics of the proposed 5-bit 1.5Gs/s CG-FADC architecture. The CG-FADC results for INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are \u0026minus;\u0026thinsp;0.67 /+0.47 and \u0026minus;\u0026thinsp;0.45 /+0.65 LSB, respectively obtained with the Maximum Resolution Bandwidth (MRB) of 500MHz. The twelfth harmonic limited the measured SFDR (Spurious Free Dynamic Range) of 32.63 dB Full Scale (FS), and the SNDR obtained from an FFT was 29.45 dB, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e13\u003c/span\u003e.With a 0.8 V supply, the ADC achieves a 4.59 ENOB (Effective Number of Bits) at 1.5 GS/s while consuming 10.63mW of power. The PDP (Power Delay Product) improves efficiency without significantly compromising execution speed. The trade-off between the circuit\u0026apos;s speed performance and efficiency can be clearly evaluated using the PDP. The intentional PDP indicates that the CG-FADC arrives at 132.8 pJ _ ns/conv.-step while considering the conversion speed.\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab7\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 7\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003ePerformance Metrics of CG \u0026ndash;FADC\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eS.No\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eParameters\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eObserved Values\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eTechnology (\u0026micro;m)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.18\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSupply voltage (V)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.8\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eResolution (bit)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eProcessing delay (\u0026micro;S)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e12.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eMaximum sampling rate (GS/s)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.5\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ePower consumption (mW)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e10.63\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eENOB (bits)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4.59\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSNDR (dB)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e29.45\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e9\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eSFDR (dB)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e32.63\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e10\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eDNL (LSB)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-0.45 /+0.65\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e11\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eINL (LSB)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-0.67 /+0.47\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e12\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eFOM pJ/conv.-step\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.44\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e13\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003ePDP (pJ _ ns/conv.-step)\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e132.8\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n \u003cp\u003eThe performance comparison between the recommended CG-ADC and other announced Flash ADCs is displayed in Table \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e. It is demonstrated that a superior trade-off between speed, power, MRB, and FOM in Flash ADC architectures, as well as excellent unique execution, could be achieved by the intended Flash ADC. The demonstrated work has a Maximum Resolution Bandwidth (MRB) of 500 MHz is lower than the authors [\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e] and consumes 10.63mW less power than references [\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e7\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e, \u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e].\u003c/p\u003e\n \u003cdiv class=\"gridtable\"\u003e\n \u003ctable id=\"Tab8\" border=\"1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 8\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eParameters Comparison of the proposed SC -FADC with other Flash ADCs\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eParameters\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSpeed\u003c/p\u003e\n \u003cp\u003e(GS/s)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eProcess\u003c/p\u003e\n \u003cp\u003e(nm)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eResolution\u003c/p\u003e\n \u003cp\u003e(bits)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eENOB\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSupply\u003c/p\u003e\n \u003cp\u003e(v)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003ePower (mW)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eMRB\u003c/p\u003e\n \u003cp\u003e(MHz)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSNDR (dB)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eSFDR (dB)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eDNL/INL\u003c/p\u003e\n \u003cp\u003e(\u0026plusmn;\u0026thinsp;LSB)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eFOM (pJ/\u003c/p\u003e\n \u003cp\u003eConv-step)\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003eThis work\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e1.5\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e180\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e\u003cstrong\u003e5\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e4.59\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e0.8\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e10.63\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e500\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e29.45\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e32.63\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e-0.45/+0.65\u003c/strong\u003e\u003c/p\u003e\n \u003cp\u003e\u003cstrong\u003e-0.67/+0.47\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u003cstrong\u003e0.44\u003c/strong\u003e\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e5\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.2G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e90\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e6.05\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e204m\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e750\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e38.17\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e46.6\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.70/0.64\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.25G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e90\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e6.91\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e207m\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e600\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e43.36\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e57.36\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.3/1.1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.4\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e180\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e4\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e3.48\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.8\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e530m\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e100\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-0.14/+0.15\u003c/p\u003e\n \u003cp\u003e-0.20/+0.24\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.8G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e65\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e5\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4.40\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1.97m\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e700\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e26.92\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e35.90\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0.56/0.62\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e116\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e4G\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e16\u003c/p\u003e\n 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\u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e[\u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e]\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e65\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"char\"\u003e\n \u003cp\u003e7\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e5.88\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e8.11m\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1228\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e36.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e46.2\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e-0.44/+0.54\u003c/p\u003e\n \u003cp\u003e-1.01/+1.07\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e125\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003c/div\u003e\n\u003c/div\u003e"},{"header":"4. Conclusion","content":"\u003cp\u003eThe suggested work presents a Clock Gating Flash ADC (CG-FADC) is fabricated in 0.18\u0026micro;m CMOS VLSI Technology. Using an Adaptive Priority Encoder (APE) and low switching power Clock Gating- NOR-LTE comparator, the prospective design achieves a maximum conversion rate 1.5GS/s with the MRB of 500MHz. The power-hungry resistive ladder and complex encoder structure have been removed by employing various techniques. Based on this CG-FADC technique, the Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR) and Signal-to-Noise and Distortion Ratio (SNDR) are obtained at 4.59, 29.45 dB and 32.63 dB respectively. The prototype ADC draws only 10.63mW of energy from the 0.8-V supply at a sampling frequency of 500 GHz with DNL is -0.45/+0.65 LSB and INL is -0.67/+0.47 LSB and has a FOM of 0.44 pJ/Conversion-step. The main contribution of this design is to reduce the power consumption, propagation delay and area, which can also be employed for low-power CMOS VLSI Integrated circuit designs, such as robotics, instrumentation and measurement, industrial automation, and Internet of Things (IOT) devices.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003e5. Competing interests\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp;The authors state that they have no competing interests.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e6. Conflicts of Interest\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors declare no conflicts of interest\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e7. Consent for publication\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp; \u0026nbsp;\u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;Not applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e8. Ethics Approval and consent to participate\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp; \u0026nbsp;\u0026nbsp; Not applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e9\u003c/strong\u003e\u003cstrong\u003e. Funding\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u0026nbsp; \u0026nbsp; \u0026nbsp; This research work does not have any\u0026nbsp;external\u0026nbsp;funding\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e10\u003c/strong\u003e\u003cstrong\u003e.\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eData Availability Statement\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eData are contained within the article.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e1\u003c/strong\u003e\u003cstrong\u003e1\u003c/strong\u003e\u003cstrong\u003e. Author\u0026rsquo;s Contribution\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eG. Prathiba, \u0026nbsp;and N. Vasu Nithyanandam have developed an innovative idea, designed a new architecture Clock Gating Flash-ADC (CG-FADC) uses CG-NOR-LTE comparator and Adaptive Priority Encoder (APE). G. Prathiba constructs and develops the graphical response for a CG-NOR-LTE comparator, Inverted AND Gate Bubble Error Controller (IAG-BEC) and an Adaptive Priority Encoder (APE). N. Vasu Nithyanandam is reviewing the schematic, simulation output of CG-FADC and corrects the text with alignment. Authors are studied and approved the completed work.\u003c/p\u003e\n\u003col start=\"12\"\u003e\n \u003cli\u003e\u003cstrong\u003eAcknowledgments\u003c/strong\u003e\u003c/li\u003e\n\u003c/ol\u003e\n\u003cp\u003e\u0026nbsp; Not applicable\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e13. Clinical trial number\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eNot applicable\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eChun-Cheng Huang and Jieh-Tsorng Wu, \u0026quot;A background comparator calibration technique for flash analog-to-digital converters\u0026quot;, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 9, pp. 1732-1740, 2005.\u003c/li\u003e\n\u003cli\u003eS. Buchner, T. Meehan, A. Campbell, K. Clark and D. McMorrow, \u0026quot;Characterization of single-event upsets in a flash analog-to-digital converter (AD9058)\u0026quot;, IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2358-2364, 2000.\u003c/li\u003e\n\u003cli\u003eP. M. Figueiredo and J. C. Vital, \u0026quot;Averaging technique in flash analog-to-digital converters,\u0026quot; in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 233-253, Feb. 2004.\u003c/li\u003e\n\u003cli\u003eD. E. Bellasi, L. Bettini, C. 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Li, \u0026quot;A Reconfigurable DeltaSigma ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling,\u0026quot; in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2263-2271, Aug. 2014.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Low switching power, CMOS Clock Gating - NOR-LTE comparator, Inverted AND Gate Bubble Error Controller, Adaptive priority encoder","lastPublishedDoi":"10.21203/rs.3.rs-7704931/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7704931/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eADCs transform analog sensor readings into digital data that Microcontrollers and Processors may use in control algorithms for the majority of applications, such as Robotics, Industrial Instrumentation, Automation and Internet of Things (IOT) devices. Several methods were suggested to convert the analog signal to a discrete signal the analog signal's inaccuracy prevented a successful conversion. High resolution Flash ADC is constructed using MOSFET devices in reliable VLSI circuits to reduce power dissipation. A Novel 1.5 GS/s Clock Gating (CG) Flash ADC was proposed in this study and it involves a low switching power Clock Gating NOR-LTE comparator used to avoid the occurrence of race condition by minimizing the clock skew and jitter, an Adaptive Priority Encoder and Inverted AND Gate Bubble Error Controller. Execution of the suggested CG Flash ADC takes place on a 0.18\u0026micro;m Tanner EDA tool with 0.8V power supply. The observed minimum and maximum power consumption is 10.63mW and 15.45mW at -20\u0026deg;C and +\u0026thinsp;60\u0026deg;C respectively that is equal to 30% variations compared to the conventional method. The measured values of SNDR and SFDR of the proposed 5-bit 1.5GS/s CG-FADC are 29.45 dB and 32.63 dB, with a resulting ENOB of 4.59 bits.\u003c/p\u003e","manuscriptTitle":"A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-10-15 08:56:24","doi":"10.21203/rs.3.rs-7704931/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"d572e1b9-e619-4569-8960-c741d3b310f4","owner":[],"postedDate":"October 15th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-11-07T15:38:35+00:00","versionOfRecord":[],"versionCreatedAt":"2025-10-15 08:56:24","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7704931","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7704931","identity":"rs-7704931","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}