Developing and Assessinginexact Multiplierarchitectures for Imageprocessing

Abstract In the realm of approximate computing, the inexact multiplier architecture stands out as a cornerstone, playing a pivotal role acrosserror-tolerated applications. This article delves into the intricacies ofthree distinct inexact multiplier architectures tailored specifically forimage processing tasks. The study revolves around efficiently partitioning the partial product stage into smaller modules and thenemploying decoder algorithms/truncation techniques, to obtain thesuggested multiplier’s final result. The resulting 8×8 imprecise multipliers are engineered with reduced design overhead and reasonableerror metrics. Through simulation with the Cadence RTL compilerusing TSMC 90 nm technology, the realization showcases substantialarea and power savings compared to conventional imprecise multipliers. Comparing one of the proposed approximate models to precisemultipliers reveals significant reductions in both the area and thepower requirement, amounting to 37.19% and 46.14%, respectively, allwhile ensuring acceptable error metrics. Furthermore, in comparison toalternative approximation multiplier designs, the suggested 8×8 multiplier showcases superior performance metrics. It achieves justifiablemean Structural Similarity Index (SSI) values, making it particularlyadvantageous for tasks such as picture multiplication and sharpening.