Investigation of Variation in Device Design Parameters on the Saturation Voltages of Hetero-junction Nanowire Tunnel FETs

Abstract Estimation of the saturation voltages of beyond CMOS devices is essential for the accurate circuit design and analysis. In this work, we look at the influence of device design parameters on the saturation voltage (VDSAT) of a Tunnel Field Effect Transistor (TFET) using 3D TCAD Numerical Simulations. The variation in channel length, underlap at gate-drain, source/drain doping, and the source/channel material are some of the vital optimization parameters in the design and optimization of TFET based circuits. We observe, with the increasing value of drain bias (VDS), TFET device initially enters in the soft saturation state and subsequently a deep saturation state is attained. These voltages are altered with device variability and hence the analog performance. An increase in drain (source) doping increases (decreases) the soft saturation voltage of TFETs. It is also found that an early onset of saturation can be achieved by the gate-drain underlap in TFETs. The impact of short channel lengths is to worsen the perfect saturation phenomenon in Tunnel FETs. In addition, the reduction in nanowire diameter delays the saturation by few milivolts.