A High-Speed Low-Offset Double Tail Dynamic Comparator for Low-Power Applications

Abstract This paper presents a double tail dynamic comparator (DTDC) to obtain the high speed, low-power and low-offset voltage. In the proposed design, a regenerative latch is activated more quickly and it uses the lowest amount of power with an addition of two PMOS switching transistors MR4 and MR5 to the latch stage. The design and simulations are carried out in 90 nm CMOS technology with the supply voltage of 0.8 V having the clock frequency of 1 GHz. The simulation results confirm that the power consumption and offset voltages are significantly reduced in the proposed DTDC. The power consumption is 11.67 µW, the delay and slew rate are 76.97 ps and 10.51 V/ns, respectively. And also the offset voltage is reduced to 1.657 mV. Further, the total power consumption is reduced by a factor of 77.11 % in comparison to existing works. In addition, the Monte-Carlo simulation for the analysis of the 1-sigma offset error is performed.