Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Abstract The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.