A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance ( R on,sp ) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width ( W ch ) and has the effect of modulating current distribution, resulting in lower R on,sp and higher transconductance ( g m ). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region ( N d-opt ) and further reducing the R on,sp . Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage ( BV ). Meanwhile, gate-drain charge ( Q GD ) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the N d-opt . The highly doped N-drift region provides a low-resistance path for the current, which also further reduces R on,sp . Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the R on,sp and Q GD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.