Direct Bonding of 6-inch SiC/Si Wafer with Enhanced Thermal Interface | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Direct Bonding of 6-inch SiC/Si Wafer with Enhanced Thermal Interface Peng Gao, Szuyu Huang, Fachen Liu, Jiaxin Liu, Ruilin Mao, Junfu Zhang, and 3 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6564445/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology dominates the semiconductor industry but faces fundamental limitations in high-temperature and high-power applications due to its low thermal conductivity and narrow bandgap. Heterogeneous integration with silicon carbide (SiC), a wide-bandgap semiconductor with superior thermal properties, offers a promising path forward. However, the substantial lattice mismatch between 4H-SiC and Si presents challenges for epitaxial growth, and hydrophilic direct bonding often results in the formation of an interfacial oxide layer that severely degrades interface thermal conductivity across the interface. Here, we report a surface activation bonding (SAB) strategy, combined with controlled post-bonding annealing, to fabricate high-quality 4H-SiC/Si heterostructures. Annealing at 1000°C significantly enhances the bonding strength and reduces the interfacial thermal resistance (ITR) by up to ~58% (from 12.140 m2K/MW to 5.079 m2K/MW), thereby substantially improving heat dissipation. Atomic-resolution electron microscopy reveals the absence of amorphous interlayers and the formation of 1–1.5 nm-thick 3C-SiC islands at the interface after annealing, both of them contribute to the enhanced thermal property. Sub-nanoscale phonon spectroscopy and atomistic simulations further clarify that these distinctive interfacial microstructures underpin the observed improvements in both mechanical and thermal performance. Our work not only achieves low ITR in 6-inch 4H-SiC/Si wafers but also provides atomic-scale insights into thermal interface engineering. Physical sciences/Materials science/Condensed-matter physics/Semiconductors Physical sciences/Materials science/Techniques and instrumentation/Microscopy/Transmission electron microscopy Physical sciences/Physics/Condensed-matter physics/Surfaces, interfaces and thin films Physical sciences/Physics/Statistical physics, thermodynamics and nonlinear dynamics/Thermodynamics Physical sciences/Materials science/Materials for devices/Electronic devices Full Text Additional Declarations There is NO Competing Interest. Supplementary Files SI.pdf Supplementary Material: Direct Bonding of 6-inch SiC/Si Wafer with Enhanced Thermal Interface Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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