Innovative Low Power SRAM Solutions: Memristor-Enhanced 4T2M and 6T2M Architectures with MTCMOS Techniques

Innovative Low Power SRAM Solutions: Memristor-Enhanced 4T2M and 6T2M Architectures with MTCMOS Techniques | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Innovative Low Power SRAM Solutions: Memristor-Enhanced 4T2M and 6T2M Architectures with MTCMOS Techniques Harshitha BR, Jalaja S This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4809268/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract In recent years, the demand for low-power devices has surged, driven by the scaling of CMOS technology, resulting in smaller chip sizes and higher transistor densities within System on Chip (SoC) designs, including memory components. This paper introduces the design and evaluation of Memristor-based SRAM, leveraging the unique properties of memristors to enhance power efficiency and processing speed. The integration of memristors reduces the transistor count, transitioning from traditional 6T SRAM to a 4T2M configuration and from 8T to 6T2M power usage. To further reduce power consumption, we implement the Multi-Threshold CMOS (MTCMOS) technique, known for minimizing leakage power by selectively deactivating inactive circuit domains. We perform a detailed analysis and parameterization of Memristor-based SRAM, including an MTCMOS-enhanced configuration, using the Cadence Virtuoso tool at a 90nm process technology with an operating voltage of 1.2 volts. This study addresses the pressing need for low-power memory solutions in modern electronic devices, focusing on the analysis and optimization of Memristor-based SRAM configurations. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Low-power SRAM Memristor 4T2M SRAM 6T2M SRAM MTCMOS CMOS technology power efficiency non-volatile memory Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 INTRODUCTION In VLSI design, memory plays a very important role. Memory, whether SRAM or DRAM, encounters challenges like operation speed, noise immunity, area, and power consumption [ 1 ]. Unlike DRAM, SRAM doesn't require periodic refreshing, enhancing energy efficiency. Studies show a preference for 6T SRAM over 4T due to its lower power consumption, higher noise margin, and reduced delay. To tackle SRAM's volatile nature, non-volatile techniques like FeRAM, MTJ RAM, MRAM, RRAM, and Phase Change RAM are explored. Memristors prove promising for data retention, offering non-volatility through resistance state changes. Widely adopted for their non-volatile features, memristors enhance memory retention even without power, making them ideal for non-volatile memory designs [ 2 ]. NVSRAM is valued for its non-volatile property, achieved through various techniques. Among Memristor models, the VTEAM model exhibits superior performance [ 4 ]. To address SRAM's volatility, a 4T2M NVSRAM proposal has been made, reducing the 6T SRAM configuration to 4T with the addition of 2 memristors. Memristors, acting as a fourth passive element. The Memristor comprises two terminals, positive and negative, both constructed with platinum electrodes [ 3 ]. The assignment of terminals is determined on the doping level of Titanium Dioxide (TiO2). Heavy doping of TiO2 determines one side as the positive terminal and the opposite side as the negative terminal. The concentration of doping can vary. When subjected to a high electric field, TiO2 dopants attempt to move in the direction of the current., [ 5 ] The application of voltage prompts oxygen atoms to drift either left or right, thereby modifying the material's thickness. Increased thickness denotes the High Resistance State (HRS), whereas decreased thickness indicates the Low Resistance State (LRS) [ 6 ]. The conventional 6T SRAM features two cross-coupled inverters, providing two stable states: '0' and '1'. This configuration supports both read and write operations. In a 6T SRAM cell, the inverter connects to the bit line and complementary line via access transistors. During the write operation, bit lines serve as input, and during the read operation, they serve as output. The word line, another control line, manages these phases. The schematic in Fig. 2 illustrates a conventional 6T SRAM using CMOS technology [ 7 ]. Figure 2 shows 6T SRAM, it can be analyzed in two modes of operations: Write Mode In write '1' operation, BL is set to '1' and BLB to '0'. The word line is then activated, allowing data from the bit line to be written. This written value is available at the output pins (Q and QB). During write '0', BL starts at '0', pulled down by pull-down transistors. Read Mode Bit lines are pre-charged to V DD /2 during reading. Depending on the stored value, BL is either pulled down to ground or pulled up to VDD by NMOS or PMOS transistors. A high ratio of pull-down transistor width to access transistor width ensures better read stability. This schematic operates with these principles, crucial for stable SRAM function in both read and write operations [ 7 ]. Figure 3 shows 8T SRAM, it refers to an SRAM cell design that utilizes eight transistors to store a single bit of data. The 8T configuration offers several advantages over traditional 6T SRAM cells, particularly in terms of read stability and write ability, which are critical for modern, low-power, and high-performance computing needs. The operation of an 8T SRAM cell ensures efficient and reliable read and write functions, leveraging its eight-transistor structure to improve stability and performance. Write Operation The write operation begins with the activation of the word line (WL), which turns on the two access transistors. This connects the bitlines (BL and BLB) to the storage nodes of the latch, consisting of two cross-coupled inverters. Data to be written is placed on the bitlines, with one bitline driven high (Vdd) and the other low (GND), representing binary data. This voltage difference overwrites existing data in the latch, and the access transistors transfer the bitline data to the storage nodes (Q and QB), completing the write operation. Read Operation The read operation minimizes disturbance to stored data by activating the read word line (RWL), which turns on both the read access and isolation transistors, creating a separate read path. The read bitline (RBL) is pre-charged to a high voltage. When RWL is activated, the state of the latch (Q or QB) determines the behavior of RBL. If Q is high (1), RBL discharges, indicating a logic '1'. If Q is low (0), RBL remains high, indicating a logic '0'. A sense amplifier amplifies the voltage difference on RBL to a recognizable logic level. METHODOLOGY Various models employed in Memristor design include the Linear Ion Drift Model, Non-Linear Ion Drift Model, Simmons Tunnel Barrier Model, Threshold Adaptive Memristor (TEAM) Model, and The Voltage Threshold Adaptive Memristor (VTEAM) Model. The VTEAM model stands out for its superior performance in achieving non-volatile properties, notably due to its enhanced SNM value in the Hysteresis curve. The mathematical expression utilized to formulate the VTEAM Model [ 8 ] is presented in Eq. ( 1 ). $$\:i\left(t\right)=[Ron+\frac{Roff-Ron}{woff-won}(w-woff\left)\right]$$ 1 This equation provides the I-V relation of the Memristor, with R ON and R OFF representing the resistance levels of the Memristor, while w off and won establish the boundary of the state variable w. 4T2M SRAM Conventional SRAM utilizes six transistors in its cell design. Among these, four transistors serve to latch flip-flops for storing each bit, while the remaining two function as access transistors [ 1 ]. This paper proposes a design featuring four transistors and two memristors for SRAM, depicted in Fig. 4 . In this configuration, the PMOS transistors of the 6T SRAM are replaced by two memristors, while the rest of the design mirrors that of the 6T SRAM. During write operations, when the word line is high, access transistors T1 and T2 are activated, facilitating data storage via nodes Q and QB (Q Bar) following BL (Bit Line) and BLB (Bit Line Bar). Depending on the stored data, the memristance of M1 and M2 is altered to either HRS (High Resistance State) or LRS (Low Resistance State), allowing for data storage. Conversely, when the word line is low, access transistors T1 and T2 are deactivated, preventing access to the SRAM cell and maintaining the contents of the linked transistors unchanged as long as the supply voltage is present. 6T2M SRAM In this implementation section, we present the design and implementation of a memristor-based SRAM cell, depicted in the accompanying 6T2M (6 Transistor, 2 Memristor) circuit diagram. This design integrates memristors into the traditional SRAM architecture, aiming to leverage the unique properties of memristors for enhanced performance, power efficiency, and data retention. The circuit comprises key components including memristors (M1 and M2), access transistors (NM3 and NM4), pull-down transistors (NM1 and NM0), and pull-up transistors (NM2 and NM5). The memristors serve as the core storage elements, utilizing their non-volatility and high-density storage capabilities. The access transistors control the read and write operations, activated by the word line signals (WWL and RWL). The pull-down and pull-up transistors form part of the cross-coupled inverters, maintaining data stability. During a write operation, the WWL activates NM3, allowing data to be written via the bit line WBL, adjusting the resistance state of M1 to store the data. Conversely, during a read operation, the RWL activates NM4, enabling the state of M2 to be sensed through WBLX, with the resulting current indicating the stored data value. This 6T2M design offers significant advantages such as non-volatility, high storage density, low power consumption, and improved performance. The non-volatile nature of memristors ensures data retention without power, while their nanoscale scalability allows for higher storage densities. Moreover, memristors reduce power consumption during write operations and do not require constant power to maintain data states, enhancing overall efficiency. The integration of memristors also facilitates faster read and write operations, further boosting performance. This implementation highlights the potential of memristor-based SRAM cells to revolutionize memory technology by combining traditional architectures with the innovative properties of memristors. Additionally, circuits continue to consume power even in idle mode. To address this, the MTCMOS technique was developed, introducing transistors with higher voltage threshold values that isolate lower threshold circuits from VDD and ground. This method employs two additional "sleep transistors"—one at the top and another at the bottom of the circuit, with complementary inputs. The upper transistor receives a sleep input, and the lower receives a sleep bar input, effectively disconnecting the low Vt logic from the power supply and significantly reducing subthreshold current flow during inactive modes. However, while MTCMOS reduces power consumption, it complicates timing alignment, especially in sequential circuits. Turning off sleep transistors can disrupt stored data due to clocking issues. Additionally, improper sizing of these transistors may lead to circuit malfunction. Therefore, careful consideration of transistor sizing and timing is crucial when implementing MTCMOS techniques. IMPLEMENTATIONS The SRAM 4T2M simulation was conducted using cadence virtuoso and is illustrated in Fig. 4 . This design integrates four NMOS transistors—T1, T2, T3, and T4—with two memristors, M1 and M2, forming a 4T2M cell. This cell revises the traditional 6T SRAM by substituting its two PMOS transistors with memristors, M1 and M2. These memristors are connected with a specific polarity to VDD, enhancing the cell's design and efficiency. T1 and T2 function as access transistors, facilitating the read/write operations, while T3 and T4, along with M1 and M2, comprise the memory component of the design. This 4T2M configuration not only optimizes the layout but also reduces power consumption by leveraging the unique properties of memristors. In the 6T2M configuration as seen in Fig. 8 , the SRAM cell uses six transistors and two memristors, combining the benefits of both technologies. The write operation starts with the activation of the word line (WL), turning on the access transistors. This connects the bitlines (BL and BLB) to the storage nodes, formed by memristors (M1 and M2) and transistors. Data is written by driving one bitline high (Vdd) and the other low (GND), altering the memristance states (HRS or LRS) for data storage. The read operation begins with the read word line (RWL) activation, turning on the read access and isolation transistors. This creates a separate read path, isolating the latch from the bitlines. The read bitline (RBL) is precharged, and its voltage state changes based on the stored data, which is then amplified by a sense amplifier. In the SRAM circuit utilizing the MTCMOS technique illustrates in Fig. 9 , power efficiency is optimized through the use of sleep transistors. The design features a PMOS transistor (PmosV1) at the top, linking the power supply (VDD) to the SRAM cell, and a transistor (NmosV1) at the bottom, connecting the cell to ground (VSS). These transistors are controlled by 'sleep' and 'sleep bar' signals, respectively. During active operation, the 'sleep' signal is low, activating PmosV1, and the 'sleep bar' is high, deactivating NmosV1, enabling normal cell operations. The SRAM cell, modified from the traditional 6T design shown in fig xxx, uses four NMOS transistors (N1, N2, N3, N4) and two memristors (M1, M2) which enhance data retention due to their non-volatile nature. In idle mode, 'sleep' is high and 'sleep bar' is low, effectively isolating the cell from VDD and minimizing leakage currents by grounding the cell. This strategic use of sleep transistors significantly reduces power consumption without sacrificing data integrity, showcasing a sophisticated application of MTCMOS technology in reducing energy consumption in memory circuits, suitable for energy-sensitive electronic devices. 6T2M (6 Transistor, 2 Memristor) SRAM cell integrated with Multi-Threshold CMOS (MTCMOS) technology, as depicted in Fig. 10 . This advanced design leverages memristors to enhance performance, power efficiency, and data retention. The circuit comprises key components, including memristors (M1 and M2) as primary storage elements, and access transistors (NM3 and NM4) controlled by word line signals (WWL and RWL) to manage read and write operations. Pull-down (NM1 and NM0) and pull-up transistors (NM2 and NM5) form cross-coupled inverters, ensuring data stability. During write operations, WWL activates NM3, allowing data on the bit line WBL to adjust M1’s resistance and store data. For read operations, RWL activates NM4, enabling the state of M2 to be sensed through WBLX, indicating the stored data. The integration of MTCMOS technology significantly reduces power consumption by using high-threshold voltage transistors to cut off power to inactive regions, minimizing leakage current. This 6T2M SRAM design with MTCMOS offers non-volatility, high storage density, low power consumption, and improved performance, showcasing the potential of combining memristor technology with MTCMOS for advanced memory applications. RESULTS AND DISSCUSSION The simulated waveform results for the 4T2M and 6T2M SRAM cells confirm their effective operation, including successful write and read operations, data retention during power-down, and accurate state restoration after power-up. These designs leverage the non-volatile properties of memristors, ensuring data integrity even when power is cycled. 4T2M SRAM Cell The waveform results from the simulation of the 4T2M SRAM cell demonstrate its functionality, including write operations, retention during power-down, and restoration after power-up. The waveforms for the write line (WL), power supply (VDD), bit line (B), complementary bit line (B_B), storage node (Q), and complementary storage node (Q_B) are shown in Fig. 11 . The WL signal is asserted during the write operations, enabling data writing to the storage nodes Q and Q_B. The VDD waveform is cycled between high (1.2V) and low (0V) to test the SRAM cell's retention capability during power-down and its ability to restore the state after power-up. During the write cycles, WL is high, and data is written to the cell with B set to high and B_B set to low, resulting in Q being set high and Q_B low. When the data inputs are inverted (B low and B_B high), Q is set low and Q_B high. During the power-down phase, VDD is set to 0V, and the states of Q and Q_B are retained. After power-up, where VDD is restored to 1.2V, Q and Q_B correctly return to their states before the power-down, demonstrating the non-volatile retention capability of the memristors integrated into the SRAM cell. 6T2M SRAM Cell The waveform results for the 6T2M SRAM cell demonstrate its functionality, including write operations, read operations, retention during power-down, and restoration after power-up. The waveforms for the write word line (WWL), power supply (VDD), bit line (WBL), complementary bit line (WBLB), read word line (RWL), read bit line (RBL), storage node (Q), and complementary storage node (Q_B) are shown in Fig. 12 . During the write cycles, WWL is asserted to enable data writing to Q and Q_B. The VDD waveform cycles between high (1.2V) and low (0V) to test the SRAM cell's retention capability during power-down and its ability to restore the state after power-up. Data is written with WBL set to high and WBLB set to low, resulting in Q being set high and Q_B low. When the data inputs are inverted, Q is set low and Q_B high. During the power-down phase, Q and Q_B retain their states. After power-up, Q and Q_B return to their states before power-down, demonstrating the non-volatile retention capability of the memristors. During the read operation, the read word line (RWL) is activated, and the state of the storage nodes (Q and Q_B) is sensed through the read bit line (RBL). If Q is high, RBL is discharged, indicating a logic '1'. If Q is low, RBL remains high, indicating a logic '0'. This ensures accurate state detection without disturbing the stored data. These results confirm the expected behavior of the 4T2M and 6T2M SRAM cells, showing successful write and read operations, state retention during power-down, and accurate state restoration after power-up. The memristor-based design effectively maintains data integrity, making it a viable solution for low-power, non-volatile memory applications. The Table 1 presents the power consumption metrics for various SRAM configurations, including traditional 6T, 6T2M from previous work, and our proposed 4T2M and 6T2M designs. The power consumption is measured in terms of write power and read power The traditional 6T SRAM configuration demonstrates a failure in write operations and a high read power of 176.36 µW. The 6T2M configuration from previous work [30] shows improved power efficiency, with Write power and Read power values of 0.930 µW and 0.803 µW, respectively. Our proposed designs, which incorporate Multi-Threshold CMOS (MTCMOS) techniques, show further improvements. The 4T2M configuration achieves a Write power of 0.152 µW and a Read power of 0.423 µW. The proposed 6T2M design exhibits the lowest power consumption, with Write power and Read power values of 0.123 µW and 0.392 µW, respectively. MTCMOS reduces leakage power by selectively deactivating inactive circuit domains, significantly lowering static power dissipation. This results in improved energy efficiency for the SRAM designs. Table 1 Power consumption metrics for SRAM configurations. Architecture Power in write-mode Power in read-mode 4T2M [12] 0.930 µW 0.803 µW 4T2M(proposed) 0.152 µW 0.423 µW 6T2M(proposed) 0.123 µW 0.392 µW CONCLUSION In this study, we have explored innovative low-power SRAM solutions by integrating memristors into traditional SRAM architectures and employing Multi-Threshold CMOS (MTCMOS) techniques. The proposed 4T2M and 6T2M SRAM designs demonstrate significant improvements in power efficiency compared to conventional SRAM configurations. Our results indicate that the proposed 4T2M configuration achieves a write power of 0.152 µW and a read power of 0.423 µW, while the proposed 6T2M configuration exhibits the lowest power consumption, with Power write and Power read values of 0.123 µW and 0.392 µW, respectively. These improvements are attributed to the unique properties of memristors, which enhance data retention and reduce static power dissipation, and the effective use of MTCMOS techniques, which minimize leakage power by selectively deactivating inactive circuit domains. The successful integration of memristors and MTCMOS techniques in SRAM designs paves the way for more energy-efficient memory solutions, addressing the growing demand for low-power devices in modern electronic applications. Future work could explore further optimizations and the implementation of these designs in larger memory arrays to validate their scalability and performance in real-world scenarios. References Pal S, Ranjan NS (2016) Design of Non-volatile SRAM Cell Using Memristor. In: Satapathy S, Mandal J, Udgata S, Bhateja V (eds) Information Systems Design and Intelligent Applications. Advances in Intelligent Systems and Computing, vol 435. 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IEEE Trans Very Large Scale Integr VLSI Syst, 19, 5 Additional Declarations There is NO Competing Interest. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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circuit\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image3.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/33721b2bcd4a5aa4a68eee86.jpeg"},{"id":62877414,"identity":"73dc0839-34db-457f-97a2-00467d3b93d9","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":25382,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eCircuit diagram of 4T2M SRAM.\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image4.png","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/b982126974a8c0e96f5d6c22.png"},{"id":62877413,"identity":"4f601e77-984d-4070-95c7-63039b636cfc","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":13097,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eCircuit diagram of 4T2M SRAM.\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image5.png","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/325c51fe3746c0ed52f0e9f2.png"},{"id":62877417,"identity":"6a482662-2309-41af-9e09-17629018ad53","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":20308,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eGeneral MTCMOS logic with CMOS and Memristor\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image6.png","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/f1c777dac6d0cc8d99b0b780.png"},{"id":62879083,"identity":"cc0d806b-0841-4edc-a5b1-d3c8d7a80d7d","added_by":"auto","created_at":"2024-08-20 14:28:00","extension":"jpeg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":109377,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eSchematic of 4T2M SRAM\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image7.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/caf89598a5af09bdd0171473.jpeg"},{"id":62878195,"identity":"481ba5fa-1b8a-4cd7-95c6-f1c07b8e1d58","added_by":"auto","created_at":"2024-08-20 14:20:00","extension":"jpeg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":187338,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eSchematic of 6T2M SRAM\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image8.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/5b8ffcb7092604d8e80d90cf.jpeg"},{"id":62877419,"identity":"2929347a-b178-4530-a7f0-c5a2baa46bd5","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"jpeg","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":146248,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eSchematic of 4T2M SRAM with MTCMOS\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image9.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/0167b43c79c1f74187952705.jpeg"},{"id":62877421,"identity":"2994dcf5-8c01-416b-a711-2fde242068d6","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"jpeg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":146334,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eSchematic of 6T2M SRAM with MTCMOS\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image10.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/c517a6f7f11f1260f4c6ef8e.jpeg"},{"id":62877422,"identity":"8d473236-77b1-4212-955f-008b954c0f72","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"jpeg","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":122163,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eTransient response of 4T2M SRAM cell\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image11.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/db7ce0c39f054d27d0986d27.jpeg"},{"id":62877424,"identity":"76cd6105-500e-40f7-861f-45d5c480e6ca","added_by":"auto","created_at":"2024-08-20 14:12:00","extension":"jpeg","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":138191,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eTransient response of 6T2M SRAM cell\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"image12.jpeg","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/e87dcb1f17636920cc74ec88.jpeg"},{"id":62880743,"identity":"90baa9f3-a8bd-4da6-bf24-7a8bffe7111c","added_by":"auto","created_at":"2024-08-20 14:44:03","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1454950,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4809268/v1/c7d176e5-31bb-45f2-bc22-2b199c37bbd7.pdf"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Innovative Low Power SRAM Solutions: Memristor-Enhanced 4T2M and 6T2M Architectures with MTCMOS Techniques","fulltext":[{"header":"INTRODUCTION ","content":"\u003cp\u003eIn VLSI design, memory plays a very important role. Memory, whether SRAM or DRAM, encounters challenges like operation speed, noise immunity, area, and power consumption [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Unlike DRAM, SRAM doesn't require periodic refreshing, enhancing energy efficiency. Studies show a preference for 6T SRAM over 4T due to its lower power consumption, higher noise margin, and reduced delay. To tackle SRAM's volatile nature, non-volatile techniques like FeRAM, MTJ RAM, MRAM, RRAM, and Phase Change RAM are explored. Memristors prove promising for data retention, offering non-volatility through resistance state changes. Widely adopted for their non-volatile features, memristors enhance memory retention even without power, making them ideal for non-volatile memory designs [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eNVSRAM is valued for its non-volatile property, achieved through various techniques. Among Memristor models, the VTEAM model exhibits superior performance [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. To address SRAM's volatility, a 4T2M NVSRAM proposal has been made, reducing the 6T SRAM configuration to 4T with the addition of 2 memristors. Memristors, acting as a fourth passive element. The Memristor comprises two terminals, positive and negative, both constructed with platinum electrodes [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. The assignment of terminals is determined on the doping level of Titanium Dioxide (TiO2). Heavy doping of TiO2 determines one side as the positive terminal and the opposite side as the negative terminal. The concentration of doping can vary. When subjected to a high electric field, TiO2 dopants attempt to move in the direction of the current., [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e] The application of voltage prompts oxygen atoms to drift either left or right, thereby modifying the material's thickness. Increased thickness denotes the High Resistance State (HRS), whereas decreased thickness indicates the Low Resistance State (LRS) [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe conventional 6T SRAM features two cross-coupled inverters, providing two stable states: '0' and '1'. This configuration supports both read and write operations. In a 6T SRAM cell, the inverter connects to the bit line and complementary line via access transistors. During the write operation, bit lines serve as input, and during the read operation, they serve as output. The word line, another control line, manages these phases. The schematic in Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e illustrates a conventional 6T SRAM using CMOS technology [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e shows 6T SRAM, it can be analyzed in two modes of operations:\u003c/p\u003e \u003cp\u003e \u003cstrong\u003eWrite Mode\u003c/strong\u003e \u003cp\u003eIn write '1' operation, BL is set to '1' and BLB to '0'. The word line is then activated, allowing data from the bit line to be written. This written value is available at the output pins (Q and QB). During write '0', BL starts at '0', pulled down by pull-down transistors.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003cstrong\u003eRead Mode\u003c/strong\u003e \u003cp\u003eBit lines are pre-charged to V\u003csub\u003eDD\u003c/sub\u003e/2 during reading. Depending on the stored value, BL is either pulled down to ground or pulled up to VDD by NMOS or PMOS transistors. A high ratio of pull-down transistor width to access transistor width ensures better read stability. This schematic operates with these principles, crucial for stable SRAM function in both read and write operations [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e].\u003c/p\u003e \u003c/p\u003e \u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e shows 8T SRAM, it refers to an SRAM cell design that utilizes eight transistors to store a single bit of data. The 8T configuration offers several advantages over traditional 6T SRAM cells, particularly in terms of read stability and write ability, which are critical for modern, low-power, and high-performance computing needs. The operation of an 8T SRAM cell ensures efficient and reliable read and write functions, leveraging its eight-transistor structure to improve stability and performance.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cstrong\u003eWrite Operation\u003c/strong\u003e \u003cp\u003eThe write operation begins with the activation of the word line (WL), which turns on the two access transistors. This connects the bitlines (BL and BLB) to the storage nodes of the latch, consisting of two cross-coupled inverters. Data to be written is placed on the bitlines, with one bitline driven high (Vdd) and the other low (GND), representing binary data. This voltage difference overwrites existing data in the latch, and the access transistors transfer the bitline data to the storage nodes (Q and QB), completing the write operation.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003cstrong\u003eRead Operation\u003c/strong\u003e \u003cp\u003eThe read operation minimizes disturbance to stored data by activating the read word line (RWL), which turns on both the read access and isolation transistors, creating a separate read path. The read bitline (RBL) is pre-charged to a high voltage. When RWL is activated, the state of the latch (Q or QB) determines the behavior of RBL. If Q is high (1), RBL discharges, indicating a logic '1'. If Q is low (0), RBL remains high, indicating a logic '0'. A sense amplifier amplifies the voltage difference on RBL to a recognizable logic level.\u003c/p\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"METHODOLOGY","content":"\u003cp\u003eVarious models employed in Memristor design include the Linear Ion Drift Model, Non-Linear Ion Drift Model, Simmons Tunnel Barrier Model, Threshold Adaptive Memristor (TEAM) Model, and The Voltage Threshold Adaptive Memristor (VTEAM) Model. The VTEAM model stands out for its superior performance in achieving non-volatile properties, notably due to its enhanced SNM value in the Hysteresis curve. The mathematical expression utilized to formulate the VTEAM Model [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e] is presented in Eq.\u0026nbsp;(\u003cspan refid=\"Equ1\" class=\"InternalRef\"\u003e1\u003c/span\u003e).\u003cdiv id=\"Equ1\" class=\"Equation\"\u003e\u003cdiv format=\"TEX\" class=\"mathdisplay\" id=\"FileID_Equ1\" name=\"EquationSource\"\u003e\n$$\\:i\\left(t\\right)=[Ron+\\frac{Roff-Ron}{woff-won}(w-woff\\left)\\right]$$\u003c/div\u003e\u003cdiv class=\"EquationNumber\"\u003e1\u003c/div\u003e\u003c/div\u003e\u003c/p\u003e \u003cp\u003eThis equation provides the I-V relation of the Memristor, with R\u003csub\u003eON\u003c/sub\u003e and R\u003csub\u003eOFF\u003c/sub\u003e representing the resistance levels of the Memristor, while w\u003csub\u003eoff\u003c/sub\u003e and won establish the boundary of the state variable w.\u003c/p\u003e \u003cp\u003e \u003cb\u003e4T2M SRAM\u003c/b\u003e \u003c/p\u003e \u003cp\u003eConventional SRAM utilizes six transistors in its cell design. Among these, four transistors serve to latch flip-flops for storing each bit, while the remaining two function as access transistors [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. This paper proposes a design featuring four transistors and two memristors for SRAM, depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. In this configuration, the PMOS transistors of the 6T SRAM are replaced by two memristors, while the rest of the design mirrors that of the 6T SRAM. During write operations, when the word line is high, access transistors T1 and T2 are activated, facilitating data storage via nodes Q and QB (Q Bar) following BL (Bit Line) and BLB (Bit Line Bar). Depending on the stored data, the memristance of M1 and M2 is altered to either HRS (High Resistance State) or LRS (Low Resistance State), allowing for data storage. Conversely, when the word line is low, access transistors T1 and T2 are deactivated, preventing access to the SRAM cell and maintaining the contents of the linked transistors unchanged as long as the supply voltage is present.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cb\u003e6T2M SRAM\u003c/b\u003e \u003c/p\u003e \u003cp\u003eIn this implementation section, we present the design and implementation of a memristor-based SRAM cell, depicted in the accompanying 6T2M (6 Transistor, 2 Memristor) circuit diagram. This design integrates memristors into the traditional SRAM architecture, aiming to leverage the unique properties of memristors for enhanced performance, power efficiency, and data retention. The circuit comprises key components including memristors (M1 and M2), access transistors (NM3 and NM4), pull-down transistors (NM1 and NM0), and pull-up transistors (NM2 and NM5). The memristors serve as the core storage elements, utilizing their non-volatility and high-density storage capabilities. The access transistors control the read and write operations, activated by the word line signals (WWL and RWL). The pull-down and pull-up transistors form part of the cross-coupled inverters, maintaining data stability. During a write operation, the WWL activates NM3, allowing data to be written via the bit line WBL, adjusting the resistance state of M1 to store the data. Conversely, during a read operation, the RWL activates NM4, enabling the state of M2 to be sensed through WBLX, with the resulting current indicating the stored data value. This 6T2M design offers significant advantages such as non-volatility, high storage density, low power consumption, and improved performance. The non-volatile nature of memristors ensures data retention without power, while their nanoscale scalability allows for higher storage densities. Moreover, memristors reduce power consumption during write operations and do not require constant power to maintain data states, enhancing overall efficiency. The integration of memristors also facilitates faster read and write operations, further boosting performance. This implementation highlights the potential of memristor-based SRAM cells to revolutionize memory technology by combining traditional architectures with the innovative properties of memristors.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eAdditionally, circuits continue to consume power even in idle mode. To address this, the MTCMOS technique was developed, introducing transistors with higher voltage threshold values that isolate lower threshold circuits from VDD and ground. This method employs two additional \"sleep transistors\"\u0026mdash;one at the top and another at the bottom of the circuit, with complementary inputs. The upper transistor receives a sleep input, and the lower receives a sleep bar input, effectively disconnecting the low Vt logic from the power supply and significantly reducing subthreshold current flow during inactive modes. However, while MTCMOS reduces power consumption, it complicates timing alignment, especially in sequential circuits. Turning off sleep transistors can disrupt stored data due to clocking issues. Additionally, improper sizing of these transistors may lead to circuit malfunction. Therefore, careful consideration of transistor sizing and timing is crucial when implementing MTCMOS techniques.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"IMPLEMENTATIONS ","content":"\u003cp\u003eThe SRAM 4T2M simulation was conducted using cadence virtuoso and is illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. This design integrates four NMOS transistors\u0026mdash;T1, T2, T3, and T4\u0026mdash;with two memristors, M1 and M2, forming a 4T2M cell. This cell revises the traditional 6T SRAM by substituting its two PMOS transistors with memristors, M1 and M2. These memristors are connected with a specific polarity to VDD, enhancing the cell's design and efficiency. T1 and T2 function as access transistors, facilitating the read/write operations, while T3 and T4, along with M1 and M2, comprise the memory component of the design. This 4T2M configuration not only optimizes the layout but also reduces power consumption by leveraging the unique properties of memristors.\u003c/p\u003e \u003cp\u003eIn the 6T2M configuration as seen in Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e8\u003c/span\u003e, the SRAM cell uses six transistors and two memristors, combining the benefits of both technologies.\u003c/p\u003e \u003cp\u003eThe write operation starts with the activation of the word line (WL), turning on the access transistors. This connects the bitlines (BL and BLB) to the storage nodes, formed by memristors (M1 and M2) and transistors. Data is written by driving one bitline high (Vdd) and the other low (GND), altering the memristance states (HRS or LRS) for data storage.\u003c/p\u003e \u003cp\u003eThe read operation begins with the read word line (RWL) activation, turning on the read access and isolation transistors. This creates a separate read path, isolating the latch from the bitlines. The read bitline (RBL) is precharged, and its voltage state changes based on the stored data, which is then amplified by a sense amplifier.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eIn the SRAM circuit utilizing the MTCMOS technique illustrates in Fig.\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e9\u003c/span\u003e, power efficiency is optimized through the use of sleep transistors. The design features a PMOS transistor (PmosV1) at the top, linking the power supply (VDD) to the SRAM cell, and a transistor (NmosV1) at the bottom, connecting the cell to ground (VSS). These transistors are controlled by 'sleep' and 'sleep bar' signals, respectively.\u003c/p\u003e \u003cp\u003eDuring active operation, the 'sleep' signal is low, activating PmosV1, and the 'sleep bar' is high, deactivating NmosV1, enabling normal cell operations. The SRAM cell, modified from the traditional 6T design shown in fig xxx, uses four NMOS transistors (N1, N2, N3, N4) and two memristors (M1, M2) which enhance data retention due to their non-volatile nature.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eIn idle mode, 'sleep' is high and 'sleep bar' is low, effectively isolating the cell from VDD and minimizing leakage currents by grounding the cell. This strategic use of sleep transistors significantly reduces power consumption without sacrificing data integrity, showcasing a sophisticated application of MTCMOS technology in reducing energy consumption in memory circuits, suitable for energy-sensitive electronic devices.\u003c/p\u003e \u003cp\u003e6T2M (6 Transistor, 2 Memristor) SRAM cell integrated with Multi-Threshold CMOS (MTCMOS) technology, as depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e10\u003c/span\u003e. This advanced design leverages memristors to enhance performance, power efficiency, and data retention. The circuit comprises key components, including memristors (M1 and M2) as primary storage elements, and access transistors (NM3 and NM4) controlled by word line signals (WWL and RWL) to manage read and write operations. Pull-down (NM1 and NM0) and pull-up transistors (NM2 and NM5) form cross-coupled inverters, ensuring data stability. During write operations, WWL activates NM3, allowing data on the bit line WBL to adjust M1\u0026rsquo;s resistance and store data. For read operations, RWL activates NM4, enabling the state of M2 to be sensed through WBLX, indicating the stored data. The integration of MTCMOS technology significantly reduces power consumption by using high-threshold voltage transistors to cut off power to inactive regions, minimizing leakage current. This 6T2M SRAM design with MTCMOS offers non-volatility, high storage density, low power consumption, and improved performance, showcasing the potential of combining memristor technology with MTCMOS for advanced memory applications.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"RESULTS AND DISSCUSSION","content":"\u003cp\u003eThe simulated waveform results for the 4T2M and 6T2M SRAM cells confirm their effective operation, including successful write and read operations, data retention during power-down, and accurate state restoration after power-up. These designs leverage the non-volatile properties of memristors, ensuring data integrity even when power is cycled.\u003c/p\u003e \u003cp\u003e \u003cb\u003e4T2M SRAM Cell\u003c/b\u003e \u003c/p\u003e \u003cp\u003eThe waveform results from the simulation of the 4T2M SRAM cell demonstrate its functionality, including write operations, retention during power-down, and restoration after power-up. The waveforms for the write line (WL), power supply (VDD), bit line (B), complementary bit line (B_B), storage node (Q), and complementary storage node (Q_B) are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig10\" class=\"InternalRef\"\u003e11\u003c/span\u003e. The WL signal is asserted during the write operations, enabling data writing to the storage nodes Q and Q_B. The VDD waveform is cycled between high (1.2V) and low (0V) to test the SRAM cell's retention capability during power-down and its ability to restore the state after power-up.\u003c/p\u003e \u003cp\u003eDuring the write cycles, WL is high, and data is written to the cell with B set to high and B_B set to low, resulting in Q being set high and Q_B low. When the data inputs are inverted (B low and B_B high), Q is set low and Q_B high. During the power-down phase, VDD is set to 0V, and the states of Q and Q_B are retained. After power-up, where VDD is restored to 1.2V, Q and Q_B correctly return to their states before the power-down, demonstrating the non-volatile retention capability of the memristors integrated into the SRAM cell.\u003c/p\u003e \u003cp\u003e \u003cb\u003e6T2M SRAM Cell\u003c/b\u003e \u003c/p\u003e \u003cp\u003eThe waveform results for the 6T2M SRAM cell demonstrate its functionality, including write operations, read operations, retention during power-down, and restoration after power-up. The waveforms for the write word line (WWL), power supply (VDD), bit line (WBL), complementary bit line (WBLB), read word line (RWL), read bit line (RBL), storage node (Q), and complementary storage node (Q_B) are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig11\" class=\"InternalRef\"\u003e12\u003c/span\u003e.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eDuring the write cycles, WWL is asserted to enable data writing to Q and Q_B. The VDD waveform cycles between high (1.2V) and low (0V) to test the SRAM cell's retention capability during power-down and its ability to restore the state after power-up. Data is written with WBL set to high and WBLB set to low, resulting in Q being set high and Q_B low. When the data inputs are inverted, Q is set low and Q_B high. During the power-down phase, Q and Q_B retain their states. After power-up, Q and Q_B return to their states before power-down, demonstrating the non-volatile retention capability of the memristors.\u003c/p\u003e \u003cp\u003eDuring the read operation, the read word line (RWL) is activated, and the state of the storage nodes (Q and Q_B) is sensed through the read bit line (RBL). If Q is high, RBL is discharged, indicating a logic '1'. If Q is low, RBL remains high, indicating a logic '0'. This ensures accurate state detection without disturbing the stored data.\u003c/p\u003e \u003cp\u003eThese results confirm the expected behavior of the 4T2M and 6T2M SRAM cells, showing successful write and read operations, state retention during power-down, and accurate state restoration after power-up. The memristor-based design effectively maintains data integrity, making it a viable solution for low-power, non-volatile memory applications.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eThe Table \u003cspan refid=\"Tab1\" class=\"InternalRef\"\u003e1\u003c/span\u003e presents the power consumption metrics for various SRAM configurations, including traditional 6T, 6T2M from previous work, and our proposed 4T2M and 6T2M designs. The power consumption is measured in terms of write power and read power The traditional 6T SRAM configuration demonstrates a failure in write operations and a high read power of 176.36 \u0026micro;W. The 6T2M configuration from previous work [30] shows improved power efficiency, with Write power and Read power values of 0.930 \u0026micro;W and 0.803 \u0026micro;W, respectively.\u003c/p\u003e \u003cp\u003eOur proposed designs, which incorporate Multi-Threshold CMOS (MTCMOS) techniques, show further improvements. The 4T2M configuration achieves a Write power of 0.152 \u0026micro;W and a Read power of 0.423 \u0026micro;W. The proposed 6T2M design exhibits the lowest power consumption, with Write power and Read power values of 0.123 \u0026micro;W and 0.392 \u0026micro;W, respectively.\u003c/p\u003e \u003cp\u003eMTCMOS reduces leakage power by selectively deactivating inactive circuit domains, significantly lowering static power dissipation. This results in improved energy efficiency for the SRAM designs.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab1\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003ePower consumption metrics for SRAM configurations.\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"3\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eArchitecture\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003ePower in write-mode\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003ePower in read-mode\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e4T2M [12]\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e0.930 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e0.803 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e4T2M(proposed)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e0.152 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e0.423 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e6T2M(proposed)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e0.123 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e0.392 \u0026micro;W\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e"},{"header":"CONCLUSION","content":"\u003cp\u003eIn this study, we have explored innovative low-power SRAM solutions by integrating memristors into traditional SRAM architectures and employing Multi-Threshold CMOS (MTCMOS) techniques. The proposed 4T2M and 6T2M SRAM designs demonstrate significant improvements in power efficiency compared to conventional SRAM configurations. Our results indicate that the proposed 4T2M configuration achieves a write power of 0.152 \u0026micro;W and a read power of 0.423 \u0026micro;W, while the proposed 6T2M configuration exhibits the lowest power consumption, with Power write and Power read values of 0.123 \u0026micro;W and 0.392 \u0026micro;W, respectively. These improvements are attributed to the unique properties of memristors, which enhance data retention and reduce static power dissipation, and the effective use of MTCMOS techniques, which minimize leakage power by selectively deactivating inactive circuit domains. The successful integration of memristors and MTCMOS techniques in SRAM designs paves the way for more energy-efficient memory solutions, addressing the growing demand for low-power devices in modern electronic applications. Future work could explore further optimizations and the implementation of these designs in larger memory arrays to validate their scalability and performance in real-world scenarios.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003ePal S, Ranjan NS (2016) Design of Non-volatile SRAM Cell Using Memristor. In: Satapathy S, Mandal J, Udgata S, Bhateja V (eds) Information Systems Design and Intelligent Applications. Advances in Intelligent Systems and Computing, vol 435. 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IEEE Trans Very Large Scale Integr VLSI Syst, 19, 5\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"Bangalore Institute of Technology","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Low-power SRAM, Memristor, 4T2M SRAM, 6T2M SRAM, MTCMOS, CMOS technology, power efficiency, non-volatile memory","lastPublishedDoi":"10.21203/rs.3.rs-4809268/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4809268/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn recent years, the demand for low-power devices has surged, driven by the scaling of CMOS technology, resulting in smaller chip sizes and higher transistor densities within System on Chip (SoC) designs, including memory components. This paper introduces the design and evaluation of Memristor-based SRAM, leveraging the unique properties of memristors to enhance power efficiency and processing speed. The integration of memristors reduces the transistor count, transitioning from traditional 6T SRAM to a 4T2M configuration and from 8T to 6T2M power usage. To further reduce power consumption, we implement the Multi-Threshold CMOS (MTCMOS) technique, known for minimizing leakage power by selectively deactivating inactive circuit domains. We perform a detailed analysis and parameterization of Memristor-based SRAM, including an MTCMOS-enhanced configuration, using the Cadence Virtuoso tool at a 90nm process technology with an operating voltage of 1.2 volts. This study addresses the pressing need for low-power memory solutions in modern electronic devices, focusing on the analysis and optimization of Memristor-based SRAM configurations.\u003c/p\u003e","manuscriptTitle":"Innovative Low Power SRAM Solutions: Memristor-Enhanced 4T2M and 6T2M Architectures with MTCMOS Techniques","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-08-20 14:11:55","doi":"10.21203/rs.3.rs-4809268/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"4cc10bd8-2758-46d5-89b4-ccd9c70b41ea","owner":[],"postedDate":"August 20th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[{"id":35701844,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":35701845,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices"}],"tags":[],"updatedAt":"2024-08-20T14:11:57+00:00","versionOfRecord":[],"versionCreatedAt":"2024-08-20 14:11:55","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-4809268","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4809268","identity":"rs-4809268","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}