Constraint-Aware Circuit-Level DAG Generation Using Full-Topology Enumeration

Constraint-Aware Circuit-Level DAG Generation Using Full-Topology Enumeration | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Constraint-Aware Circuit-Level DAG Generation Using Full-Topology Enumeration Dimitris Georgiou This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8634113/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Directed Acyclic Graphs (DAGs) serve as fundamen tal structural representations for combinational logic circuits, data flow graphs, and Boolean dependency networks. In recent years, the rapid application of machine learning (ML) techniques in logic synthesis, satisfiability (SAT) solving, and hardware secu rity has generated a strong demand for large-scale, structurally diverse circuit netlist datasets. However, existing circuit gener ators either suffer from insufficient diversity when rule-based or exhibit poor structural controllability and low topological space coverage when random-based. This paper proposes a fast and accurate random circuit netlist generator based on DAG theory and full topological enumeration principles. Inspired by the FT-DAG framework, this generator combines shape-driven DAGconstruction with circuit-specific constraints, including fixed input scale, precise internal fan-in, and controllable number of sink nodes. The framework addresses combinatorial explosion in the graph space through a hierarchical search strategy. Experimental results demonstrate high structural diversity, strict constraint satisfaction, and scalability, making it an ideal choice for data-intensive AI-driven EDA workflows. Electrical Engineering Directed acyclic graph circuit modeling topology enumeration logic synthesis EDA benchmarking Machine Learning Full Text Additional Declarations The authors declare no competing interests. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8634113","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":576453091,"identity":"b398893d-037d-43be-bb40-8824e7409d2d","order_by":0,"name":"Dimitris Georgiou","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAABJklEQVRIie3Rv0vDQBTA8RcyZDDqegVD/oUrgeIQzOi/4XFwU0DBJZMUHLLpGnHovxAJODk8OGiXiJt0FAqdHK60QwdBrzX+gjNdBe8LgbyQD7xcAGy2v5gEQADSTBRgt7l1+m0Ev5PO6lVsI9hcn1HcQHZGW0zO7vaT8PB8OFucxKwaczlXEAcleo/KQDpyu0ScEnZTD/n1HhXsdiwEQRBRif5pYSB0TZAcdYs0cgmVmqQ9vZhkmnDTYh8k6Q6e30lVHM8VwutG4gyIHzlKk5KkoBdDTTxpIutvqZGw0hfcBSqiop72SE15dCV913hiD/eVyvAsCXMpneVLHFzmfKKy7CC4GOWTX8652RABXP9rhNVIW0nY139v+fOZ99RKbDab7b/0Bv3fdOTpar7/AAAAAElFTkSuQmCC","orcid":"","institution":"","correspondingAuthor":true,"prefix":"","firstName":"Dimitris","middleName":"","lastName":"Georgiou","suffix":""}],"badges":[],"createdAt":"2026-01-19 01:49:18","currentVersionCode":1,"declarations":{"humanSubjects":false,"vertebrateSubjects":false,"conflictsOfInterestStatement":false,"humanSubjectEthicalGuidelines":false,"humanSubjectConsent":false,"humanSubjectClinicalTrial":false,"humanSubjectCaseReport":false,"vertebrateSubjectEthicalGuidelines":false},"doi":"10.21203/rs.3.rs-8634113/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8634113/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":100804053,"identity":"0e97810f-b0f6-4a76-b282-122839d827ec","added_by":"auto","created_at":"2026-01-21 14:35:33","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":544506,"visible":true,"origin":"","legend":"","description":"","filename":"IEEEJournalPaperTemplate.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8634113/v1_covered_9e47930f-ba0c-44b4-af0a-22f94bf98c17.pdf"}],"financialInterests":"The authors declare no competing interests.","formattedTitle":"\u003cp\u003eConstraint-Aware Circuit-Level DAG Generation Using Full-Topology Enumeration\u003c/p\u003e","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Directed acyclic graph, circuit modeling, topology enumeration, logic synthesis, EDA benchmarking, Machine Learning","lastPublishedDoi":"10.21203/rs.3.rs-8634113/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8634113/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eDirected Acyclic Graphs (DAGs) serve as fundamen tal structural representations for combinational logic circuits, data flow graphs, and Boolean dependency networks. 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