Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

Abstract Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm-1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).