Heat Management Strategy for Hybrid-Bonded Wafers using MgO Interlayer Dielectric

Heat Management Strategy for Hybrid-Bonded Wafers using MgO Interlayer Dielectric | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Heat Management Strategy for Hybrid-Bonded Wafers using MgO Interlayer Dielectric Anh-Duy Nguyen, Geon Park, Hyun Soo Kim, Rino Choi, An Nguyen, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6379463/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 7 You are reading this latest preprint version Abstract As the features of metal oxide semiconductor field-effect transistor (MOSFET) devices are aggressively scaled down, 3-dimensional (3D) integration is receiving significant attention for further development of semiconductor technology. While hybrid bonding is a promising solution for 3D integration because it can achieve high interconnect density, thermal management of bonded dies would be a potential problem. The thermal conductivity of the interlayer dielectric is crucial for effective thermal management. With high thermal conductivity and low fabrication temperature, magnesium oxide (MgO) is one of attractive dielectric interlayers. However, due to the high dielectric constant, crosstalk degradation is a major challenge for MgO implementation. This study proposes various strategies for MgO implementation. 2-dimensional technology computer-aided-design transient thermal simulation has been utilized to investigate MgO performance as an interlayer dielectric, while the finite element method has been used to study the tradeoff with crosstalk performance. The simulated results reveal that the device operating temperature can be reduced up to 7°C by applying a MgO layer in SiO 2 intermetal dielectric, with a thickness ratio ranging from 20–40%. MgO single-layer implementation as a heat-conducting channel has also been studied. M4, M5, or M6 are recommended for high thermal conductivity and low crosstalk tradeoff. This study demonstrates that an optimized usage of MgO layer in the back-end-of-line can minimize crosstalk degradation while maintaining heat dissipation enhancement. These results suggest that MgO interlayer can be an attractive solution to the local heating issue in high-performance applications. thermal conductivity BEOL dielectric thermal simulation TCAD simulation hybrid bonding Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 I. INTRODUCTION Complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) dissipate thermal energy during device operation as a result of the current flowing through the semiconductor channel and metal interconnect, also known as heat dissipation (HD) in CMOS [ 1 ]. Multiple studies and research have been conducted on the impact of the HD effect on device performance. It has been pointed out that temperature increase due to HD can cause serious degradation not only to transistor performance but also to device reliability and lifetime projections [ 2 ]. As the device dimensions have been aggressively scaled down, several challenges have been presented to IC power control. The leakage current during the off state significantly increases due to the short-channel effect, and the tunneling current through the gate dielectric drastically increases [ 3 ]. Recently, to overcome the physical limitation of traditional devices, novel structures and materials have been widely studied and implemented [ 4 ]. In those studies, the designs are usually complex, and device materials have low thermal conductivity [ 5 ]. These changes add complexities in thermal dissipation of ICs and exacerbate challenges in thermal management. Therefore, HD control in IC becomes one of the key obstacles for future IC development. Despite being recorded 40 years ago [ 6 ][ 7 ], HD continues to attract significant attention and research. Moreover, while today’s applications constantly demand more computing power and memory, the shrinking of device dimensions is facing physical barriers. This constraint leads to larger chips, which in turn increase the length of metal wiring and worsen signal integrity. Given this challenge, 3D integration offers a compelling alternative. By stacking up wafers or dices vertically, this method can significantly shorten signal paths and allow for greater device packing [ 8 ]. Among the various 3D integration techniques, hybrid bonding is a promising candidate, as it can achieve a fine interconnection pitch, thus providing high-bandwidth connections between wafers/dices [ 9 ]. However, like other 3D integration methods, hybrid bonded structures face serious difficulties in thermal management [ 8 ][ 10 ]. Increasing the number of device layers cannot contribute to a reduction in the thermal dissipated power per unit area. The limited space in hybrid bonded IC, coupled with intricate heat paths, can exacerbate the HD problem. Furthermore, for bonded interface, material thermal expansion is a major concern, causing stress on the metal-dielectric contacts and potentially resulting in reliability issues such as dielectric delamination or degradation in electrical performance [ 8 ][ 11 ][ 12 ]. Consequently, managing HD, a major hurdle in standard IC integration, is an even greater concern in hybrid-bonded assemblies. From the above reasons, simple and effective ways to manage thermal issues are highly desired. Multiple approaches have been explored, such as the introduction of dynamic thermal management to control power dissipation [ 13 ]. Mitigating heat dissipation can involve adopting measures such as reducing the clock frequency or operating voltage. However, this will inevitably result in a degradation of performance. An alternative approach is to use external heat sinks or heat spreaders to cool down the IC [ 14 ]. Nevertheless, the efficacy of this method is constrained by the intricate heat paths and the considerable distance from heat sources. The above methods further highlight the challenges in effectively improving the thermal performance of hybrid bonded structures without sacrificing performance, which is a main advantage of this technique. In general, to improve thermal management, one of the most effective ways is to improve the heat dissipation of the interconnect structure. This depends on the thermal conductance of the medium between heat sources to heat sinks [ 2 ]. This region is usually referred to as back-end-of-line (BEOL) layers. In these layers, this medium consists of metal wires and insulators. While metal wires already possess high thermal conductivity, the interlayer dielectric (ILD), commonly SiO 2 , has considerably lower heat dissipating capacity (~ 1.2 W/(m.K)) [ 15 ]. Hence, thermal resistance of the medium is generally subjected to thermal conductivity of the BEOL insulating materials. Other studies have shown that the reduction of thermal conductivity of ILD can lead to noticeable increases in BEOL structure, especially as this value decreases to around 1 W/(m.K) [ 16 ]. It is noteworthy that common materials for ILD have thermal conductivity around this range or even lower. For advanced BEOL structures, low-k dielectrics are commonly implemented as a solution for enhanced signal integrity. These materials have considerably smaller thermal conductivity, even in comparison to SiO 2 , as low as 0.3 W/(m.K) [ 17 ]. The integration of these materials into BEOL has been predicted to cause the temperature of the structure to rise up to 75% in comparison to common SiO 2 [ 16 ]. On the other hand, it has also been predicted that if ILD with thermal conductivity larger than 5 W/(m.K) is implemented instead of SiO 2 , 20% reduction in the BEOL increased temperature can be achieved. Therefore, a desired choice for BEOL insulators is a dielectric with high thermal conductivity, preferably one whose processing is compatible with the current CMOS process. Among various insulator materials, MgO is a well-studied dielectric that has been used in numerous applications [ 18 ]. Furthermore, high-quality thin film MgO can be fabricated through various techniques, especially with chemical vapor deposition at temperatures as low as 350 °C [ 19 ][ 20 ][ 21 ]. Notably, MgO possesses a significantly higher thermal conductivity compared to SiO 2 (33–42 W/(m.K) to 1.2 W/(m.K)) [ 22 ]. This makes MgO an attractive candidate for BEOL insulator. However, MgO is a relatively high-k dielectric with permittivity around 10. The incorporation of MgO in BEOL is expected to cause elevated interconnect parasitic capacitance and subsequent degradation in crosstalk. Therefore, different strategies of MgO implementation have been explored to find an optimal structure to improve thermal dissipation with minimized tradeoffs using electrical and thermal simulation in this study. Technology Computer-Aided Design (TCAD) is a powerful tool that has been widely used to investigate thermal performance and assess crosstalk situations under various conditions [ 23 ][ 24 ][ 25 ][ 26 ]. In this research, 2D TCAD simulation has been employed to examine the performance of MgO as a BEOL insulator and to analyze the necessary trade-off with crosstalk degradation, especially in hybrid bonded wafers and dices. Dedicated models for the proposed implementation schemes have been constructed and tested with thermal simulation and crosstalk evaluation. II. SIMULATION SETUP A. TCAD Thermal Simulation To study the effect of high thermal conductive MgO BEOL insulators in hybrid bonded wafers, an initial 2D model of the BEOL structure has been constructed in Synopsys Sentaurus TCAD. Fig. 1 (a) shows the model structure used for simulation. The model consists of two symmetrical parts to represent each bonded wafer. Each wafer has nine layers of BEOL, from M0 to M8 on 3 μm silicon substrates. The initial BEOL dielectric is implemented by SiO 2 . To focus on the effectiveness of thermal conduction of dielectric layers, thermal capacity values of SiO 2 and MgO are set to be identical even though MgO specific heat is larger than SiO 2 (~880 J/(kg.K) to 680 J/(kg.K)). Research on higher thermal capacity, which also contributes to lower model temperature, will be explored in another research. Beneath the silicon, another 2 μm packaging insulator was implemented. The heat sink is then located at the upper and lower boundaries of the model, where it is kept at room temperature. The metal lines and vias dimensions are referred to after guidance from other references [27], [28]. Copper has been designated as the material for metal lines and vias in M1 to M8, while tungsten has been selected for the metal via at M0. The hybrid bonded interface is deemed perfectly aligned as well as contacted for simulation simplicity. The side boundaries of the model are symmetrical and repeatable. To simplify the simulation, thermal heat sources are used instead of the CMOS devices. The heat power of the sources is referred to as CMOS power density. Varying the magnitude of heat source power, the heating rate and temperature of the model are monitored. Transient behavior has been recorded to observe the effect of MgO insulator on the heating and cooling of the model. The heat sources are applied in the form of one square pulse with a width of 1 μs at the contact points of M0 metal vias and silicon. Hot spots arise due to uneven heating power density. Consequently, to assess the influence of MgO on these hot spots and ensure model symmetry, only heat sources positioned in the center of the model are chosen to receive power. A temperature gradient from the local heated region to the boundaries of the volume is generated accordingly. Temperature variations throughout the model are recorded during and after the application of the heating pulse to monitor heating and cooling behaviors. The temperature at the heat source is consistently recorded during the simulation process and serves as the equivalent value for gate temperature in CMOS operation. Fig. 1 (b) shows the thermal distribution of the model, and Fig. 1 (c) illustrates the heating and cooling process of the device in the transient simulation. The temperature distribution is recorded at the end of the heating pulse, coinciding with the device reaching its maximum temperature. As depicted in the graph, the metal lines in direct contact with heat sources register higher temperatures than the surrounding volume. This is attributed to the lower thermal conductivity of SiO 2 in comparison to metal lines. After the TCAD model for a hybrid bonded wafer BEOL structure has been completed, MgO integrated models are built by replacing a certain SiO 2 BEOL dielectric with MgO dielectric. Two different schemes to replace SiO 2 with MgO dielectric are used in this work. Laminating stacks of two or more insulators has been investigated as a method to incorporate high-k dielectric into BEOL structure, especially in metal-insulator-metal capacitors for BEOL. Therefore, in this research, lamination of MgO and SiO 2 is investigated as a method to incorporate MgO into the BEOL structure. An ideal ratio between the MgO and SiO 2 is needed to balance thermal and electrical performance. Therefore, the first scheme is that some bottom parts of the SiO 2 dielectric layer in every BEOL layer is replaced with a MgO layer so that the BEOL layer is split into two sheets, MgO at the bottom and SiO 2 on top. Because the simulation is performed in 2D, the height ratio between two sheets represents the total volume ratio of MgO and SiO 2 in the mixture. M0 would be reserved for SiO 2, and the density ratio of metal interconnect to dielectric in this layer would be the highest to resemble the real device conditions. Because hybrid bonding has been studied intensively with the interface between copper and SiO 2 , the top dielectric layer of the M8 layer remains as SiO 2 . The layers of MgO are expected to become high thermal conductivity channels and improve thermal dissipation, while traditional SiO 2 layers help reduce crosstalk impact due to their low dielectric constant. In this research, each model would be named after the percentage of MgO in the mixture. For example, the model with 20 % of dielectric substituted for MgO would be named as 20% MgO. The ratio has increased from 0% to 80%, as shown in the Fig. 2. Another approach in MgO implementation is to subsequently change MgO to each BEOL dielectric layer to create high thermal conducting paths. However, as metal densities are different across BEOL layers, the above model needs to be adjusted to precisely study the impact of MgO on thermal and crosstalk performance. To simplify the simulation, the density of metal interconnect and dielectric has been kept constant in all layers. Furthermore, given that only a single layer is altered to MgO, the thermal behavior is more influenced by the proximity of the concerned layer to the heat sources. This means the symmetry of the structure is less important than in the first approach. Therefore, the model is changed to contain only one wafer with full BEOL layers. All the simulation conditions and parameters are kept unchanged. Like the first approach, the gate temperatures are extracted to analyze the effectiveness of MgO, as in Fig. 3. The models are named after which layer that was chosen to use MgO. For example, the model with MgO as M1 is referred to as M1-MgO. B. Crosstalk Simulation Finite element simulation (FEM) has been applied to evaluate the effect of MgO implementation on the degradation of crosstalk. The transmission line model (TLM) has been widely used as a simple and reliable method to estimate signal integrity and crosstalk impact in CMOS circuits [29][30][31]. Therefore, the Synopsys Sentaurus TCAD simulating tool has been utilized to generate a 2D TLM model with various metal thicknesses and pitches as demonstrated in Fig. 1. The model consists of two parallel metal lines buried in an insulator, of which the dielectric constant can be controlled. The capacitance per length (CL) and the mutual capacitance between two lines (CM) are then extracted using AC sweeping with 1 GHz frequency. The inductance matrix is then calculated by C 0 is the capacitance matrix if all the insulators are replaced by free space, ε 0 is vacuum permittivity, and μ 0 is vacuum permeability. From the inductance matrix, inductance per length (LL) and mutual inductance (LM) are obtained. To quantify crosstalk impact, Near-End Crosstalk Coefficient (NEXT) and Far-End Crosstalk Coefficient (FEXT) are used. The magnitude of FEXT and NEXT is derived from the parasitic matrices. L trace is the length of the coupled region of two metal traces, t rise is the rise time of the signal, and V is the signal transfer speed. In a CMOS integrated circuit, NEXT is generally more significant than FEXT [32]. Therefore, NEXT values would be used to compare crosstalk performance between different scenarios. III. RESULTS AND DISCUSSIONS A. MgO BEOL Dielectric Bilayer Integration Thermal simulations have been conducted using the models with inter-metal layers with various ratios of MgO to SiO 2, whose structures are depicted in Fig. 2. Fig. 4. (a) illustrates the transient changes in gate temperature during pulse application. The heating power was kept constant at 2.4 W/cm 2 . This heating power was selected to elevate the temperature of the model to the thermal operating limitation of conventional IC, specifically in the scenario where only SiO 2 is used as the BEOL dielectric. The gate temperatures were compared to the impact of MgO percentage. Without MgO interlayers, the temperature is rapidly raised to 168 °C with an average rate of 0.15 K/ns. The maximum temperature is lowered as the MgO ratio increases. The temperature rise in the initial stage is also lowered with the increase of the MgO ratio. Fig. 4. (b) provides the highest temperature of device regions under different heating pulses. The temperatures were collected with an interval of 1 μs and at various heating power densities (1.8-2.4 W/cm 2 ). With higher power density, the gate temperature is generally higher. Different power is used to represent various operating conditions of the hybrid bonded structure. The consistent trend is that models with MgO have reduced gate temperatures compared to the referenced model. The reduction is more significant as the gate temperature gets higher. This can be attributed to a larger temperature gradient generated by higher device power. The largest temperature reduction can reach up to 8 °C in the 80% MgO model at the highest power density. This suggests that MgO is effective in thermal dissipation, as expected. The temperature at the bonding interface is another important information, as well as the device temperature in hybrid bonded wafers. Fig. 5 shows the simulated results of temperatures at the interface recorded at the highest power density. As the MgO ratio increases, the temperature at the bonded interface decreases from 123 °C (0% MgO) to 115 °C (80% MgO). This would contribute to reducing the thermal stress during operation on the bonded interface and reduce degradation and risk of tearing, delaminating of copper and SiO 2 contact, and improve the reliability of the bonding [11]. The temperature of the metal lines connected to the heat source is also observed to be at a decreased temperature. This can reduce the thermal expansion of copper under operation and reduce physical stress on the metal [33]. To analyze the reason for temperature reduction by MgO, temperature distribution in the simulated models has been studied and compared. Fig. 6 illustrates the temperature profile when the gate temperature is at maximum at various MgO concentrations. Under operation, temperature at the heat sources increases and thermal energy is transferred throughout the models. This creates a temperature gradient from the heat sources to the model boundaries. Therefore, heat paths are expected to form, and thermal energy is conducted throughout the structure. In models without MgO layers, the temperature difference between the heat source and the boundary is bigger. This describes the local heating effect taking place. Due to the poor thermal conductivity of SiO 2 BEOL dielectric, thermal energy dissipation is less effective. When combined with the results of transient heating simulations, the elevated heating and slower cooling rates can also stem from similar underlying reasons. The temperature variation over the distance from the heat source is less drastic with MgO layers. As MgO percentage increases, a noticeable decrease in temperature of the metal lines in direct contact with heat sources is recorded. Moreover, in comparison to the scenario without MgO, the surrounding BEOL dielectric demonstrates a slightly higher temperature. At higher MgO percentages, the temperature increases in the BEOL dielectric is observed at locations more distant from heat sources. Under similar heat power, implementing MgO suggests an improved spread of thermal energy throughout the BEOL dielectric compared to the scenario with only SiO 2 . This evidently shows MgO has a positive impact on thermal conduction in the structure. The impact of MgO incorporation in BEOL has been investigated using 1 cycle of heating/cooling. However, as the BEOL structure is subjected to multiple heating cycles, the temperature of the structure has a tendency to rise until thermal equilibrium is achieved. It is of interest to check if the impact of MgO on BEOL cooling can still be achieved in this condition. Therefore, the models are subjected to multiple heating cycles. Due to the limitation of running time, 5 continuous cycles are used, as shown in Fig. 7. Fig. 7 (a) presents the transient gate temperatures at multiple MgO ratios. It can be observed that the temperature increases after each cycle. However, the increasing rate is slowed down at later cycles until the change in gate temperature between the 4 th and 5 th cycle is less than 5 %. It can be considered that 5 cycles are enough to observe the saturation of gate temperature. Furthermore, models with MgO at all tested ratios show reduced gate temperature in comparison to the SiO 2 -only model. The reduction increases as the MgO ratio becomes higher. Fig. 7 (b) shows the values for maximum gate temperature with models at 0/40/80 % MgO. It can be seen that there is a constant temperature reduction of 8 °C over every cycle when 80 % MgO is implemented. When 40 % MgO is used, the reduction is around 6 °C. This suggests that not only can MgO help to lower the temperature of the device, but this benefit still exists until the thermal equilibrium is reached. With the contribution of MgO to cooling the BEOL structure after multiple working cycles studied, there is a concern that the time for MgO to conduct heat from hot spot to heat sink between heating cycles reduces. To modify that concern, different heating frequencies of 5 and 10 MHz are applied to models with varied MgO ratios. The maximum gate temperatures after a certain heating time were recorded for both frequencies and the temperature. Fig. 8. (b)-(c) shows the transient gate temperature of 5 MHz and 10 MHz, respectively. Fig. 8. (a). presents the maximum temperature reduction over heating time when a 40 % MgO ratio is used. The reason for choosing a 40 % ratio is that at higher MgO percentages, the temperature reduction does not increase significantly. It can be observed that at higher frequencies, the reduction in temperature is diminished. This is because of the shortening of the cooling time, as expected. However, even when the frequency doubles, around 4.5 °C can still be recorded when 40 % MgO is used. This suggests that the effectiveness of MgO in the model is affected by the frequency, but there is still a benefit to have in using MgO in the BEOL. In this simulation, the heating power is applied continuously and with higher frequency; the resting time in between is shortened significantly. However, in real device operation, not all devices operate at the same time and continuously like this. Time for heat dissipation will depend on the function and power management. Therefore, it is reasonable to expect the contribution of MgO in BEOL cooling in real applications even at higher frequencies. Another investigated factor to determine the temperature under heating is the impact of the duty cycle. With different duty cycles, the ratio between heating and cooling time in one cycle is varied. Therefore, the impact of MgO incorporation should be considered as well. The initial models used a duty cycle of 50 %. Therefore, the models with different MgO percentages are subjected to heating with duty cycles of 25 % and 75 %. Fig. 9 (a) gives the transient thermal performance of the models in these conditions. It is obvious that at a higher duty cycle, the maximum temperature increases significantly. It is because of the longer heating time and diminished time to dissipate heat. However, an important thing to notice is that for all the tested duty cycles, the temperature reduction due to MgO is similar and around 8 °C. From the transient temperature curves, this can be explained by observing the reduction of gate temperature right after the power is stopped. It can be seen that the gate temperatures in models using MgO reduce rapidly and reach the level of the SiO 2 model in a short time. This time is much smaller than the varied time caused by different duty cycles. Therefore, unless the duty cycle is unreasonably high, MgO is expected to contribute to the cooling of devices. The crosstalk model is assessed in this scheme of MgO implementation. The dielectric in which the metal lines are embedded is adapted to a bilayer structure, similar to the thermal model. As an illustration, Fig. 10 (b) depicts the models to compute NEXT of dielectric layers with 50% MgO and 50% SiO 2 . Fig. 10 (a) represents the NEXT dependence on the relative thickness of the MgO layer. A higher ratio of MgO leads to linearly increased crosstalk across different metal pitches. Fig. 11 shows the device temperature reduction and NEXT changing over an increased percentage of MgO in the dielectric bilayer for BEOL. 2.4 W/cm 2 heating power for thermal simulation and 200 nm metal pitch for crosstalk are used. From 0 % up to 40 % MgO usage, the temperature reduces rapidly over 7 °C, while the decrease is slowed down from 40 % to 80 % MgO. Furthermore, the crosstalk coefficient has almost linearly increased. Therefore, the most optimized selection ratio for MgO mixture is proposed to be from 20 % to 40 %. At higher concentrations, the impact on device temperature is outweighed by the degradation of crosstalk performance. At 20% to 40%, the gate temperature can be reduced up to 7 °C while NEXT only increases by around 2%. Based on the simulated result, a mixture of 20% to 40% MgO and SiO 2 is proposed as a BEOL dielectric to reduce self-heating in hybrid bonded structures. B. MgO single BEOL layer Models with MgO substituted with individual BEOL layers from M1 to M8 have been studied and determine the most efficient level relative to the heat source to implement MgO. Fig. 12 shows the gate temperature variation with different implemented layers. The applied heating power is as in the first scheme. In the case of no MgO, the maximum gate temperature is 144 °C. With MgO implementation, the temperature can be reduced up to 4 °C (to 140 °C when M1 is changed to MgO). As MgO is considered in the higher BEOL layer, the temperature decrease is reduced. At M5 to M6, MgO can reduce the gate temperature by around 3 °C to 3.5 °C. Even as MgO is placed on M8, which is furthest away from the device layer, almost 2 °C is compared to the non-MgO model. In comparison with MgO dielectric bilayer integration, the effect of a single MgO layer is less pronounced. It can be attributed to the difference in total MgO volume. Nevertheless, it is well known that even a 1 or 2 °C reduction can still release significant needs for heat dissipation. Therefore, the effect of a single MgO layer on device temperature is still considerable. Crosstalk degradation is assessed in this model where one of the dielectric levels of the SiO 2 layer is replaced completely with MgO and NEXT. Fig. 13 shows the comparison of NEXT at different BEOL layers when MgO or SiO 2 is used. Crosstalk coefficients in the case of MgO replacing SiO 2 are generally 3% higher than when SiO 2 is implemented. Fig. 14 shows a tradeoff between the thermal performance and the impact on NEXT with different levels of MgO layer. In the case of MgO used as M1, M2, or M3 dielectric, the crosstalk situation would be significantly degraded. The NEXT coefficients are higher than 32% from M1 to M3. This can be attributed to the small metal pitches and high metal concentration in these layers. The crosstalk simulation also predicts that NEXT would relax considerably from M4 to above, quickly reducing from 30% to 18%. To achieve high effectiveness with MgO and balance with crosstalk tradeoff, the simulation has shown that M4, M5, and M6 are suitable candidates. The temperature reduction is expected to be from 3.5 °C to 4 °C, while NEXTs are expected to be lower than 30%. Therefore, strategically implementing MgO to a single BEOL layer can improve thermal performance while retaining control over crosstalk degradation. As mentioned above, to investigate the effect of MgO location on device temperature, the metal concentration was adjusted to be uniform in all layers. However, this also raises concern about the metal density effect on MgO contribution. As metal has high thermal conductivity, much greater than insulator in general, the increase in metal density can reduce the contribution of MgO. To address this concern, the effect of MgO in the BEOL structure with varied metal density needs to be investigated. Therefore, using the model built for this implementation scheme, the metal density in the BEOL structure is adjusted. The metal density after dummy filler in normal IC is around 50 %. In this research, a pessimistic situation will be assumed to check the effectiveness of MgO. Metal densities of 50/60/70 % were used in thermal simulation of BEOL with MgO implemented at different layers. Fig. 15. (b) illustrates varied metal density in the BEOL structure. Simulated gate temperatures are presented in Fig. 15. (a). As metal density increases, the device temperature tends to decrease. This is attributed to the impact of metal on thermal dissipation of BEOL structures. However, a clear temperature drop is noticed when MgO is implemented as above. Furthermore, this benefit can be seen at all metal densities. The temperature has the largest reduction when MgO is used in M1, M2 up to M6. At higher layers, the reduction gets smaller. One important thing that can be noticed is that the difference between the models with and without MgO is less significant at higher metal density. For example, at a metal density of 50 %, without MgO, the gate temperature is 155 °C at maximum, while it reduces to 152.5 °C when MgO is used at M8. That is 2.5 °C in difference. When the metal density is 70 %, the difference is only 1.5 °C. It suggests that the MgO effect is affected by metal density, as expected. However, the diminishing impact is noted at very high metal concentrations. At normal density, the contribution of MgO is considerable. IV. CONCLUSION MgO incorporation in the intermetal layer dielectric has been proposed as an innovative BEOL dielectric to mitigate the HD effect in hybrid bonded wafers/dices and traditional IC. Since the degraded crosstalk due to the high dielectric constant of MgO can be a trade-off, the structure and incorporation ratio would be optimized. Therefore, two MgO incorporation schemes have been studied to enhance HD capability and minimize the crosstalk impact. The first one is using double dielectric layers of MgO and SiO 2 with a specific ratio. The second one is to implement a single layer of BEOL MgO as a highly thermal conductive channel. A bilayer with MgO thickness ratio from 20–40% can reduce the device temperature up to 7 °C while avoiding the large increase in NEXT. As a single layer, it is recommended that MgO be used in M4, M5, or M6 to maximize the benefits of high thermal conductivity while keeping crosstalk degradation under control. From these simulated results, MgO is a promising solution for local heating and thermal reliability issues while minimizing signal integrity deterioration. Declarations Author Contribution Anh-Duy Nguyen: conceptualization, data curation, formal analysis, investigation, methodology, validation, visualization, and writing – original draft, An Hoang-Thuy Nguyen: conceptualization, data curation, formal analysis, investigation, methodology, validation, visualization, and first author equally contributed, Manh-Cuong Nguyen: data curation, formal analysis, validation, and visualization, G. Park: data curation, H. Kim: data curation, and R. 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(2020) 3–6. https://doi.org/10.1109/EDTM47692.2020.9117912. J.G. Massey, L. Luo, P. Smith, R. Wachnik, 2021 IEEE Microelectron. Des. Test Symp. MDTS 2021 (2021) 1–4. https://doi.org/10.1109/MDTS52103.2021.9476141. A.K. Sahoo, S. Frégonèse, M. Weis, N. Malbert, T. Zimmer, IEEE Trans. Electron Devices 59 (2012) 2619–2625. https://doi.org/10.1109/TED.2012.2209651. S. Tyagi, Proc. Int. Symp. Phys. Fail. Anal. Integr. Circuits, IPFA (2007) 10–15. https://doi.org/10.1109/IPFA.2007.4378049. K. Fischer, M. Agostinelli, C. Allen, D. Bahr, M. Bost, P. Charvat, V. Chikarmane, Q. Fu, C. Ganpule, M. Haran, M. Heckscher, H. Hiramatsu, E. Hwang, P. Jain, I. Jin, R. Kasim, S. Kosaraju, K.S. Lee, H. Liu, R. McFadden, S. Nigam, R. Patel, C. Pelto, P. Plekhanov, M. Prince, C. Puls, S. Rajamani, D. Rao, P. Reese, A. Rosenbaum, S. Sivakumar, B. Song, M. Uncuer, S. Williams, M. Yang, P. Yashar, S. Natarajan, 2015 IEEE Int. Interconnect Technol. Conf. 2015 IEEE Mater. Adv. Met. Conf. IITC/MAM 2015 (2015) 5–7. https://doi.org/10.1109/IITC-MAM.2015.7325600. J. Zhang, F. Liu, B. Li, Y. Huang, S. Chen, Y. Wang, J. Luo, J. Wan, IEEE Int. Reliab. Phys. Symp. Proc. 2022-March (2022) P181–P186. https://doi.org/10.1109/IRPS48227.2022.9764422. Y. Eo, W.R. Eisenstadt, J.Y. Jeong, O.K. Kwon, IEEE Trans. Electron Devices 47 (2000) 129140. S. Saini, A.M. Kumar, S. Veeramachaneni, M.B. Srinivas, IEEE Reg. 10 Annu. Int. Conf. Proceedings/TENCON (2009) 1–5. https://doi.org/10.1109/TENCON.2009.5396104. A. Vittal, L.H. Chen, M. Marek-sadowska, K. Wang, S. Yang, Short Papers, 18 (1999) 1817–1824. J. Zhang, M.O. Bloomfield, J.Q. Lu, R.J. Gutmann, T.S. Cale, Microelectron. Eng. 82 (2005) 534–547. https://doi.org/10.1016/j.mee.2005.07.053. Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 19 May, 2025 Reviews received at journal 19 May, 2025 Reviewers agreed at journal 09 May, 2025 Reviewers invited by journal 09 May, 2025 Editor assigned by journal 10 Apr, 2025 Submission checks completed at journal 08 Apr, 2025 First submitted to journal 04 Apr, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6379463","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":454214531,"identity":"3daf9d53-8666-4a78-8e47-4e0381075c28","order_by":0,"name":"Anh-Duy Nguyen","email":"","orcid":"","institution":"Inha University","correspondingAuthor":false,"prefix":"","firstName":"Anh-Duy","middleName":"","lastName":"Nguyen","suffix":""},{"id":454214532,"identity":"936efd03-887f-4e38-83a8-087045c7fc78","order_by":1,"name":"Geon Park","email":"","orcid":"","institution":"Inha University","correspondingAuthor":false,"prefix":"","firstName":"Geon","middleName":"","lastName":"Park","suffix":""},{"id":454214533,"identity":"3fbcf143-7a9c-47bd-9e43-c784cdad5924","order_by":2,"name":"Hyun Soo Kim","email":"","orcid":"","institution":"Inha University","correspondingAuthor":false,"prefix":"","firstName":"Hyun","middleName":"Soo","lastName":"Kim","suffix":""},{"id":454214534,"identity":"fc7ca307-25bf-4634-b07a-a9482e684c09","order_by":3,"name":"Rino Choi","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA0ElEQVRIiWNgGAWjYDACZjB5gIGNvbEBwmZgI1YLz0FitTBAtTBIJDAQp8W8nffgA4aaO3J8ko/bHhfUMMjzN7ClfcCnReYwX7IBw7FnxmzSie3GM44xGM44wHZ4Bj4tEsw8ZhKMDYcT26SBiIeNgXEDA3szXochtEgeBGr5x2BPghYJxjZp3jaGxA0MbIcJaTE2SDh22JiNB+gw3j6J5BmH2ZLxa+E/Y/jgQ81hOfn248+keb7Z2Pa3txnj1QIGCUhGwCJ3FIyCUTAKRgElAAAz2DnwnbyqSAAAAABJRU5ErkJggg==","orcid":"","institution":"Inha University","correspondingAuthor":true,"prefix":"","firstName":"Rino","middleName":"","lastName":"Choi","suffix":""},{"id":454214536,"identity":"479f71d9-f56d-40a8-8786-c9c112a20b3b","order_by":4,"name":"An Nguyen","email":"","orcid":"","institution":"3D Convergence Center at Inha University","correspondingAuthor":false,"prefix":"","firstName":"An","middleName":"","lastName":"Nguyen","suffix":""},{"id":454214537,"identity":"acd27adc-0d5e-400f-9144-ba141ff806fd","order_by":5,"name":"Cuong-Manh Nguyen","email":"","orcid":"","institution":"3D Convergence Center at Inha University","correspondingAuthor":false,"prefix":"","firstName":"Cuong-Manh","middleName":"","lastName":"Nguyen","suffix":""}],"badges":[],"createdAt":"2025-04-05 02:53:14","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6379463/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6379463/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":82643476,"identity":"395c024b-d32f-4bed-8a05-18edf69752cc","added_by":"auto","created_at":"2025-05-13 15:39:20","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":1066895,"visible":true,"origin":"","legend":"\u003cp\u003ea) Initial hybrid bonded BEOL model for thermal simulation, b) thermal distribution of the model under device operation, and c) gate temperature at the heated zone as recorded throughout the transient thermal simulation.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/c33eac22ee0ace506046f8c3.png"},{"id":82643484,"identity":"402022e7-7f74-42d0-a925-5553c8de8943","added_by":"auto","created_at":"2025-05-13 15:39:20","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":1138039,"visible":true,"origin":"","legend":"\u003cp\u003eBEOL models with different MgO ratios in BEOL dielectric mixtures.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/b1d1a7eb1bbef3fecf24d697.png"},{"id":82645318,"identity":"9bcd86be-58b8-4072-9011-d67f081bc954","added_by":"auto","created_at":"2025-05-13 15:55:20","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":901310,"visible":true,"origin":"","legend":"\u003cp\u003eBEOL models with single MgO integrated at different BEOL layers.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/8ac3e9c12fd8f1cb73dda1b5.png"},{"id":82644187,"identity":"bae42542-f690-4bf2-a6aa-75583471fc1d","added_by":"auto","created_at":"2025-05-13 15:47:20","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":855411,"visible":true,"origin":"","legend":"\u003cp\u003ea) Gate temperature over time in heating and cooling transient simulation. b) Maximum gate temperature recorded with different gate power density and various MgO ratio dielectric mixture.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/a428af9cfedb5d2fb74579ee.png"},{"id":82645821,"identity":"be114395-e6ca-4cba-95fa-38f8d9d72f30","added_by":"auto","created_at":"2025-05-13 16:03:20","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":355552,"visible":true,"origin":"","legend":"\u003cp\u003eThermal distribution in models with different MgO concentrations.\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/196c072ac0838fbc17b3559b.png"},{"id":82644184,"identity":"a35d5d7b-5b7e-41bf-83d0-37a83c90fa84","added_by":"auto","created_at":"2025-05-13 15:47:20","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":2191001,"visible":true,"origin":"","legend":"\u003cp\u003eThermal distribution in models with various MgO concentrations in the BEOL dielectric mixture.\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/abe4b0a7268849ae500322ff.png"},{"id":82643491,"identity":"c2bed11b-5765-4803-ae68-a6b5ab11118d","added_by":"auto","created_at":"2025-05-13 15:39:20","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":218097,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eGate temperature over 5 consecutive cycles. a) Transient dependence of gate temperature with multiple MgO ratios. b) Maximum recorded gate temperature with 0/40/80% MgO ratio.\u003c/strong\u003e\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/3d3ccb6ac9b5a9d275e84036.png"},{"id":82643480,"identity":"c8ae463b-0f8f-4457-9586-215fd82410c5","added_by":"auto","created_at":"2025-05-13 15:39:20","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":247497,"visible":true,"origin":"","legend":"\u003cp\u003eGate temperature over heating time with different power frequencies. a) Maximum gate temperature reduction over heating time when a 40 % MgO ratio is used. b) Transient gate temperature with power frequency of 5 MHz. c) Transient gate temperature with power frequency of 10 MHz.\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/b4158b476b66a1093180ed9a.png"},{"id":82643497,"identity":"b86e2977-1ebd-491c-ae19-9744a7cc7396","added_by":"auto","created_at":"2025-05-13 15:39:20","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":179189,"visible":true,"origin":"","legend":"\u003cp\u003eGate temperature under different heating duty cycles. a) Gate temperature over time in the heating and cooling transient simulation. b) Maximum gate temperature recorded with different gate power density and various MgO ratio dielectric mixture.\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/eb6f5337da79420140dfbc86.png"},{"id":82643502,"identity":"77a5c4f5-0eac-43f7-ac3a-d5164d12a0d3","added_by":"auto","created_at":"2025-05-13 15:39:21","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":366465,"visible":true,"origin":"","legend":"\u003cp\u003ea) NEXT coefficients with different MgO ratios and various metal pitches. b) 2D TLM model to estimate crosstalk with metal pitch at 200 nm and 50% MgO mixture as interlayer dielectric. c) Electrical potential distribution in the same model.\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/3e0ebfa18634550483d2f053.png"},{"id":82644236,"identity":"ba17716b-9f4f-46e2-8234-33e3860934eb","added_by":"auto","created_at":"2025-05-13 15:47:21","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":113829,"visible":true,"origin":"","legend":"\u003cp\u003eGate temperature over different MgO concentrations and respective crosstalk performance.\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/8f13520f651175081b9f368b.png"},{"id":82644192,"identity":"535d8656-e283-46aa-a498-d5465f3a7749","added_by":"auto","created_at":"2025-05-13 15:47:20","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":126690,"visible":true,"origin":"","legend":"\u003cp\u003eMaximum gate temperature with various heating powers and different MgO layer locations.\u003c/p\u003e","description":"","filename":"12.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/d5cd18b6d6408a19820a5680.png"},{"id":82644235,"identity":"9683f5e4-ca7e-499b-bf15-625a78fa7d54","added_by":"auto","created_at":"2025-05-13 15:47:20","extension":"png","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":85413,"visible":true,"origin":"","legend":"\u003cp\u003eCrosstalk coefficients at different layers with MgO and SiO2 as BEOL dielectric.\u003c/p\u003e","description":"","filename":"13.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/bbdafc1bc20a926feef64e1d.png"},{"id":82643527,"identity":"e770e6fa-a818-49df-89d5-8601f0ba09e9","added_by":"auto","created_at":"2025-05-13 15:39:22","extension":"png","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":138238,"visible":true,"origin":"","legend":"\u003cp\u003eGate temperature over different MgO implementing locations and respective crosstalk performance.\u003c/p\u003e","description":"","filename":"14.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/d4b95faf979181898bbb3663.png"},{"id":82643503,"identity":"83bee929-b668-429c-8686-dce916227089","added_by":"auto","created_at":"2025-05-13 15:39:21","extension":"png","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":219437,"visible":true,"origin":"","legend":"\u003cp\u003eCrosstalk coefficients at different layers with MgO and SiO\u003csub\u003e2\u003c/sub\u003e as BEOL dielectric.\u003c/p\u003e","description":"","filename":"15.png","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/e82d4d20eb8414294f0cef16.png"},{"id":82646622,"identity":"d2dbe27b-5b53-4d2d-bee5-5f934bbd50d4","added_by":"auto","created_at":"2025-05-13 16:11:23","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":8752161,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6379463/v1/055612db-d44a-413e-981b-23a0c078fcfd.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Heat Management Strategy for Hybrid-Bonded Wafers using MgO Interlayer Dielectric","fulltext":[{"header":"I. INTRODUCTION","content":"\u003cp\u003eComplementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) dissipate thermal energy during device operation as a result of the current flowing through the semiconductor channel and metal interconnect, also known as heat dissipation (HD) in CMOS [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. Multiple studies and research have been conducted on the impact of the HD effect on device performance. It has been pointed out that temperature increase due to HD can cause serious degradation not only to transistor performance but also to device reliability and lifetime projections [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. As the device dimensions have been aggressively scaled down, several challenges have been presented to IC power control. The leakage current during the off state significantly increases due to the short-channel effect, and the tunneling current through the gate dielectric drastically increases [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. Recently, to overcome the physical limitation of traditional devices, novel structures and materials have been widely studied and implemented [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. In those studies, the designs are usually complex, and device materials have low thermal conductivity [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. These changes add complexities in thermal dissipation of ICs and exacerbate challenges in thermal management. Therefore, HD control in IC becomes one of the key obstacles for future IC development. Despite being recorded 40 years ago [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e][\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], HD continues to attract significant attention and research.\u003c/p\u003e \u003cp\u003eMoreover, while today\u0026rsquo;s applications constantly demand more computing power and memory, the shrinking of device dimensions is facing physical barriers. This constraint leads to larger chips, which in turn increase the length of metal wiring and worsen signal integrity. Given this challenge, 3D integration offers a compelling alternative. By stacking up wafers or dices vertically, this method can significantly shorten signal paths and allow for greater device packing [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. Among the various 3D integration techniques, hybrid bonding is a promising candidate, as it can achieve a fine interconnection pitch, thus providing high-bandwidth connections between wafers/dices [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]. However, like other 3D integration methods, hybrid bonded structures face serious difficulties in thermal management [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e][\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. Increasing the number of device layers cannot contribute to a reduction in the thermal dissipated power per unit area. The limited space in hybrid bonded IC, coupled with intricate heat paths, can exacerbate the HD problem. Furthermore, for bonded interface, material thermal expansion is a major concern, causing stress on the metal-dielectric contacts and potentially resulting in reliability issues such as dielectric delamination or degradation in electrical performance [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e][\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e][\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. Consequently, managing HD, a major hurdle in standard IC integration, is an even greater concern in hybrid-bonded assemblies.\u003c/p\u003e \u003cp\u003eFrom the above reasons, simple and effective ways to manage thermal issues are highly desired. Multiple approaches have been explored, such as the introduction of dynamic thermal management to control power dissipation [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e]. Mitigating heat dissipation can involve adopting measures such as reducing the clock frequency or operating voltage. However, this will inevitably result in a degradation of performance. An alternative approach is to use external heat sinks or heat spreaders to cool down the IC [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. Nevertheless, the efficacy of this method is constrained by the intricate heat paths and the considerable distance from heat sources. The above methods further highlight the challenges in effectively improving the thermal performance of hybrid bonded structures without sacrificing performance, which is a main advantage of this technique.\u003c/p\u003e \u003cp\u003eIn general, to improve thermal management, one of the most effective ways is to improve the heat dissipation of the interconnect structure. This depends on the thermal conductance of the medium between heat sources to heat sinks [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. This region is usually referred to as back-end-of-line (BEOL) layers. In these layers, this medium consists of metal wires and insulators. While metal wires already possess high thermal conductivity, the interlayer dielectric (ILD), commonly SiO\u003csub\u003e2\u003c/sub\u003e, has considerably lower heat dissipating capacity (~\u0026thinsp;1.2 W/(m.K)) [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e]. Hence, thermal resistance of the medium is generally subjected to thermal conductivity of the BEOL insulating materials. Other studies have shown that the reduction of thermal conductivity of ILD can lead to noticeable increases in BEOL structure, especially as this value decreases to around 1 W/(m.K) [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]. It is noteworthy that common materials for ILD have thermal conductivity around this range or even lower. For advanced BEOL structures, low-k dielectrics are commonly implemented as a solution for enhanced signal integrity. These materials have considerably smaller thermal conductivity, even in comparison to SiO\u003csub\u003e2\u003c/sub\u003e, as low as 0.3 W/(m.K) [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e]. The integration of these materials into BEOL has been predicted to cause the temperature of the structure to rise up to 75% in comparison to common SiO\u003csub\u003e2\u003c/sub\u003e [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]. On the other hand, it has also been predicted that if ILD with thermal conductivity larger than 5 W/(m.K) is implemented instead of SiO\u003csub\u003e2\u003c/sub\u003e, 20% reduction in the BEOL increased temperature can be achieved. Therefore, a desired choice for BEOL insulators is a dielectric with high thermal conductivity, preferably one whose processing is compatible with the current CMOS process.\u003c/p\u003e \u003cp\u003eAmong various insulator materials, MgO is a well-studied dielectric that has been used in numerous applications [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e]. Furthermore, high-quality thin film MgO can be fabricated through various techniques, especially with chemical vapor deposition at temperatures as low as 350 \u0026deg;C [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e][\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e][\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e]. Notably, MgO possesses a significantly higher thermal conductivity compared to SiO\u003csub\u003e2\u003c/sub\u003e (33\u0026ndash;42 W/(m.K) to 1.2 W/(m.K)) [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e]. This makes MgO an attractive candidate for BEOL insulator. However, MgO is a relatively high-k dielectric with permittivity around 10. The incorporation of MgO in BEOL is expected to cause elevated interconnect parasitic capacitance and subsequent degradation in crosstalk. Therefore, different strategies of MgO implementation have been explored to find an optimal structure to improve thermal dissipation with minimized tradeoffs using electrical and thermal simulation in this study.\u003c/p\u003e \u003cp\u003eTechnology Computer-Aided Design (TCAD) is a powerful tool that has been widely used to investigate thermal performance and assess crosstalk situations under various conditions [\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e][\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e][\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e][\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e]. In this research, 2D TCAD simulation has been employed to examine the performance of MgO as a BEOL insulator and to analyze the necessary trade-off with crosstalk degradation, especially in hybrid bonded wafers and dices. Dedicated models for the proposed implementation schemes have been constructed and tested with thermal simulation and crosstalk evaluation.\u003c/p\u003e"},{"header":"II. SIMULATION SETUP","content":"\u003ch2\u003eA. TCAD Thermal Simulation\u003c/h2\u003e\n\u003cp\u003eTo study the effect of high thermal conductive MgO BEOL insulators in hybrid bonded wafers, an initial 2D model of the BEOL structure has been constructed in Synopsys Sentaurus TCAD. Fig. 1 (a) shows the model structure used for simulation. The model consists of two symmetrical parts to represent each bonded wafer. Each wafer has nine layers of BEOL, from M0 to M8 on 3 \u0026mu;m silicon substrates. The initial BEOL dielectric is implemented by SiO\u003csub\u003e2\u003c/sub\u003e.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eTo focus on the effectiveness of thermal conduction of dielectric layers, thermal capacity values of SiO\u003csub\u003e2\u003c/sub\u003e and MgO are set to be identical even though MgO specific heat is larger than SiO\u003csub\u003e2\u003c/sub\u003e (~880 J/(kg.K) to 680 J/(kg.K)). Research on higher thermal capacity, which also contributes to lower model temperature, will be explored in another research. Beneath the silicon, another 2 \u0026mu;m packaging insulator was implemented. The heat sink is then located at the upper and lower boundaries of the model, where it is kept at room temperature. The metal lines and vias dimensions are referred to after guidance from other references [27], [28]. Copper has been designated as the material for metal lines and vias in M1 to M8, while tungsten has been selected for the metal via at M0. The hybrid bonded interface is deemed perfectly aligned as well as contacted for simulation simplicity. The side boundaries of the model are symmetrical and repeatable.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eTo simplify the simulation, thermal heat sources are used instead of the CMOS devices. The heat power of the sources is referred to as CMOS power density. Varying the magnitude of heat source power, the heating rate and temperature of the model are monitored. Transient behavior has been recorded to observe the effect of MgO insulator on the heating and cooling of the model. The heat sources are applied in the form of one square pulse with a width of 1 \u0026mu;s at the contact points of M0 metal vias and silicon. Hot spots arise due to uneven heating power density. Consequently, to assess the influence of MgO on these hot spots and ensure model symmetry, only heat sources positioned in the center of the model are chosen to receive power. A temperature gradient from the local heated region to the boundaries of the volume is generated accordingly. Temperature variations throughout the model are recorded during and after the application of the heating pulse to monitor heating and cooling behaviors. The temperature at the heat source is consistently recorded during the simulation process and serves as the equivalent value for gate temperature in CMOS operation. Fig. 1 (b) shows the thermal distribution of the model, and Fig. 1 (c) illustrates the heating and cooling process of the device in the transient simulation. The temperature distribution is recorded at the end of the heating pulse, coinciding with the device reaching its maximum temperature. As depicted in the graph, the metal lines in direct contact with heat sources register higher temperatures than the surrounding volume. This is attributed to the lower thermal conductivity of SiO\u003csub\u003e2\u003c/sub\u003e in comparison to metal lines.\u003c/p\u003e\n\u003cp\u003eAfter the TCAD model for a hybrid bonded wafer BEOL structure has been completed, MgO integrated models are built by replacing a certain SiO\u003csub\u003e2\u003c/sub\u003e BEOL dielectric with MgO dielectric. Two different schemes to replace SiO\u003csub\u003e2\u003c/sub\u003e with MgO dielectric are used in this work. Laminating stacks of two or more insulators has been investigated as a method to incorporate high-k dielectric into BEOL structure, especially in metal-insulator-metal capacitors for BEOL. Therefore, in this research, lamination of MgO and SiO\u003csub\u003e2\u003c/sub\u003e is investigated as a method to incorporate MgO into the BEOL structure. An ideal ratio between the MgO and SiO\u003csub\u003e2\u003c/sub\u003e is needed to balance thermal and electrical performance. Therefore, the first scheme is that some bottom parts of the SiO\u003csub\u003e2\u003c/sub\u003e dielectric layer in every BEOL layer is replaced with a MgO layer so that the BEOL layer is split into two sheets, MgO at the bottom and SiO\u003csub\u003e2\u003c/sub\u003e on top. Because the simulation is performed in 2D, the height ratio between two sheets represents the total volume ratio of MgO and SiO\u003csub\u003e2\u003c/sub\u003e in the mixture. M0 would be reserved for SiO\u003csub\u003e2,\u003c/sub\u003e and the density ratio of metal interconnect to dielectric in this layer would be the highest to resemble the real device conditions. Because hybrid bonding has been studied intensively with the interface between copper and SiO\u003csub\u003e2\u003c/sub\u003e, the top dielectric layer of the M8 layer remains as SiO\u003csub\u003e2\u003c/sub\u003e. The layers of MgO are expected to become high thermal conductivity channels and improve thermal dissipation, while traditional SiO\u003csub\u003e2\u003c/sub\u003e layers help reduce crosstalk impact due to their low dielectric constant. In this research, each model would be named after the percentage of MgO in the mixture. For example, the model with 20 % of dielectric substituted for MgO would be named as 20% MgO. The ratio has increased from 0% to 80%, as shown in the Fig. 2.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eAnother approach in MgO implementation is to subsequently change MgO to each BEOL dielectric layer to create high thermal conducting paths. However, as metal densities are different across BEOL layers, the above model needs to be adjusted to precisely study the impact of MgO on thermal and crosstalk performance. To simplify the simulation, the density of metal interconnect and dielectric has been kept constant in all layers. Furthermore, given that only a single layer is altered to MgO, the thermal behavior is more influenced by the proximity of the concerned layer to the heat sources. This means the symmetry of the structure is less important than in the first approach. Therefore, the model is changed to contain only one wafer with full BEOL layers. All the simulation conditions and parameters are kept unchanged. Like the first approach, the gate temperatures are extracted to analyze the effectiveness of MgO, as in Fig. 3. The models are named after which layer that was chosen to use MgO. For example, the model with MgO as M1 is referred to as M1-MgO.\u0026nbsp;\u003c/p\u003e\n\u003ch2\u003eB. Crosstalk Simulation\u003c/h2\u003e\n\u003cp\u003eFinite element simulation (FEM) has been applied to evaluate the effect of MgO implementation on the degradation of crosstalk. The transmission line model (TLM) has been widely used as a simple and reliable method to estimate signal integrity and crosstalk impact in CMOS circuits [29][30][31]. Therefore, the Synopsys Sentaurus TCAD simulating tool has been utilized to generate a 2D TLM model with various metal thicknesses and pitches as demonstrated in Fig. 1. The model consists of two parallel metal lines buried in an insulator, of which the dielectric constant can be controlled. The capacitance per length (CL) and the mutual capacitance between two lines (CM) are then extracted using AC sweeping with 1 GHz frequency. The inductance matrix is then calculated by\u003c/p\u003e\n\u003cp\u003e\u003cimg width=\"347\" height=\"22\" src=\"data:image/png;base64,/9j/4AAQSkZJRgABAQEAYABgAAD/2wBDAAoHBwkHBgoJCAkLCwoMDxkQDw4ODx4WFxIZJCAmJSMgIyIoLTkwKCo2KyIjMkQyNjs9QEBAJjBGS0U+Sjk/QD3/wAALCAAWAVsBAREA/8QAHwAAAQUBAQEBAQEAAAAAAAAAAAECAwQFBgcICQoL/8QAtRAAAgEDAwIEAwUFBAQAAAF9AQIDAAQRBRIhMUEGE1FhByJxFDKBkaEII0KxwRVS0fAkM2JyggkKFhcYGRolJicoKSo0NTY3ODk6Q0RFRkdISUpTVFVWV1hZWmNkZWZnaGlqc3R1dnd4eXqDhIWGh4iJipKTlJWWl5iZmqKjpKWmp6ipqrKztLW2t7i5usLDxMXGx8jJytLT1NXW19jZ2uHi4+Tl5ufo6erx8vP09fb3+Pn6/9oACAEBAAA/APTrHV7m98R6lYLDCtvYGNWcsS7l0DcDGBjOOtJomtz65Y3k0Votu0FxJbx75NyyFDtLcDpkGpPD2rS6xYTSzxJFJDcy27CNiynY5XIyB1xWrRTZJEiQvI6og6sxwBQJEZ2RXUuuNyg8jPTIod1jQu7BVUZLE4AFNhniuIxJBKkiHoyMCPzFZd/q1zD4isdLtYYW+0QyTPJIxG0IVGAAOSd36U278QOLq9ttMsZL+WxTdcBXCAMRkRg85cjnHbIyea1YZXmtI5fLMbugby36qSOh+lYln4kl8nVWvrN2fT7kQFbJHmMmVVshQM/xfpVmx1ldcSeG2g1KydVH7y4s3i6n+HeME1H4Mup73wfpdxdyvNPJAGeRzyx9TW3RRRRRRRRRRRRRRRRRRRRRRRRSEgAknAHUmsiTxCieHbnWkt5JbWKNpowhG6RFGd3OAAcZHtU0+sJbWdpeTJttZ9gd8/6ovjbn2yQM+9aVclY3iad4g8Y3kv3IDBIfwgBpngfU7aDRdG0qNxPeTW7XNwY+RESdzbvQlnxjr19Ku+Cf+QZf/wDYTu//AEa1ZWs+F5L3V7m4HhPR7wSNnz5r90d+OpURnH51veFtMbStNkhbSrTTS0pbyrWcyqeB8xJVeeOmO1UfHlxEunadZ3DhYrzUYI5CemxW8xs+3yY/Gsqy1lor/WbuFDFd3+rQ2MfmxnMcYVVVyOM5+dgPen6rqk2paPDZ3oRZE1U28l0ykQL5Tb1aRfRgoG3OMnqKuXOoSWWLbRBZxPJaz6hLIkBCSuhUYC543E8nPalivP7R8YeHrwJs+0aVNLt9NxiOP1qLwtqUGk291bX5candarPvhCkuS8h2tj+7s2nd0wKs2XiK9n1a1ZvKNld3lzZrGF+aMxbsNnPOfLbP1FTeF/8AkM+Jv+wiP/RMdb9xBHdQPDMu6NxhhkjI+oqDTtMs9ItBa6fAsECnKxqTgfT0q3RRRRRRRRRRRRRRRRRRRRRRRRVDXoZrjw9qUNrnz5LWVY8ddxUgfrXP3VxCvwiL7gqNo4RfqYsBceueMUniR1uvhVP9nYO0tlHHEV5y52qoHvuxXWxBliQOcsFGT71m2mivZ6/f6jHdEpfFGkhaMcFUCjDfhWlKrtE6xOEcj5WK5wfXHeqGh6R/YtlJAZ2naWeS4dyoX5nYscAdua0qKp3OmQ3WpWV7I0gls9/lqD8p3jByO/HT60anpkOq2qwzF0KSLLHIhw0bqcqwzx1p2nafFptsYYSzbnaR3c5Z3Y5Zj7kmq2q6Fb6tKkskk0MixPCWhYAtG+NyHIPBwPcdjUVxoAOq6ffWdx9m+xQNbrF5YZSjFeOvH3BWxWRb+HLS1vzdxPLuWSSaKNiCkUkn32Axnnnqe5xjNP0bRm0qS/lkuTcTXs/nyNsCAHaq4A+iitSiiiiiiiiiiiiiiiiiiiiiiiiiiioLWzis1dIAVjZi4TspPJx6ZPOPeie0iuZImmBYRNvVT03DofqO1T1//9k=\" alt=\"image\"\u003e\u003c/p\u003e\n\u003cp\u003eC\u003csub\u003e0\u003c/sub\u003e is the capacitance matrix if all the insulators are replaced by free space, \u0026epsilon;\u003csub\u003e0\u003c/sub\u003e is vacuum permittivity, and \u0026mu;\u003csub\u003e0\u003c/sub\u003e is vacuum permeability. From the inductance matrix, inductance per length (LL) and mutual inductance (LM) are obtained. To quantify crosstalk impact, Near-End Crosstalk Coefficient (NEXT) and Far-End Crosstalk Coefficient (FEXT) are used. The magnitude of FEXT and NEXT is derived from the parasitic matrices.\u003c/p\u003e\n\u003cp\u003e\u003cimg width=\"308\" height=\"39\" src=\"data:image/png;base64,/9j/4AAQSkZJRgABAQEAYABgAAD/2wBDAAoHBwkHBgoJCAkLCwoMDxkQDw4ODx4WFxIZJCAmJSMgIyIoLTkwKCo2KyIjMkQyNjs9QEBAJjBGS0U+Sjk/QD3/wAALCAAnATQBAREA/8QAHwAAAQUBAQEBAQEAAAAAAAAAAAECAwQFBgcICQoL/8QAtRAAAgEDAwIEAwUFBAQAAAF9AQIDAAQRBRIhMUEGE1FhByJxFDKBkaEII0KxwRVS0fAkM2JyggkKFhcYGRolJicoKSo0NTY3ODk6Q0RFRkdISUpTVFVWV1hZWmNkZWZnaGlqc3R1dnd4eXqDhIWGh4iJipKTlJWWl5iZmqKjpKWmp6ipqrKztLW2t7i5usLDxMXGx8jJytLT1NXW19jZ2uHi4+Tl5ufo6erx8vP09fb3+Pn6/9oACAEBAAA/APZqKKKKKKq6jfJptjLcyRTSrGpbZEm5jgZ4/wDr0aZfJqelWl9GjIl1Ckyq3UBlBAP51Wh1J7rV7mGHYtpZDbPK38UhGdoPbaCCT7gdjUdhrsmpNazWunztYXJby7ksB8oBIcr1Ctjg9eRwM1r0UVm6fq5v9V1KzFuyLYSJGZS4IkZlDYA7YDDOfWtKs201GT+17jTbsKJlXz4GXgSRE4/NTwfqp71pUUUUUUUUUUUUUUUUUUUUUVWvtRtNNiSS+uI4I3cRq0hwCx6DPvTTqdmtzcW5uEE1tGJZk7oh6E+3B/KobXxBpd68aW15HI0kZlQDPzoMZYeo5HT1FMTxJpDw20y6hbmK5V3hfdxIqcuQfQd6IfEukXFwkEV/E0ruEVeQSxG4D6kcj2rUoqnq6zPpN1HbwtNLJEyKisFySCOpIFU9CE2leEbOPUITBJZWaJKpZW+4gBIIPTisvR9NuNR+GjQpII73VbSWZpD2kmBbJ/76A/CrM13e2OgyxSWg0+KK1SGKTzlLeafkULjIwCRyevpWb4f1PUtR1zTLW5u5FW0sZGuEYANcSK4j3sMdMhsYxnBPpXZSyxwRtJK6xxqMszHAH1NPrl9DTVNNEzXdiIRdXs91dzSTIVjjOdgGDknaqD0HNYtnrOrXTWFgb2VDcaishmOMvAyecI1OOcLkEjpwO9dB4of7FqGhaivBjvltnP8AsTAoR/31sP4V0VFFFFFFFFFFFFFFFFFFFFFcz4stYdcubLQZnAW5WaZxnkBUIU/gzgj/AHfasSHU7tfA2t6teq0V/MgswG4/eIoiyPbzC5+lbGnahYaFYXRn1NL2HT44o4zHEB5SlQBGpH3mYr0z6Zqr4PtYrfUtXsb+NBcwHckRbckNvL8/lr24bcD64HbFXPCCwapa3uqOElNzqUs0bMMlQn7pD7fKv61a8SQ38pt/sC6m2N2/7FPDH6Y3eZ174x703w3DqEUlx9vTVFBC7fts8Eg752+X0/Gr+pLqzNH/AGVNYxrg7/tMTuT6Y2sKztUGpf8ACH60dQls5ZTZzeWbWNlH+rPXcx5zU+mLdnwhpg0x7dJvssO0zoWTGwdgQf1qCVPEnypNd6D8x4D20nJ/7+VYtYNfW9SS7m0houknlW8iuV9AS5qh46XVD4fvjaS2S2n2c+Ys0Ts5OexDADt2rZsl1VbWYX8tk9wc+UYInVBxxuBYk8+hFZzL4m3eW15oe5h9020uSPp5lH2XxN8n7/Q/k+7/AKJL8v0/eVD48yPDcOceZ9vtMY9fPSumoooooooooooooooooorCs7y41q81dILhrdLScWkbKASGCqztg8E/NgZ4GM1nrc6np+hazdNeyXcWnyNLaTSgBpkRAXVsAAjO9Qcdvauotp0urWK4jzslQOufQjIqWikxilooorL1+4uobOOKzhndp5BG8kK7jCnVmx64GB7kHtWP4E2X/gS3tWt5Y4fKaLLjAcEnOOcnrjJq94KkdvCdjBN/r7NTaSj0aIlD/wCg5/Gs/Qrey1uyub7WVilmv72WONJjyixOVSNfQjZuOO5Jro9N1GLVLd5oUkVEleL5xjJRipI9sg/lVplDqVYAg9QRS1y80ts3jy4vbkxLDpOnKrSOB8jyuSef91B/3171uW+pRXWo3llGkoktNnmMV+U7hkAH6dayfFCG91DQtOXky3y3L+0cILn/AMe2D8a6KiiiiiiiiiiiiiiiiiisY6EyzamsFxLbw6iwld4SBJHJtCkrkEchR9Dn14jl8PynRrnTRqF1cR3SeS73BTMUeMEKFVRyMj/9VbUcawxJHGoVEAVQOwHSn0UUUUUUhAIIIyDUVraW9jAsFpBHBCucRxqFUZ9hVO30+Wy1m4ntyptbzDzRk4KSgAbh/vAAH3APc1P/AGZaLcNcxWtul0ckTeUNwYjBOev1qpoGk3Wj2cdtNeJPFFGFUJFty2SWckk8knp2rWoqlLoumzXDTy2Fq8zsGZ2iUliOhJxyRgYqpp+k3llqV1cNexvFc3DTughwx+UKq7sngBR25qa00+U6vcald7fNK+RAinIjiByfxY8n6KO1aVFFFFFFFFFFFFFFFFFFFFFf/9k=\" alt=\"image\"\u003e\u003c/p\u003e\n\u003cp\u003e\u003cimg width=\"305\" height=\"37\" src=\"data:image/png;base64,/9j/4AAQSkZJRgABAQEAYABgAAD/2wBDAAoHBwkHBgoJCAkLCwoMDxkQDw4ODx4WFxIZJCAmJSMgIyIoLTkwKCo2KyIjMkQyNjs9QEBAJjBGS0U+Sjk/QD3/wAALCAAlATEBAREA/8QAHwAAAQUBAQEBAQEAAAAAAAAAAAECAwQFBgcICQoL/8QAtRAAAgEDAwIEAwUFBAQAAAF9AQIDAAQRBRIhMUEGE1FhByJxFDKBkaEII0KxwRVS0fAkM2JyggkKFhcYGRolJicoKSo0NTY3ODk6Q0RFRkdISUpTVFVWV1hZWmNkZWZnaGlqc3R1dnd4eXqDhIWGh4iJipKTlJWWl5iZmqKjpKWmp6ipqrKztLW2t7i5usLDxMXGx8jJytLT1NXW19jZ2uHi4+Tl5ufo6erx8vP09fb3+Pn6/9oACAEBAAA/APZqKKKKKKyfDWqXGtaMl9cRxJ5sjiMRk4KBiqtz64z+Na1FFFFRzyPFCzxxGVwOEBAyfqaz/DervruhW+oSQiB5S4MatuC7XZevfpWpRWZrOoS25trOzKi9vXKREjIjUDLuR32j8yQO9QTatdTancabpUcUs1nCrzzTkhQ7AlE47kDJPYEdc1rW7StbRNcIqTFAZEU5CtjkA9+akorJ1TVLi01nSbG2jif7bJIJC5OURF3EjH4D8RWtWVrF/LpMtveM4NjvENypA/d7iAsgPsSAR6HPatWiiiiiiiiiiiiiqd9q1pp01tDcu4luWKwokTOXIGSBtB7An8KrnxHpq29vN50my5ma3iAgkLNIucrtxnPyt19DQ3iPTEtlnad1ja5FoMwuD5pONpGMg549KZL4p0mBple5bMDvHJiFztKDc/QdAOp6VZ07WLLVjKLOVnMQUuGjZCAwyp+YDqOavVX1CO4l0+4js2RLh42WJnztViOCcVzFxDq/h3wm8UctvDFaWMdvCYQXbzMhfMbIGAOuPqTV+C81BtSnhjuhNa21tFMz+R88jEtlR25VfwyKyrfxVqDQTTloXza28qp5TBYnlfacnuqDBY/Xp2sz6xqq6hb2FrPBMXQSi6eLasgMhXaBnnCg5Iz1XoK6vIGOevSjIzjPPpTZTIImMKq0mPlDHAJ9zg1keFNLvNF0KKwvjAzxM5DwsSCGdm7gY+9itkkDGT1oyM4zz6Vz1o3234gag5+7p9lFCo9GkZnY/kqVJFpOo2GpajNYy2pS/uUnZ5gxaMBVRlAHB4XjkYz3rmtZ1TUh/bbWdzcpBeFYoJgx227K/lMEPZmJB47AntXoEUYiiSMFmCKFyxyTj1Pen1g6jpmpyeIV1KzNmwhsnggWZ2G2R2BLHAOR8qjH1rH1TU9RsdaknhuJpUtrM21xtz5SSbPM80r0HAwPUnFa9hpj33gKKwvJ5biW6sdsksrFmZnXk5PuaseFNRfVfCml3spzLLbIZD6uBhv1BrXoooooooooooorldXhk1fxlbWcNxcWhtLCaVbiOPIEkhVBgkEZChjjrzUfiNg3iDSrU3U9rHaQTXBuFj34kIEadQQThnOOvFGtytqnh+DSbL7Qt1c2ouBczxsphCYZZG/2ywGB16ntUOp3EU/w1gS1t5YG1BI7cxmNi8ZkYCXdxngFySfTNdhHDFDny41TIAO0YzgYH6VyN/pOryX9w8VpfNG0jFSuvSRgjPGFC4X6dq6KG3vBoccMUv2a7EajfKxuNh75JIL/AF4ql/Z3iP8A6D1p/wCC3/7ZR/Z3iP8A6D1p/wCC3/7ZR/Z3iP8A6D1p/wCC3/7ZR/Z3iP8A6D1p/wCC3/7ZTvEkDS6JHCYprm+LqLd4BsKTdpM87AOSc54yOc4MPheC5tpr5NVR31UsrTXW0+XOvOzy+wUcjb1Byec5KSJq4vPs48TackzH5YTZDfjr08zJ4qItqgjmkPivSxHA22VjZriM+jHzeD9au61GJfDYjuI5b+dggja1Gxml/hdTk7MHndnAHrVXwxbXtre3aa4Gn1ZkUteKp8mWP+FU7Lg5yvUk7u/BoXHjTxSD18y2P4eSP8DVi7tdbjaWb+3rOC3DEgSWOdi54BbzBn61FBba7dRCS38SWEsZON0dgGH5iStN7fUTpawpfxLejGbg2+VPPPybvT3qvZWWtRXSPeavbXEAzujSy8snj+9vOPyqLVI9UhkluV12ysrMEYE9oDs7cuZB39qYth4hZQy6/ZlSMgjTuv8A5ErVsIruG2CX11HczZP7xIfLGPTbk/zrD+Hn/Ijab6ESEfQyNj9K6WiiiiiiiiiuY064n17wm2pE3jSXReRIrWURvtDEIisSMcAZORzn6VVtNZnt/DWg6i1xNPI9xHZ3XmrtZizmNgy/3lfv7H1rsaKKKKKKK5bxHLE/ivQ7We+ktYws0+Fk2+Yw2ooA/iOZDxWpN4j06O2uJUuFf7OG3jDABlwCCccckfnnpUx1myjneCa4SOWJS0oOdqYUMQW6cAg/Q1PZX9tqETSWsokVHKNwQVYdiDyOo/OrFFcXq0+iXPiGKxE9jam2vorq5feolln42Io6kn5cn0wO5xHY2aalr2vaMYlNr/aS3V5leHUxRFU99zAk+yn1rtwMDA6Utc8ifYPH8rHiPU7JcH1khY5H12yD/vk1Hq0qTeNNOtr51jsba1lvB5hAR5QyqM54O0Fj7ZB7VfstQsV1CGz0+AbLuFr7zYgAhBYfMe+WLZ6eta1Fc342aOfTLPTZSmNRvoYWDEcoG3v/AOOofzrQOv2rS2aWoa5FzcPbK0ZGFKBix56gbSOM81Jr9/8A2ZoF9d/xRQsUA/ibGFH4kgfjSeH9N/sfw9p+nnG62t0jYjuwAyfzzWjRRRRRRRRRWPbaAtvaCzjuJ4reKdpoPIkKMoYklDjquWOPw9Kkn0SGUWUCqEtLSUXAQE5dxkjP4nd7mtSiiiiiiimPDHI6O8aM6HKMRkr9PSsqTw9G+j3Nj57A3Fwbh5doyWMm/BHpwF+gqveeFEv2vjcXkhN4gRtiBQcMGUsBwxGAueDjIrW0+ySwtRCm0/MWYhduSep//Xk+9WqKrHTrNrjz2tLczZ3eYYxuz65xmpwiqWKqAWOWIHX606is3XLMXNkJ0fy7izb7RBJjO1gDkEdwQSpHoateVDfW0TXEEcgKhgrqGAJHvVCXRZm1p7+K+aJXSKIxrEOERi20HtuLHPtiteiop7WC5Ci4gilC9N6BsfnWZf6C1zd2s9ndCz+zRSRxqkKkKXxlh6EAcfU069tft+q2lrM5NvbAXJTvK4OEyfQH5vcgela1FFFFFFFFFFFFFf/Z\" alt=\"image\"\u003e\u003c/p\u003e\n\u003cp\u003eL\u003csub\u003etrace\u003c/sub\u003e is the length of the coupled region of two metal traces, t\u003csub\u003erise\u003c/sub\u003e is the rise time of the signal, and V is the signal transfer speed. In a CMOS integrated circuit, NEXT is generally more significant than FEXT [32]. Therefore, NEXT values would be used to compare crosstalk performance between different scenarios.\u003c/p\u003e"},{"header":"III. RESULTS AND DISCUSSIONS","content":"\u003ch2\u003eA. \u0026nbsp; MgO BEOL Dielectric Bilayer Integration\u003c/h2\u003e\n\u003cp\u003eThermal simulations have been conducted using the models with inter-metal layers with various ratios of MgO to SiO\u003csub\u003e2,\u003c/sub\u003e whose structures are depicted in Fig. 2. Fig. 4. (a) illustrates the transient changes in gate temperature during pulse application. The heating power was kept constant at 2.4 W/cm\u003csup\u003e2\u003c/sup\u003e. This heating power was selected to elevate the temperature of the model to the thermal operating limitation of conventional IC, specifically in the scenario where only SiO\u003csub\u003e2\u003c/sub\u003e is used as the BEOL dielectric. The gate temperatures were compared to the impact of MgO percentage. Without MgO interlayers, the temperature is rapidly raised to 168 \u0026deg;C with an average rate of 0.15 K/ns. The maximum temperature is lowered as the MgO ratio increases. The temperature rise in the initial stage is also lowered with the increase of the MgO ratio. Fig. 4. (b) provides the highest temperature of device regions under different heating pulses. The temperatures were collected with an interval of 1 \u0026mu;s and at various heating power densities (1.8-2.4 W/cm\u003csup\u003e2\u003c/sup\u003e). With higher power density, the gate temperature is generally higher. Different power is used to represent various operating conditions of the hybrid bonded structure. The consistent trend is that models with MgO have reduced gate temperatures compared to the referenced model. The reduction is more significant as the gate temperature gets higher. This can be attributed to a larger temperature gradient generated by higher device power. The largest temperature reduction can reach up to 8 \u0026deg;C in the 80% MgO model at the highest power density. This suggests that MgO is effective in thermal dissipation, as expected.\u003c/p\u003e\n\u003cp\u003eThe temperature at the bonding interface is another important information, as well as the device temperature in hybrid bonded wafers. Fig. 5 shows the simulated results of temperatures at the interface recorded at the highest power density. As the MgO ratio increases, the temperature at the bonded interface decreases from 123 \u0026deg;C (0% MgO) to 115 \u0026deg;C (80% MgO). This would contribute to reducing the thermal stress during operation on the bonded interface and reduce degradation and risk of tearing, delaminating of copper and SiO\u003csub\u003e2\u003c/sub\u003e contact, and improve the reliability of the bonding [11]. The temperature of the metal lines connected to the heat source is also observed to be at a decreased temperature. This can reduce the thermal expansion of copper under operation and reduce physical stress on the metal [33].\u003c/p\u003e\n\u003cp\u003eTo analyze the reason for temperature reduction by MgO, temperature distribution in the simulated models has been studied and compared. Fig. 6 illustrates the temperature profile when the gate temperature is at maximum at various MgO concentrations. Under operation, temperature at the heat sources increases and thermal energy is transferred throughout the models. This creates a temperature gradient from the heat sources to the model boundaries. Therefore, heat paths are expected to form, and thermal energy is conducted throughout the structure. In models without MgO layers, the temperature difference between the heat source and the boundary is bigger. This describes the local heating effect taking place. Due to the poor thermal conductivity of SiO\u003csub\u003e2\u003c/sub\u003e BEOL dielectric, thermal energy dissipation is less effective. When combined with the results of transient heating simulations, the elevated heating and slower cooling rates can also stem from similar underlying reasons. The temperature variation over the distance from the heat source is less drastic with MgO layers. As MgO percentage increases, a noticeable decrease in temperature of the metal lines in direct contact with heat sources is recorded. Moreover, in comparison to the scenario without MgO, the surrounding BEOL dielectric demonstrates a slightly higher temperature. At higher MgO percentages, the temperature increases in the BEOL dielectric is observed at locations more distant from heat sources. Under similar heat power, implementing MgO suggests an improved spread of thermal energy throughout the BEOL dielectric compared to the scenario with only SiO\u003csub\u003e2\u003c/sub\u003e. This evidently shows MgO has a positive impact on thermal conduction in the structure.\u003c/p\u003e\n\u003cp\u003eThe impact of MgO incorporation in BEOL has been investigated using 1 cycle of heating/cooling. However, as the BEOL structure is subjected to multiple heating cycles, the temperature of the structure has a tendency to rise until thermal equilibrium is achieved. It is of interest to check if the impact of MgO on BEOL cooling can still be achieved in this condition. Therefore, the models are subjected to multiple heating cycles. Due to the limitation of running time, 5 continuous cycles are used, as shown in Fig. 7. Fig. 7 (a) presents the transient gate temperatures at multiple MgO ratios. It can be observed that the temperature increases after each cycle. However, the increasing rate is slowed down at later cycles until the change in gate temperature between the 4\u003csup\u003eth\u003c/sup\u003e and 5\u003csup\u003eth\u003c/sup\u003e cycle is less than 5 %. It can be considered that 5 cycles are enough to observe the saturation of gate temperature. Furthermore, models with MgO at all tested ratios show reduced gate temperature in comparison to the SiO\u003csub\u003e2\u003c/sub\u003e-only model. The reduction increases as the MgO ratio becomes higher. Fig. 7 (b) shows the values for maximum gate temperature with models at 0/40/80 % MgO. It can be seen that there is a constant temperature reduction of 8 \u0026deg;C over every cycle when 80 % MgO is implemented. When 40 % MgO is used, the reduction is around 6 \u0026deg;C. This suggests that not only can MgO help to lower the temperature of the device, but this benefit still exists until the thermal equilibrium is reached.\u003c/p\u003e\n\u003cp\u003eWith the contribution of MgO to cooling the BEOL structure after multiple working cycles studied, there is a concern that the time for MgO to conduct heat from hot spot to heat sink between heating cycles reduces. To modify that concern, different heating frequencies of 5 and 10 MHz are applied to models with varied MgO ratios. The maximum gate temperatures after a certain heating time were recorded for both frequencies and the temperature. Fig. 8. (b)-(c) shows the transient gate temperature of 5 MHz and 10 MHz, respectively. Fig. 8. (a). presents the maximum temperature reduction over heating time when a 40 % MgO ratio is used. The reason for choosing a 40 % ratio is that at higher MgO percentages, the temperature reduction does not increase significantly. It can be observed that at higher frequencies, the reduction in temperature is diminished. This is because of the shortening of the cooling time, as expected. However, even when the frequency doubles, around 4.5 \u0026deg;C can still be recorded when 40 % MgO is used. This suggests that the effectiveness of MgO in the model is affected by the frequency, but there is still a benefit to have in using MgO in the BEOL. In this simulation, the heating power is applied continuously and with higher frequency; the resting time in between is shortened significantly. However, in real device operation, not all devices operate at the same time and continuously like this. Time for heat dissipation will depend on the function and power management. Therefore, it is reasonable to expect the contribution of MgO in BEOL cooling in real applications even at higher frequencies.\u003c/p\u003e\n\u003cp\u003eAnother investigated factor to determine the temperature under heating is the impact of the duty cycle. With different duty cycles, the ratio between heating and cooling time in one cycle is varied. Therefore, the impact of MgO incorporation should be considered as well. The initial models used a duty cycle of 50 %. Therefore, the models with different MgO percentages are subjected to heating with duty cycles of 25 % and 75 %. Fig. 9 (a) gives the transient thermal performance of the models in these conditions. It is obvious that at a higher duty cycle, the maximum temperature increases significantly. It is because of the longer heating time and diminished time to dissipate heat. However, an important thing to notice is that for all the tested duty cycles, the temperature reduction due to MgO is similar and around 8\u0026nbsp;\u0026deg;C. From the transient temperature curves, this can be explained by observing the reduction of gate temperature right after the power is stopped. It can be seen that the gate temperatures in models using MgO reduce rapidly and reach the level of the SiO\u003csub\u003e2\u003c/sub\u003e model in a short time. This time is much smaller than the varied time caused by different duty cycles. Therefore, unless the duty cycle is unreasonably high, MgO is expected to contribute to the cooling of devices.\u003c/p\u003e\n\u003cp\u003eThe crosstalk model is assessed in this scheme of MgO implementation. The dielectric in which the metal lines are embedded is adapted to a bilayer structure, similar to the thermal model. As an illustration, Fig. 10 (b) depicts the models to compute NEXT of dielectric layers with 50% MgO and 50% SiO\u003csub\u003e2\u003c/sub\u003e. Fig. 10 (a) represents the NEXT dependence on the relative thickness of the MgO layer. A higher ratio of MgO leads to linearly increased crosstalk across different metal pitches.\u003c/p\u003e\n\u003cp\u003eFig. 11 shows the device temperature reduction and NEXT changing over an increased percentage of MgO in the dielectric bilayer for BEOL. 2.4 W/cm\u003csup\u003e2\u003c/sup\u003e heating power for thermal simulation and 200 nm metal pitch for crosstalk are used. From 0 % up to 40 % MgO usage, the temperature reduces rapidly over 7 \u0026deg;C, while the decrease is slowed down from 40 % to 80 % MgO. Furthermore, the crosstalk coefficient has almost linearly increased. Therefore, the most optimized selection ratio for MgO mixture is proposed to be from 20 % to 40 %. At higher concentrations, the impact on device temperature is outweighed by the degradation of crosstalk performance. At 20% to 40%, the gate temperature can be reduced up to 7 \u0026deg;C while NEXT only increases by around 2%. Based on the simulated result, a mixture of 20% to 40% MgO and SiO\u003csub\u003e2\u003c/sub\u003e is proposed as a BEOL dielectric to reduce self-heating in hybrid bonded structures.\u003c/p\u003e\n\u003ch2\u003eB.\u0026nbsp; \u0026nbsp;MgO single BEOL layer\u003c/h2\u003e\n\u003cp\u003eModels with MgO substituted with individual BEOL layers from M1 to M8 have been studied and determine the most efficient level relative to the heat source to implement MgO. Fig. 12 shows the gate temperature variation with different implemented layers. The applied heating power is as in the first scheme. In the case of no MgO, the maximum gate temperature is 144 \u0026deg;C. With MgO implementation, the temperature can be reduced up to 4 \u0026deg;C (to 140 \u0026deg;C when M1 is changed to MgO). As MgO is considered in the higher BEOL layer, the temperature decrease is reduced. At M5 to M6, MgO can reduce the gate temperature by around 3 \u0026deg;C to 3.5 \u0026deg;C. Even as MgO is placed on M8, which is furthest away from the device layer, almost 2 \u0026deg;C is compared to the non-MgO model. In comparison with MgO dielectric bilayer integration, the effect of a single MgO layer is less pronounced. It can be attributed to the difference in total MgO volume. Nevertheless, it is well known that even a 1 or 2 \u0026deg;C reduction can still release significant needs for heat dissipation. Therefore, the effect of a single MgO layer on device temperature is still considerable.\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eCrosstalk degradation is assessed in this model where one of the dielectric levels of the SiO\u003csub\u003e2\u003c/sub\u003e layer is replaced completely with MgO and NEXT. Fig. 13 shows the comparison of NEXT at different BEOL layers when MgO or SiO\u003csub\u003e2\u003c/sub\u003e is used. Crosstalk coefficients in the case of MgO replacing SiO\u003csub\u003e2\u003c/sub\u003e are generally 3% higher than when SiO\u003csub\u003e2\u003c/sub\u003e is implemented.\u003c/p\u003e\n\u003cp\u003eFig. 14 shows a tradeoff between the thermal performance and the impact on NEXT with different levels of MgO layer. In the case of MgO used as M1, M2, or M3 dielectric, the crosstalk situation would be significantly degraded. The NEXT coefficients are higher than 32% from M1 to M3. This can be attributed to the small metal pitches and high metal concentration in these layers. The crosstalk simulation also predicts that NEXT would relax considerably from M4 to above, quickly reducing from 30% to 18%. To achieve high effectiveness with MgO and balance with crosstalk tradeoff, the simulation has shown that M4, M5, and M6 are suitable candidates. The temperature reduction is expected to be from 3.5 \u0026deg;C to 4 \u0026deg;C, while NEXTs are expected to be lower than 30%. Therefore, strategically implementing MgO to a single BEOL layer can improve thermal performance while retaining control over crosstalk degradation.\u003c/p\u003e\n\u003cp\u003eAs mentioned above, to investigate the effect of MgO location on device temperature, the metal concentration was adjusted to be uniform in all layers. However, this also raises concern about the metal density effect on MgO contribution. As metal has high thermal conductivity, much greater than insulator in general, the increase in metal density can reduce the contribution of MgO. To address this concern, the effect of MgO in the BEOL structure with varied metal density needs to be investigated. Therefore, using the model built for this implementation scheme, the metal density in the BEOL structure is adjusted. The metal density after dummy filler in normal IC is around 50 %. In this research, a pessimistic situation will be assumed to check the effectiveness of MgO. Metal densities of 50/60/70 % were used in thermal simulation of BEOL with MgO implemented at different layers. Fig. 15. (b) illustrates varied metal density in the BEOL structure. Simulated gate temperatures are presented in Fig. 15. (a). As metal density increases, the device temperature tends to decrease. This is attributed to the impact of metal on thermal dissipation of BEOL structures. However, a clear temperature drop is noticed when MgO is implemented as above. Furthermore, this benefit can be seen at all metal densities. The temperature has the largest reduction when MgO is used in M1, M2 up to M6. At higher layers, the reduction gets smaller. One important thing that can be noticed is that the difference between the models with and without MgO is less significant at higher metal density. For example, at a metal density of 50 %, without MgO, the gate temperature is 155 \u0026deg;C at maximum, while it reduces to 152.5 \u0026deg;C when MgO is used at M8. That is 2.5 \u0026deg;C in difference. When the metal density is 70 %, the difference is only 1.5 \u0026deg;C. It suggests that the MgO effect is affected by metal density, as expected. However, the diminishing impact is noted at very high metal concentrations. At normal density, the contribution of MgO is considerable.\u003c/p\u003e"},{"header":"IV. CONCLUSION","content":"\u003cp\u003eMgO incorporation in the intermetal layer dielectric has been proposed as an innovative BEOL dielectric to mitigate the HD effect in hybrid bonded wafers/dices and traditional IC. Since the degraded crosstalk due to the high dielectric constant of MgO can be a trade-off, the structure and incorporation ratio would be optimized. Therefore, two MgO incorporation schemes have been studied to enhance HD capability and minimize the crosstalk impact. The first one is using double dielectric layers of MgO and SiO\u003csub\u003e2\u003c/sub\u003e with a specific ratio. The second one is to implement a single layer of BEOL MgO as a highly thermal conductive channel. A bilayer with MgO thickness ratio from 20\u0026ndash;40% can reduce the device temperature up to 7 \u0026deg;C while avoiding the large increase in NEXT. As a single layer, it is recommended that MgO be used in M4, M5, or M6 to maximize the benefits of high thermal conductivity while keeping crosstalk degradation under control. From these simulated results, MgO is a promising solution for local heating and thermal reliability issues while minimizing signal integrity deterioration.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eAnh-Duy Nguyen: conceptualization, data curation, formal analysis, investigation, methodology, validation, visualization, and writing \u0026ndash; original draft, An Hoang-Thuy Nguyen: conceptualization, data curation, formal analysis, investigation, methodology, validation, visualization, and first author equally contributed, Manh-Cuong Nguyen: data curation, formal analysis, validation, and visualization, G. Park: data curation, H. Kim: data curation, and R. Choi: funding acquisition, project administration, resources, supervision, and writing \u0026ndash; review, and editing\u003c/p\u003e\u003ch2\u003eAcknowledgement\u003c/h2\u003e\u003cp\u003eThis work was supported by Inha University Research Grant.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eC. Prasad, S. Ramey, L. Jiang, IEEE Int. Reliab. Phys. Symp. Proc. (2017) 6A4.1-6A4.7. https://doi.org/10.1109/IRPS.2017.7936336.\u003c/li\u003e\n\u003cli\u003eC. Prasad, IEEE Trans. Electron Devices 66 (2019) 4546\u0026ndash;4555. https://doi.org/10.1109/TED.2019.2943744.\u003c/li\u003e\n\u003cli\u003eO. Semenov, A. Vassighi, M. Sachdev, IEEE Trans. Device Mater. Reliab. 6 (2006) 17\u0026ndash;27. https://doi.org/10.1109/TDMR.2006.870340.\u003c/li\u003e\n\u003cli\u003eD. Vasileska, K. Raleva, S.M. Goodnick, J. Comput. Electron. 7 (2008) 66\u0026ndash;93. https://doi.org/10.1007/s10825-008-0254-y.\u003c/li\u003e\n\u003cli\u003eY. Sun, X. Yu, R. Zhang, B. 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Eng. 82 (2005) 534\u0026ndash;547. https://doi.org/10.1016/j.mee.2005.07.053.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"thermal conductivity, BEOL dielectric, thermal simulation, TCAD simulation, hybrid bonding","lastPublishedDoi":"10.21203/rs.3.rs-6379463/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6379463/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eAs the features of metal oxide semiconductor field-effect transistor (MOSFET) devices are aggressively scaled down, 3-dimensional (3D) integration is receiving significant attention for further development of semiconductor technology. While hybrid bonding is a promising solution for 3D integration because it can achieve high interconnect density, thermal management of bonded dies would be a potential problem. The thermal conductivity of the interlayer dielectric is crucial for effective thermal management. With high thermal conductivity and low fabrication temperature, magnesium oxide (MgO) is one of attractive dielectric interlayers. However, due to the high dielectric constant, crosstalk degradation is a major challenge for MgO implementation. This study proposes various strategies for MgO implementation. 2-dimensional technology computer-aided-design transient thermal simulation has been utilized to investigate MgO performance as an interlayer dielectric, while the finite element method has been used to study the tradeoff with crosstalk performance. The simulated results reveal that the device operating temperature can be reduced up to 7\u0026deg;C by applying a MgO layer in SiO\u003csub\u003e2\u003c/sub\u003e intermetal dielectric, with a thickness ratio ranging from 20\u0026ndash;40%. MgO single-layer implementation as a heat-conducting channel has also been studied. M4, M5, or M6 are recommended for high thermal conductivity and low crosstalk tradeoff. This study demonstrates that an optimized usage of MgO layer in the back-end-of-line can minimize crosstalk degradation while maintaining heat dissipation enhancement. These results suggest that MgO interlayer can be an attractive solution to the local heating issue in high-performance applications.\u003c/p\u003e","manuscriptTitle":"Heat Management Strategy for Hybrid-Bonded Wafers using MgO Interlayer Dielectric","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-05-13 15:39:15","doi":"10.21203/rs.3.rs-6379463/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2025-05-19T22:43:25+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-05-19T15:00:54+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"229652891345709749439727960674674126857","date":"2025-05-09T08:52:54+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-05-09T08:35:17+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-04-10T05:52:53+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-04-09T00:19:43+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of the Korean Physical Society","date":"2025-04-05T02:47:21+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-the-korean-physical-society","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of the Korean Physical Society](https://link.springer.com/journal/40042)","snPcode":"40042","submissionUrl":"https://submission.springernature.com/new-submission/40042/3","title":"Journal of the Korean Physical Society","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"13631d9e-4a31-41da-9bdd-69a9e94e31f5","owner":[],"postedDate":"May 13th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2025-06-20T03:38:30+00:00","versionOfRecord":[],"versionCreatedAt":"2025-05-13 15:39:15","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-6379463","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6379463","identity":"rs-6379463","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}