Analytical modeling of junction capacitance using Trapezoidal Approximation for source and drain Engineered Partially depleted Silicon on Insulator.

Abstract Junction capacitance variation in Source-Drain Engineered Partially Depleted Silicon On Insulator(SDE-PDSOI), due to the geometry effects of source and drain are discussed in this paper. Reduction in sidewall junction capacitance at saturation is caused by reduced charge due to geometrical variation of source and drain. Junction capacitance is modeled and validated with numerical simulations. Trapezoidal approximation is applied to extract the depletion width and the junction capacitance is evaluated. Modulation of the depletion width with varying potential along the channel thickness is also presented.