Effect of Polymer Liners in Different Via Shapes: Impact on Crosstalk Induced Delay

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material SiO 2 is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 nm and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T -type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.