Fault Detection Probability Evaluation Approach in Combinational Circuits Using Test Set Generation Method

This paper introduces an approach that chooses the fault detection by calculating probabilities using probability mass function (pmf) and cumulative distribution function (CDF). This work used a method for multiple stuck-at faults by producing a new test pattern in combinational circuits. We assumed that existence of all multiple faults is only because of one single component that is faulty. A complete test set can be created by all possible single stuck-at faults in a combinational circuit using some combination of gates. The test set generation fault detection method is applied on two different 3-bit input variable and 4-bit input variable circuits. The probability of error occurrence is calculated at both 3-bit and 4-bit input variable circuits. The resulting feature is used to obtain maximum error occurrence probability to detect faults by the logic used that the complexity of the circuit is inversely proportional to the fault occurrence probability. Then again, undetectability is directly proportional to the complexity of the circuit. Therefore, finest feasible circuit should have large input variable components with less complexity to reduce the fault occurrence probability.