A Low-offset High-Speed Triple-Tail Comparator with Inverter-based Amplifier

This paper presents a proposed inverter-based triple-tail comparator designed for high-speed and high-efficiency applications in analog-to-digital converters (ADCs). In this proposed comparator, parallel cross-coupled transistors and diodes are integrated seamlessly, maintaining the gain of the inverter-based pre-amplification stage and bolstering the robustness of the pre-amplifier. Combined with offset cancelled tech-niques, the definite state for each prior to comparison eliminates hysteresis effects. Utilizing the 28 nm CMOS process, the comparator achieves a high-speed data conversion rate of 2 GHz with a power consumption of only 0.366 mW. Across all process corners, the com-parator exhibits a delay of less than 40 ps with a differential input as low as 0.1 mV and a excellent delay slope of 5.1 ps/decade. Notably, it achieves a root mean square (rms) offset of 1.5 mV, representing a reduction of over 62% compared to traditional structures. Meanwhile, the gain of pre-amplifier stage increases by approximately 3.7 times.