Accelerated Circuit Simulations and Standard Cell Library Characterization through Neural Network-based Transistor Modeling

Accelerated Circuit Simulations and Standard Cell Library Characterization through Neural Network-based Transistor Modeling | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Accelerated Circuit Simulations and Standard Cell Library Characterization through Neural Network-based Transistor Modeling Rodion Novkin, Hussam Amrouch This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8902258/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract nn-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a \qty{3}{nm} nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we also perform analog- and digital-level simulations for various complex circuits. Our experiments reveal that NN-based models are a valid alternative to existing transistor compact models, capable of producing accurate delay and power estimates with a much higher speed and convergence time compared to the conventional Verilog-A-based industry-standard (BSIM-CMG) transistor compact model. Our NNs achieve sub- \((0.11%)\) and \((0.76%)\) errors for delay and total power evaluation on a wide range of circuits, while taking up to 8 times less time during the standard cell library characterization. Additionally, we provide comprehensive information and guidance on NN accuracy, unveiling the relationship between NN size and its effect on circuit simulation precision. Physical sciences/Engineering Physical sciences/Materials science Physical sciences/Mathematics and computing Physical sciences/Nanoscience and technology Neural network transistor model circuit simulation library characterization static timing analysis Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8902258","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":596122233,"identity":"24d70930-07b8-4e05-8ac9-2719aacf0eae","order_by":0,"name":"Rodion Novkin","email":"","orcid":"","institution":"Technical University of Munich","correspondingAuthor":false,"prefix":"","firstName":"Rodion","middleName":"","lastName":"Novkin","suffix":""},{"id":596122234,"identity":"56a571bd-b99a-40c8-ae9b-8c7e47e384e7","order_by":1,"name":"Hussam Amrouch","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAnElEQVRIiWNgGAWjYPCCA3JgiocULcY8JGtJ7CFaC/+0sw8f89TcSd8vkZ3A8KaCCC0St9ONjXmOPcvtkcjdwDjnDDHW3E5jk+ZtOAzWwszbRoQOeaiWdB6wln9EaDGAakmAaGkgQovh7TRmwznHDhv2nHm74eCcY0RokbudxvjgTc1hefb23I1ABhFaUMABUjWMglEwCkbBKMABAC8vNSe2iOaCAAAAAElFTkSuQmCC","orcid":"","institution":"Technical University of Munich","correspondingAuthor":true,"prefix":"","firstName":"Hussam","middleName":"","lastName":"Amrouch","suffix":""}],"badges":[],"createdAt":"2026-02-17 14:55:19","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-8902258/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-8902258/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":104898937,"identity":"9782139b-2c9c-437f-90b3-2495fb6dd1e3","added_by":"auto","created_at":"2026-03-18 12:41:48","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":638803,"visible":true,"origin":"","legend":"","description":"","filename":"source1.pdf","url":"https://assets-eu.researchsquare.com/files/rs-8902258/v1_covered_cfb7e5bf-1e99-422f-89b9-e8cc97a5efdf.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Accelerated Circuit Simulations and Standard Cell Library Characterization through Neural Network-based Transistor Modeling","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Neural network, transistor model, circuit simulation, library characterization, static timing analysis","lastPublishedDoi":"10.21203/rs.3.rs-8902258/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-8902258/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003enn-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a \\qty{3}{nm} nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we also perform analog- and digital-level simulations for various complex circuits. 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