Wafer-Scale Functional Circuits Based on Two Dimensional Semiconductors with Fabrication Optimized by Machine Learning

Wafer-Scale Functional Circuits Based on Two Dimensional Semiconductors with Fabrication Optimized by Machine Learning | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Wafer-Scale Functional Circuits Based on Two Dimensional Semiconductors with Fabrication Optimized by Machine Learning Xinyu Chen, Yufeng Xie, Yaochen Sheng, Hongwei Tang, Zeming Wang, and 29 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-152918/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 12 Oct, 2021 Read the published version in Nature Communications → Version 1 posted You are reading this latest preprint version Abstract Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials. Electrical Engineering Electronic Materials and Devices devices electronic materials two-dimensional layered materials (2DLMs) machine-learning (ML) Figures Figure 1 Figure 2 Figure 3 Figure 4 Full Text Additional Declarations There is NO Competing Interest. Supplementary Files SupplementaryInformation.pdf Supplementary Information Cite Share Download PDF Status: Published Journal Publication published 12 Oct, 2021 Read the published version in Nature Communications → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-152918","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":9029840,"identity":"8768f495-b32d-45b4-b91f-137e808bd35f","order_by":0,"name":"Xinyu Chen","email":"","orcid":"","institution":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Xinyu","middleName":"","lastName":"Chen","suffix":""},{"id":9029841,"identity":"70295a76-c119-478d-a4a2-c8876d0b19aa","order_by":1,"name":"Yufeng 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Bao","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAzElEQVRIiWNgGAWjYBACAzBZIcfAcADEYCNayxljUrUwtpGixZz98DHJn/MMEvuOnz3A8KHsMAP/7Ab8Wix70tIkJLcZJM48k5fAOOPcYQaJOwcIOOxAjtkNw21/EjccyDFg5m07zGAgkUBAy/k3ZjcS5xgkbjj/xoD5L1FabgBtOdgA1HIDaAsjMVosZzxL/9lwzMB45o03Bgd7zqXzSNwgoMWcP/mw4Y8aA9m+8zmGD36UWcvxzyCgBQUcAGIeEtSPglEwCkbBKMAFAKkaSMEYVcyqAAAAAElFTkSuQmCC","orcid":"https://orcid.org/0000-0002-3871-467X","institution":"State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"Wenzhong","middleName":"","lastName":"Bao","suffix":""}],"badges":[],"createdAt":"2021-01-22 04:40:30","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-152918/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-152918/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41467-021-26230-x","type":"published","date":"2021-10-12T04:00:00+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":5310009,"identity":"35e4d7d9-38d9-441f-bf9e-d11bb8c87799","added_by":"auto","created_at":"2021-01-27 17:18:29","extension":"jpg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":207369,"visible":true,"origin":"","legend":"a, Demonstration of uniform wafer-scale MoS2 growth by CVD, including a schematic diagram of the material growth equipment, a batch of 2 in. wafer-scale sapphire substrates uniformly covered with MoS2, a 2 in. sapphire wafer uniformly covered with MoS2 marked with Raman test points, and Raman mapping spectra from different locations marked in the previous picture. b, Schematic cross-section of an MoS2 FET with TG and global BG. Various factors that influence the device performance are categorized. c, Schematic diagram of the relationship between performance parameters of the transistor and performance limitations of the integrated circuit. d, Process flow and feedback optimization diagram from material synthesis to industrial-grade circuit design, fabrication, and test.","description":"","filename":"1.jpg","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1/797475fe246e042ccf3eb05c.jpg"},{"id":5309819,"identity":"a4e09546-9c2e-4184-acfe-e35dff828b91","added_by":"auto","created_at":"2021-01-27 17:15:29","extension":"jpg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":258629,"visible":true,"origin":"","legend":"a, Process flow for fabricating TG MoS2 FETs. The variations in each step are marked in blue. The end shows a three-dimensional hierarchical structure of an integrated circuit built with gate-last technology. b, Graphical representation of ensemble learning based on decision tree algorithm. The importance of each processing step is extracted during the creation of decision trees. c, Importance of processing steps for μ and VT based on random forest regression. d, Fabrication co-optimization based on ML. After training with EL, a score predictor can predict the overall device performance for all processing combinations using a grid search method. e, Ranking of all possible processing combinations. The high score combinations can be referenced for device fabrication. f, More than 500 MoS2 TG-FETs summarized in a μ-VT plot. Each color corresponds to one type of processing flow, and the red stars are devices fabricated with the guidance of ML analysis. g, Transfer characteristics for 60 MoS2 TG-FETs on one wafer at VDS = 0.5 V in linear and logarithmic coordinates. The inserts show histograms and Gaussian fits of statistical data for Y-function calculated mobility (upper) and threshold voltage (downside) to Gaussians.","description":"","filename":"2.jpg","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1/509e7ffcad54d962b09430f3.jpg"},{"id":5309544,"identity":"5ea091ec-19e4-4b3d-9fd1-3552ae8f2a08","added_by":"auto","created_at":"2021-01-27 17:12:29","extension":"jpg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":322601,"visible":true,"origin":"","legend":"Experimental data (circular dots) and simulation (lines) for a-b transfer and output characteristics of MoS2 TG-FETs, and c-d display VTCs of an MoS2 inverter with M1 and M2 FETs. The geometry parameter R = (W/L)M1/(W/L)M2 is used to adjust the switching point of the VTC curve in c, while a different method is used in d by independent tuning VT of M1. e shows a photograph of a negative edge-triggered D flip-flop (DFF), and f shows the corresponding experimental results. The upper two waveforms are inputs with a 0 to 3 V voltage swing, and the lower graph shows the measured output. g, Photograph of a 1-bit full-adder and h is the corresponding experimental results. i, Photograph of a 5-stage ring oscillator, and j is the corresponding output characteristics at 19.5 kHz with VDD = 3 V. k, Photograph of MoS2 memory unit arrays. The zoom-in image shows the structure of a 1T-1C dynamic memory circuit, whose schematic diagram is shown in l. m, Write and read operations in the 1T-1C unit. n, Estimated charge stored in the capacitor as a function of holding time for 5 different devices. o, Schematic diagram of an MoS2 phototransistor with a 10-nm-thick Au top gate, and p shows transfer characteristics with and without illumination at VDS = 0.5 V. q, Photocurrent mapping for a 9×9 MoS2 FET array. The photocurrent is produced by scanning the array using a microscope-focused white beam.","description":"","filename":"3.jpg","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1/2a01690abe82be36363e06b3.jpg"},{"id":5309384,"identity":"7859158b-8195-49d4-a910-b2d7d39ae996","added_by":"auto","created_at":"2021-01-27 17:09:29","extension":"jpg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":299936,"visible":true,"origin":"","legend":"Wafer-scale integrated circuits built from MoS2 FETs. a, Photograph of a 2-inch MoS2 wafer with 1-bit full-adder arrays as functional circuits in the center, and MoS2 TG-FET arrays used as monitoring devices locating in the surrounding regions. b, Wafer maps of mobility (left) and VT statistics (center) extracted from devices in the surrounding regions. The yellow scale bars show mobility and VT values. Each block’s color scale represents a value averaged from 16 FETs, and the entire wafer has 81 blocks. The right graph illustrates the yield of 1-bit full-adder circuit arrays. The red and gray squares represent the proportion of working and non-working circuits, respectively. c, Photograph of a 4-bit full-adder under which is the truth table for logical combinations. d, Functional measurements of the 4-bit full-adder with VDD = 3 V. The 4-bit full-adder was tested using a series of input combinations (A, B) in the following order: (0000+0000, 0000+0111, 1111+1000, 1111+1111) with Ci = 0 and Ci = 1.","description":"","filename":"4.jpg","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1/5cf52a5011020f56de4e0ee4.jpg"},{"id":15778910,"identity":"4f5072d3-ccb6-4a5f-8c85-c461d7025128","added_by":"auto","created_at":"2021-11-22 15:32:50","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1864473,"visible":true,"origin":"","legend":"Article File","description":"","filename":"Manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1_covered.pdf"},{"id":13579419,"identity":"ed4aa763-d909-4232-b4f9-e80963a6c69e","added_by":"auto","created_at":"2021-09-17 04:19:43","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1859579,"visible":true,"origin":"","legend":"Article File","description":"","filename":"Manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1_covered.pdf"},{"id":5310139,"identity":"bbc1dcaf-9435-4df3-a51b-8431ae5a9ee8","added_by":"auto","created_at":"2021-01-27 17:21:40","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":1328093,"visible":true,"origin":"","legend":"Article File","description":"","filename":"Manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1_stamped.pdf"},{"id":5309385,"identity":"dc27615d-762c-4b5b-af09-ed6ab8cf0148","added_by":"auto","created_at":"2021-01-27 17:09:29","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":1514902,"visible":true,"origin":"","legend":"Supplementary Information","description":"","filename":"SupplementaryInformation.pdf","url":"https://assets-eu.researchsquare.com/files/rs-152918/v1/e496457eeab71b476834b311.pdf"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Wafer-Scale Functional Circuits Based on Two Dimensional Semiconductors with Fabrication Optimized by Machine Learning","fulltext":[{"header":"Full Text","content":"\u003cp\u003eThis preprint is available for \u003ca href='/article/rs-152918/latest.pdf' target='_blank'\u003edownload as a PDF\u003c/a\u003e.\u003c/p\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nature-portfolio","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"","title":"Nature Portfolio","twitterHandle":"","acdcEnabled":false,"dfaEnabled":false,"editorialSystem":"ejp","reportingPortfolio":"","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"devices, electronic materials, two-dimensional layered materials (2DLMs), machine-learning (ML) ","lastPublishedDoi":"10.21203/rs.3.rs-152918/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-152918/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials.","manuscriptTitle":"Wafer-Scale Functional Circuits Based on Two Dimensional Semiconductors with Fabrication Optimized by Machine Learning","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2021-01-27 17:09:28","doi":"10.21203/rs.3.rs-152918/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nature-communications","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"NCOMMS","sideBox":"Learn more about [Nature Communications](http://www.nature.com/ncomms/)","snPcode":"","submissionUrl":"https://mts-ncomms.nature.com/","title":"Nature Communications","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature Communications","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"1560ec58-7030-48ec-b7b1-403194d82557","owner":[],"postedDate":"January 27th, 2021","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":2104419,"name":"Electrical Engineering"},{"id":2104420,"name":"Electronic Materials and Devices"}],"tags":[],"updatedAt":"2021-11-22T15:32:02+00:00","versionOfRecord":{"articleIdentity":"rs-152918","link":"https://doi.org/10.1038/s41467-021-26230-x","journal":{"identity":"nature-communications","isVorOnly":false,"title":"Nature Communications"},"publishedOn":"2021-10-12 04:00:00","publishedOnDateReadable":"October 12th, 2021"},"versionCreatedAt":"2021-01-27 17:09:28","video":"","vorDoi":"10.1038/s41467-021-26230-x","vorDoiUrl":"https://doi.org/10.1038/s41467-021-26230-x","workflowStages":[]},"version":"v1","identity":"rs-152918","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-152918","identity":"rs-152918","version":["v1"]},"buildId":"7rjqhiLT3MXkJMwkYKINL","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}