Unifying Heterogeneous and Monolithic Integration via Dual-sided 3D Technology

Unifying Heterogeneous and Monolithic Integration via Dual-sided 3D Technology | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Physical Sciences - Article Unifying Heterogeneous and Monolithic Integration via Dual-sided 3D Technology Heng Wu, Yanbang Chu, Peiyan Hong, Jianxiang Jin, Jinwei Sun, and 26 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-8891286/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Artificial Intelligence (AI), has been occupying the central position in recent technological advancement, propelled by exponentially increasing computing resources, which in turn stimulate the demand on higher level 3D integration for integrated circuits. However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the "Flip 3D" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce "Hyper 3D" (H3D) technology for dual-sided system-on-wafer integration. Our results validate that this unified dual-sided scheme provides effective solution to the "computing," "memory," and "connectivity" walls. This work establishes a scalable roadmap for multi-layer on-chip systems, providing a full-3D hardware strategy for the next generation of AI hardware. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Full Text Additional Declarations There is NO Competing Interest. Supplementary Files F3DandH3DdemonstrationSupplementaryInfo.pdf The supplementary information of the main article Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-8891286","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Physical Sciences - Article","associatedPublications":[],"authors":[{"id":598155122,"identity":"c55ff1a9-e222-40ed-bd24-f4594bb32c46","order_by":0,"name":"Heng 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However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the \"Flip 3D\" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce \"Hyper 3D\" (H3D) technology for dual-sided system-on-wafer integration. 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