A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability

A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability Jianbin Guo, Zhehong Qian, Xinru Chen, Hang Xu, Yafen Yang, David Wei Zhang This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4609119/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 08 Jan, 2025 Read the published version in Scientific Reports → Version 1 posted 11 You are reading this latest preprint version Abstract In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current under the clamping effect, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage ( V on ) and turn-off loss ( E off ) of the new structure is also improved by 23.2% compared with the conventional CSTBT. Physical sciences/Engineering/Electrical and electronic engineering Physical sciences/Physics/Electronics photonics and device physics CSTBT self-biased pMOS saturation current turn-off loss short-circuit safe operating area Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 I. INTRODUCTION Insulated gate bipolar transistor (IGBT) stands as a key component in power electronics, finding extensive applications in various domains such as home appliances, automotive electronics, uninterruptible power supply (UPS), photovoltaic inverters[ 1 ]. The main issue in IGBT design is the tradeoff between on-state voltage ( V on ), turn-off loss ( E off ), and short-circuit safe operating area (SCSOA). Extensive research and experiments have been carried out to improve the tradeoff relationship between V on and E off , such as the injection-enhanced gate transistor (IEGT)[ 2 ], the partially narrow mesa IGBT (PNM-IGBT)[ 3 ], the carried-stored trench-gate bipolar transistor (CSTBT)[ 4 ], Superjunction IGBT (SJ-IGBT)[ 5 ], Trench Shielded Planar gate IGBT (TSPG-IGBT)[ 6 ], and CSTBT with stepped split trench-gate (SSG-CSTBT)[ 7 ]. By modulating the carrier distribution in the on-state, IEGT, PNM-IGBT, and CSTBT reduce the V on significantly. Additionally, adjusting the gate structure to reduce gate charge or optimizing the gate control strategy have led to a noteworthy reduction in switching losses of these devices[ 8 ], [ 9 ], [ 10 ], [ 11 ], [ 12 ], [ 13 ], [ 14 ]. In order to improve short-circuit capability, many structures have been proposed[ 6 ], [ 15 ], [ 16 ], [ 17 ], [ 18 ], [ 19 ], [ 20 ], [ 21 ], [ 22 ]. Notably, among these structures, an additional diode or MOSFET has been employed to clamp the potential of the nMOS intrinsic drain in IGBT or suppress the saturation current, which serves to extends the short-circuit withstand time. However, considering that higher doped N-CS layer in the CSTBT may degrade the breakdown voltage ( BV ), the doping concentration of N-CS layer is limited. To achieve a well-balanced V on - E off - SCSOA tradeoff relationship without compromising BV characteristics, a novel deep trench CSTBT (DT-CSTBT) with self-biased pMOS has been proposed and studied by TCAD tools. II. DEVICE STRUCTURE AND PRINCIPLE As shown in Fig. 1 (b), our proposed DT-CSTBT has the same trench gate as the conventional CSTBT which is shown in Fig. 1 (a). In the CSTBT structure, the N-CS layer below the P-well region can increase the carrier concentration at the emitter side. To shield the undesirable effect of the highly doped N-CS layer on BV, the proposed DT-CSTBT features emitter trenches and the P-layer. The P-layer, N-CS layer, P-well, as well as the emitter collectively constitute a self-biased pMOS. The equivalent circuit of the proposed structure includes a nMOS, a pMOS, and a PNP bipolar transistor, as shown in Fig. 1 (c). In the off-state, compared to the conventional CSTBT structure that utilizes the P-well/N-CS junction ( J 1 ) to withstand the voltage, the voltage of the DT-CSTBT is mainly sustained by the P-layer/N-Drift junction ( J 2 ). In addition, as the potential of the collector increases, the potential of the N-CS layer in the DT-CSTBT also increases. When the potential rises to the threshold voltage of pMOS, a hole channel is established in the N-CS layer close to the emitter trench, causing the pMOS to turn on automatically. This hole channel connects the P-layer to the emitter, effectively clamping the potential of both the P-layer and N-CS layer to a low value by this self-biased pMOS. By virtue of J 2 withstanding high voltage and the presence of self-biased pMOS, there is no high electric field in the region near the gate of the proposed DT-CSTBT. Consequently, the N-CS layer can be highly doped without damaging breakdown characteristics. Similarly, the self-biased pMOS turns on as the potential of the collector rises in the on-state. The clamped potential in the N-CS layer depends on the threshold voltage of the pMOS. Since the N-CS layer acts as the intrinsic drain of the nMOS, maintaining a low clamped potential enables the proposed structure to operate at a reduced saturation current. The higher doped N-CS layer enhances the conductance modulation and reduces the Von in the on-state. III. RESULTS AND DISCUSSION The simulations have been completed by using the Sentaurus TCAD tool. Figure 2 describes the fabrication flow of the proposed DT-CSTBT. The key simulation parameters of DT-CSTBT and Conventional CSTBT are listed in Table 1. In order to reduce the threshold voltage of the pMOS, the thickness of oxide at the emitter trench is set to 25nm. TABLE Ⅰ. KEY DEVICE PARAMETERS Parameter Conventional DT-CSTBT Gate oxide thickness, T OX (nm) 120 120 Trench Emitter depth, d TE (µm) - 6.4 P-well depth, d PW (µm) 2.5 2.5 N-CS thickness, T CS (µm) \(\approx\) 1 \(\approx\) 1 N-CS doping, N CS (cm − 3 ) 1e16 1e17 P-layer thickness, T PL (µm) - 1 P-layer dose, D PL (cm − 2 ) - 6e14 Substrate thickness, T SUB (µm) 115 115 N-Drift doping, N ND (cm − 3 ) 1e14 1e14 N-FS dose, N FS (cm − 2 ) 2e16 2e16 P-collector dose, N PC (cm − 2 ) 4e17 4e17 Cell pitch, W C (µm) 3 3 A. Static characteristics The potential distributions at the emitter side in the off-state are shown in Fig. 3 . The self-biased pMOS in the proposed DT-CSTBT turns on at high reverse bias voltage. As shown in Fig. 3 (b), even if the proposed structure is under a high voltage of 600V, the potentials at each point (A, B, C) are all below 2V. This indicates that the self-biased pMOS functions well as the potential clamping or potential shielding. In the off-state, the voltage of the proposed DT-CSTBT is mainly sustained by the P-layer/N-Drift junction. Thus, the location of the peak electric field shifts to the right, as shown in Fig. 4 (a). The electric field distributions at the emitter side in both structures are shown in Fig. 4 (b) and (c). Thanks to the potential clamping in Fig. 3 (b), the electric field near the gate in the proposed structure is also significantly reduced. Specifically, the electric field below the trench gate is only 124 V/cm at high reverse bias voltage, which is about 3 orders of magnitude lower than the same position in the conventional structure ( 218498V/cm ). This signifies a notable improvement in gate reliability for the proposed DT-CSTBT. The tradeoff relationship between V on and BV is studied and the simulation results are shown in Fig. 5 . BV remains almost constant and meets the 1200V voltage class in the proposed structure when the V on decreases continuously. Due to the shielding effect of self-biased pMOS in Fig. 4 (c), a low V on of 1.201V is achieved while maintaining BV at 1600V. In contrast, the conventional structure experiences a decrease in V on from 1.614V to 1.206V as N CS increases (from 1.0×10 16 cm − 3 to 5.0×10 17 cm − 3 ). However, its BV decreases dramatically from 1762 V to 32 V. The feasibility of higher N CS in the proposed structure is verified. Figure 6 shows the distributions of the hole concentration in the on-state along line AA’ in Fig. 1 ( I CE = 200 A/cm 2 and V GE =15 V ). The DT-CSTBT with a higher N CS forms a more robust hole barrier and can effectively block a greater number of holes. The conductance modulation in the proposed structure is greatly enhanced. At point A in Fig. 3 , corresponding to the intrinsic drain of nMOS, the potential in the proposed DT-CSTBT is about 6V lower than that in the traditional CSTBT. Figure 7 compares the forward conduction characteristics, revealing a 40.3% reduction in the saturation current ( I dsat , at V CE =10 V) of the proposed DT-CSTBT attributable to the lower potential at the intrinsic drain of the nMOS. Besides, the V on of the proposed structure is 1.447 V, indicating a 10.3% reduction compared to the 1.614 V observed in the conventional CSTBT. B. Short-circuit characteristics Figure 8 (a) compares the short-circuit characteristics of the two structures. The simulation test circuit of the short-circuit characteristics is shown in Fig. 8 (b). The t SC of the proposed DT-CSTBT is 13.1 µs, representing a 23.5% improvement over the conventional CSTBT (10.6 µs). The I dsat is reduced due to the potential clamping, contributing to the enlargement of the SCSOA for the proposed structure. C. Transient characteristics The turn-off characteristics of the two structures are also studied, with the turn-off waves shown in Fig. 9 (a), and the turn-off test circuit shown in Fig. 9 (b). Notably, there is a larger and longer current tail in the conventional CSTBT. This suggests that the self-biased pMOS also promotes the extraction of hole to reduce E off during the turn-off. By adjusting the doping dose of P + at the collector side (from 5.0×10 12 cm − 2 to 1.0×10 14 cm − 2 ), the simulation of the switching characteristics is performed to obtain the tradeoff relationships as shown in Fig. 10 . At the same V on (about 1.45 V), the E off of the proposed structure is reduced by 23.2% compared to the conventional structure. The V on is reduced by 10.3% from 1.614V to 1.447V at the same E off . The tradeoff relationship between V on and E off of the proposed DT-CSTBT is significantly improved. D. Influence of D PL and d TE The emitter trench and the P-layer are introduced to protect the N-CS layer and form a self-biased pMOS to maintain a low I dsat . Since the depth of the emitter trench ( d TE ) affects the position of the withstand voltage junction J 2 , and the dose of P-layer ( D PL ) affects the electric field distribution in the depletion region and charge balance, the performances of DT-CSTBT under different d TE and D PL are also studied. The depth of the emitter trench hardly affects conductance modulation or hole extraction. As shown in Fig. 11 (a), different depths of the emitter trench have little influence on V on and E off . The deeper emitter also results in an enhanced potential shielding of the self-biased pMOS. The high potential region is further away from the nMOS. Therefore, I dsat of the proposed DT-CSTBT decreases with increasing d TE , as shown in Fig. 11 (b). However, the deeper emitter causes the junction that withstands voltage to shift downward, which corresponds to a thinning of the N-Drift region. As a result, the BV and E off inevitably decrease with increasing d TE , shown in Fig. 11 (b). High D PL is observed to enhance hole extraction, subsequently weakening the conductance modulation effect. As shown in Fig. 12 (a), an increase in D PL results in an elevation of V on , while E off concurrently decreases. In Fig. 12 (b), a consistent reduction in I dsat is observed with increasing D PL . Due to charge imbalance, BV initially decreases and subsequently rises as D PL increases. Thus, a better tradeoff between V on and E off can be obtained by properly increasing the d TE and D PL . This also leads to smaller I dsat , ensuring a larger SCSOA. Although decreases with increasing d TE , BV still meets the 1200V voltage class. IV. CONCLUSION In this work, a novel DT-CSTBT features the emitter trenches and P-layer has been proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, exhibits an excellent potential clamping effect. Under the clamping effect, both the potential and the electric field in the region near the gate decrease dramatically. The extremely low potential at the N-CS layer leads to a suppressed I dsat and a 23.5% enlarged SCSOA. It ensures the better reliability of the gate and the feasibility of higher N CS due to the high electric field away from the gate. Moreover, the proposed DT-CSTBT achieves a 23.2% reduction in E off at the same V on . A V on and E off tradeoff is effectively managed with the help of higher N CS and a hole path through the self-biased pMOS. In summary, the improved reliability and reduced losses position the proposed DT-CSTBT as a promising candidate for application in power electronic systems. Declarations Author Contribution "J.Guo, H.Xu and Y. Yang wrote the main manuscript text and Z. Qian, X. Chen prepared the figures. All authors reviewed the manuscript." Data Availability All data generated or analysed during this study are included in this published article. References N. Iwamuro and T. Laska, “IGBT History, State-of-the-Art, and Future Prospects,” IEEE Trans. Electron Devices, vol. 64, no. 3, pp. 741–752, Mar. 2017, doi: 10.1109/TED.2017.2654599 . M. Kitagawa, I. Omura, S. Hasegawa, T. Inoue, and A. Nakagawa, “A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor,” in Proceedings of IEEE International Electron Devices Meeting , Dec. 1993, pp. 679–682. doi: 10.1109/IEDM.1993.347221 . M. Sumitomo, J. Asai, H. Sakane, K. Arakawa, Y. Higuchi, and M. Matsui, “Low loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT),” in 2012 24th International Symposium on Power Semiconductor Devices and ICs , Bruges, Belgium: IEEE, Jun. 2012, pp. 17–20. doi: 10.1109/ISPSD.2012.6229012 . H. Takahashi, H. Haruguchi, H. Hagino, and T. Yamada, “Carrier stored trench-gate bipolar transistor (CSTBT)-a novel power device for high voltage application,” in 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD ’96. Proceedings , May 1996, pp. 349–352. doi: 10.1109/ISPSD.1996.509513 . F. D. Bauer, “The super junction bipolar transistor: a new silicon power device concept for ultra low loss switching applications at medium to high voltages,” Solid-State Electron., vol. 48, no. 5, pp. 705–714, May 2004, doi: 10.1016/j.sse.2003.09.017 . J. Hu, M. Bobde, H. Yilmaz, and A. Bhalla, “Trench shielded planar gate IGBT (TSPG-IGBT) for low loss and robust short-circuit capalibity,” in 2013 25th International Symposium on Power Semiconductor Devices & IC’s (ISPSD) , May 2013, pp. 25–28. doi: 10.1109/ISPSD.2013.6694390 . H. Xu, Y. Yang, J. Tan, H. Zhu, Q.-Q. Sun, and D. W. Zhang, “Carrier Stored Trench-Gate Bipolar Transistor With Stepped Split Trench-Gate Structure,” IEEE Trans. Electron Devices, pp. 1–6, 2022, doi: 10.1109/TED.2022.3200645 . W. Saito and S.-I. Nishizawa, “Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor,” IEEE Electron Device Lett. , vol. 41, no. 12, pp. 1814–1816, Dec. 2020, doi: 10.1109/LED.2020.3034898 . J. Zhang, X. Xiao, R. Zhu, Q. Zhao, and B. Zhang, “Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench,” IEEE J. Electron Devices Soc., vol. 9, pp. 704–712, 2021, doi: 10.1109/JEDS.2021.3097388 . X. Luo et al. , “A Low Loss and On-State Voltage Superjunction IGBT with Depletion Trench,” in 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) , Vienna, Austria: IEEE, Sep. 2020, pp. 130–133. doi: 10.1109/ISPSD46842.2020.9170193 . T. Sakano, K. Takao, Y. Iwakaji, H. Itokazu, and T. Matsudai, “Ultra-Low Switching Loss Triple-Gate controlled IGBT,” in 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) , Nagoya, Japan: IEEE, May 2021, pp. 363–366. doi: 10.23919/ISPSD50666.2021.9452246 . W. Saito and S.-I. Nishizawa, “Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance,” IEEE Trans. Electron Devices , vol. 67, no. 8, pp. 3285–3290, Aug. 2020, doi: 10.1109/TED.2020.3002510 . T. Sakano et al. , “Three-level Gate Drive Technique for Enhancing Switching Loss Reduction in Triple-Gate IGBTs,” in 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD) , May 2022, pp. 117–120. doi: 10.1109/ISPSD49238.2022.9813666 . K. Konishi, K. Nishi, K. Sako, and A. Furukawa, “Split-Dummy-Active CSTBT ™ for Improving Recovery dV/dt and Turn-on Switching Loss Tradeoff,” in 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD) , May 2022, pp. 273–276. doi: 10.1109/ISPSD49238.2022.9813634 . R. Kamibaba, K. Konishi, Y. Fukada, A. Narazaki, and M. Tarutani, “Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology,” in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD) , May 2015, pp. 29–32. doi: 10.1109/ISPSD.2015.7123381 . R. Bhojani, J. Lutz, R. Baburske, H.-J. Schulze, and F.-J. Niedemostheide, “A novel Injection Enhanced Floating Emitter (IEFE) IGBT structure improving the ruggedness against short-circuit and thermal destruction,” in 2017 29th International Symposium on Power Semiconductor Devices and IC’s (ISPSD) , May 2017, pp. 113–116. doi: 10.23919/ISPSD.2017.7988939 . H. Xu, D.-H. Zhao, H. Zhu, Q.-Q. Sun, and D. W. Zhang, “A process optimization method for carrier stored trench bipolar transistor (CSTBT) device,” in 2021 IEEE 14th International Conference on ASIC (ASICON) , Oct. 2021, pp. 1–4. doi: 10.1109/ASICON52560.2021.9620236 . S. Zhang et al. , “A High-voltage Silicon-On-Insulator Lateral IGBT with Segmented Trenches for Improved Short circuit Ruggedness,” in 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD) , May 2022, pp. 309–312. doi: 10.1109/ISPSD49238.2022.9813658 . H. Xu et al., "A Low Conduction Loss IGBT With Hole Path and Temperature Sensing," in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5236–5241, Oct. 2023, doi: 10.1109/TED.2023.3306734 . B. Yi, X. Xie, M. Kong, J. Cheng, and X. Chen, “A Novel Diode-Clamped Carrier Stored Trench IGBT With Improved Performances,” IEEE Trans. Electron Devices , vol. 67, no. 1, pp. 243–248, Jan. 2020, doi: 10.1109/TED.2019.2955820 . P. Li, M. Kong, and X. Chen, “A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current,” in 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD) , Jun. 2016, pp. 307–310. doi: 10.1109/ISPSD.2016.7520839 . J. Wei, S. Zhang, X. Luo, D. Fan and B. Zhang, "Low Switching Loss and EMI Noise IGBT With Self-Adaptive Hole-Extracting Path," in IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2572–2576, May 2021, doi: 10.1109/TED.2021.3065898 . Additional Declarations No competing interests reported. Cite Share Download PDF Status: Published Journal Publication published 08 Jan, 2025 Read the published version in Scientific Reports → Version 1 posted Editorial decision: Revision requested 29 Oct, 2024 Reviews received at journal 28 Oct, 2024 Reviewers agreed at journal 22 Oct, 2024 Reviewers agreed at journal 10 Jul, 2024 Reviews received at journal 27 Jun, 2024 Reviewers agreed at journal 26 Jun, 2024 Reviewers invited by journal 24 Jun, 2024 Editor assigned by journal 24 Jun, 2024 Editor invited by journal 24 Jun, 2024 Submission checks completed at journal 21 Jun, 2024 First submitted to journal 20 Jun, 2024 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4609119","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":325250304,"identity":"30891fb9-20bc-4e00-9e0d-5c414982baf4","order_by":0,"name":"Jianbin Guo","email":"","orcid":"","institution":"Fudan University","correspondingAuthor":false,"prefix":"","firstName":"Jianbin","middleName":"","lastName":"Guo","suffix":""},{"id":325250307,"identity":"e15bfbe2-5d6f-4dde-9622-671f60e33f88","order_by":1,"name":"Zhehong Qian","email":"","orcid":"","institution":"Fudan University","correspondingAuthor":false,"prefix":"","firstName":"Zhehong","middleName":"","lastName":"Qian","suffix":""},{"id":325250309,"identity":"e2d67689-08c4-4791-a75e-cd58d5bc200e","order_by":2,"name":"Xinru Chen","email":"","orcid":"","institution":"Fudan University","correspondingAuthor":false,"prefix":"","firstName":"Xinru","middleName":"","lastName":"Chen","suffix":""},{"id":325250310,"identity":"b6b8d331-82e1-4a05-b20b-9a893a9cac68","order_by":3,"name":"Hang Xu","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA70lEQVRIiWNgGAWjYBACAwglIcfPfIBBAsw+QJwWC2PJtgTStFQkbjhGrBZz9rOHX/O2SSRuPsZjeOPnDgY5vhsJjJ8L8Gix7MlLs5zZJmG87RiPsWXvGQZjyRsJzNIz8DnsQI6Zwcc2Cdlt93vMJHjbGBI33EhgY+bBp+X8GzODxDYJxs1tPGaSf9sY6glruZFj/ABoi+IGNh4zaaAtCQaEtbwxY5xxTsJY4hhbsbVsm4ThzDMPm6XxOyzH+DNPWZ0cfxvzxptv22zk+Y4nH/yMTwsQsEkgcUBsxgb8GhgYmD8QUjEKRsEoGAUjHAAAeMhKwH3EP7UAAAAASUVORK5CYII=","orcid":"","institution":"Fudan University","correspondingAuthor":true,"prefix":"","firstName":"Hang","middleName":"","lastName":"Xu","suffix":""},{"id":325250311,"identity":"0076cafb-ae94-460c-86ae-f63b0710ac1e","order_by":4,"name":"Yafen Yang","email":"","orcid":"","institution":"Fudan University","correspondingAuthor":false,"prefix":"","firstName":"Yafen","middleName":"","lastName":"Yang","suffix":""},{"id":325250312,"identity":"9bb01c15-acb6-47ba-96f5-6aa9bff1573e","order_by":5,"name":"David Wei Zhang","email":"","orcid":"","institution":"Fudan University","correspondingAuthor":false,"prefix":"","firstName":"David","middleName":"Wei","lastName":"Zhang","suffix":""}],"badges":[],"createdAt":"2024-06-20 04:41:40","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4609119/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4609119/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41598-025-85530-0","type":"published","date":"2025-01-08T15:57:46+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":60139760,"identity":"b77e051a-48d5-4e0c-a4ee-433c6e766594","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":205122,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic views of (a) the conventional CSTBT and (b) the proposed DT-CSTBT. (c) the simplified equivalent circuit of the proposed structure.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/eaee0152a652fb02828aa408.png"},{"id":60139762,"identity":"1e90173c-0c93-4d63-83e5-ec9d33ce2abe","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":160631,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Proposed fabrication flow of DT-CSTBT. (b) Schematic diagram of key fabrication process.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/0abaa4793e9541143608b642.png"},{"id":60139761,"identity":"f6413b15-503c-4a5d-8581-b2aa532839f7","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":95545,"visible":true,"origin":"","legend":"\u003cp\u003ePotential distribution in the off-state (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e = 0V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e = 600V) of (a) Conventional CSTBT (8.04V @ A, 19.05V @ B, 55.59V @ C) and (b) DT-CSTBT (1.34V @ A, 1.45V @ B, 1.72V @ C).\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/166f505efae6c153e820e6f9.png"},{"id":60139768,"identity":"db8adcf4-db89-40ee-9703-34a84d1f781c","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":186632,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Electric field in the off-state (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e = 1500 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e = 0 V ) along line AA’ in Fig. 1. Electric field distributions of (b) Conventional CSTBT and (c) DT-CSTBT in the off-state ( \u003cem\u003eV\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e = 1500 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e = 0 V ).\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/a30667bbc6c02ef69eb599d5.png"},{"id":60141241,"identity":"716f39ee-f698-44a2-88c7-6cc7a80bd013","added_by":"auto","created_at":"2024-07-12 09:05:50","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":93386,"visible":true,"origin":"","legend":"\u003cp\u003eTradeoff relationship between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eBV\u003c/em\u003e for the DT-CSTBT and conventional CSTBT.\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/6d6692ddc0e07ceaa4ab2019.png"},{"id":60139767,"identity":"cfab79af-23a6-45ca-bf51-dae6cc937750","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":125728,"visible":true,"origin":"","legend":"\u003cp\u003eHole concentration distributions at \u003cem\u003eI\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e\u003cem\u003e \u003c/em\u003e= 200 A/cm\u003csup\u003e2\u003c/sup\u003e (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e = 15V) along line AA’ in Fig. 1.\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/09aedbcc6c85f2871e812b29.png"},{"id":60139763,"identity":"82a308fa-e66f-490c-b60e-986625140acb","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":132059,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Forward conduction characteristic (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e = 15V). (b) Partial enlargement of (a).\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/34f6f9a1bb45df0590409c59.png"},{"id":60140631,"identity":"ec78a539-63fb-435d-a7aa-4f9819923234","added_by":"auto","created_at":"2024-07-12 08:57:50","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":75087,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Simulated SCSOA, (b) short-circuit characteristics test circuit, where \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e = 10 mΩ,\u003cem\u003e L\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e = 20nH, \u003cem\u003eR\u003c/em\u003e\u003csub\u003eE\u003c/sub\u003e = 10mΩ, \u003cem\u003eR\u003c/em\u003e\u003csub\u003eG\u003c/sub\u003e = 4 Ω, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBUS\u003c/sub\u003e = 600V\u003c/p\u003e","description":"","filename":"8.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/3c48da06625fe954471e29b8.png"},{"id":60139764,"identity":"48547f93-dc28-4dfc-b973-525ebf506880","added_by":"auto","created_at":"2024-07-12 08:41:50","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":110214,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Simulated turn-off characteristics. (b) Switching characteristics test circuit, where \u003cem\u003eL\u003c/em\u003e\u003csub\u003eLoad\u003c/sub\u003e = 0.1mH, \u003cem\u003eL\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e = 3nH, \u003cem\u003eL\u003c/em\u003e\u003csub\u003eE\u003c/sub\u003e = 3nH, \u003cem\u003eR\u003c/em\u003e\u003csub\u003eG\u003c/sub\u003e = 4 Ω, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBUS\u003c/sub\u003e = 600V.\u003c/p\u003e","description":"","filename":"9.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/73f0dcd97893c7d003f5087c.png"},{"id":60140114,"identity":"84f560e9-d8d9-40fd-8bbc-46f74a3580a1","added_by":"auto","created_at":"2024-07-12 08:49:50","extension":"png","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":241816,"visible":true,"origin":"","legend":"\u003cp\u003eTradeoff between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e for conventional CSTBT and DT-CSTBT.\u003c/p\u003e","description":"","filename":"10.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/c1c61d61cca74c56cfb0346f.png"},{"id":60140112,"identity":"a38854db-fcdb-4009-bbdc-543f109027e7","added_by":"auto","created_at":"2024-07-12 08:49:50","extension":"png","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":141431,"visible":true,"origin":"","legend":"\u003cp\u003eSimulated influence of \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e on (a) \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e, (b) \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e\u003cem\u003e \u003c/em\u003eand \u003cem\u003eBV\u003c/em\u003e of the DT-CSTBT. \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e = 2.0×10\u003csup\u003e14\u003c/sup\u003e cm\u003csup\u003e-2\u003c/sup\u003e.\u003c/p\u003e","description":"","filename":"11.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/979918dc2b90b2a2740f7785.png"},{"id":60140633,"identity":"1c4233ec-800a-4f1f-9940-b7fc2df3170c","added_by":"auto","created_at":"2024-07-12 08:57:50","extension":"png","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":143169,"visible":true,"origin":"","legend":"\u003cp\u003eSimulated influence of \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e\u003cem\u003e \u003c/em\u003eon (a) \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e, (b) \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e\u003cem\u003e \u003c/em\u003eand \u003cem\u003eBV\u003c/em\u003e of the DT-CSTBT. \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e = 6.4 μm.\u003c/p\u003e","description":"","filename":"12.png","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/455b8d4c85d44df92ae148b2.png"},{"id":73694019,"identity":"42bab822-09ee-4dc7-9909-0c869d4b594a","added_by":"auto","created_at":"2025-01-13 16:10:33","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2130985,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4609119/v1/efa2defc-80ab-46ea-b256-d0d1616214b2.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability","fulltext":[{"header":"I. INTRODUCTION","content":"\u003cp\u003eInsulated gate bipolar transistor (IGBT) stands as a key component in power electronics, finding extensive applications in various domains such as home appliances, automotive electronics, uninterruptible power supply (UPS), photovoltaic inverters[\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. The main issue in IGBT design is the tradeoff between on-state voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e), turn-off loss (\u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e), and short-circuit safe operating area (SCSOA).\u003c/p\u003e \u003cp\u003eExtensive research and experiments have been carried out to improve the tradeoff relationship between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e, such as the injection-enhanced gate transistor (IEGT)[\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e], the partially narrow mesa IGBT (PNM-IGBT)[\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e], the carried-stored trench-gate bipolar transistor (CSTBT)[\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e], Superjunction IGBT (SJ-IGBT)[\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e], Trench Shielded Planar gate IGBT (TSPG-IGBT)[\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e], and CSTBT with stepped split trench-gate (SSG-CSTBT)[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]. By modulating the carrier distribution in the on-state, IEGT, PNM-IGBT, and CSTBT reduce the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e significantly. Additionally, adjusting the gate structure to reduce gate charge or optimizing the gate control strategy have led to a noteworthy reduction in switching losses of these devices[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e], [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e], [\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e], [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e], [\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eIn order to improve short-circuit capability, many structures have been proposed[\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e], [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e], [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e], [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e], [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e], [\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e], [\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e], [\u003cspan citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e], [\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e]. Notably, among these structures, an additional diode or MOSFET has been employed to clamp the potential of the nMOS intrinsic drain in IGBT or suppress the saturation current, which serves to extends the short-circuit withstand time.\u003c/p\u003e \u003cp\u003eHowever, considering that higher doped N-CS layer in the CSTBT may degrade the breakdown voltage (\u003cem\u003eBV\u003c/em\u003e), the doping concentration of N-CS layer is limited. To achieve a well-balanced \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e - \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e - SCSOA tradeoff relationship without \u003ca class=\"FNLink\" href=\"#Fn1\" id=\"#FNLinkFn1\"\u003e\u003c/a\u003ecompromising \u003cem\u003eBV\u003c/em\u003e characteristics, a novel deep trench CSTBT (DT-CSTBT) with self-biased pMOS has been proposed and studied by TCAD tools.\u003c/p\u003e"},{"header":"II. DEVICE STRUCTURE AND PRINCIPLE","content":"\u003cp\u003eAs shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(b), our proposed DT-CSTBT has the same trench gate as the conventional CSTBT which is shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(a). In the CSTBT structure, the N-CS layer below the P-well region can increase the carrier concentration at the emitter side. To shield the undesirable effect of the highly doped N-CS layer on BV, the proposed DT-CSTBT features emitter trenches and the P-layer. The P-layer, N-CS layer, P-well, as well as the emitter collectively constitute a self-biased pMOS. The equivalent circuit of the proposed structure includes a nMOS, a pMOS, and a PNP bipolar transistor, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(c).\u003c/p\u003e \u003cp\u003eIn the off-state, compared to the conventional CSTBT structure that utilizes the P-well/N-CS junction (\u003cem\u003eJ\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e) to withstand the voltage, the voltage of the DT-CSTBT is mainly sustained by the P-layer/N-Drift junction (\u003cem\u003eJ\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e). In addition, as the potential of the collector increases, the potential of the N-CS layer in the DT-CSTBT also increases. When the potential rises to the threshold voltage of pMOS, a hole channel is established in the N-CS layer close to the emitter trench, causing the pMOS to turn on automatically. This hole channel connects the P-layer to the emitter, effectively clamping the potential of both the P-layer and N-CS layer to a low value by this self-biased pMOS. By virtue of \u003cem\u003eJ\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e withstanding high voltage and the presence of self-biased pMOS, there is no high electric field in the region near the gate of the proposed DT-CSTBT. Consequently, the N-CS layer can be highly doped without damaging breakdown characteristics.\u003c/p\u003e \u003cp\u003eSimilarly, the self-biased pMOS turns on as the potential of the collector rises in the on-state. The clamped potential in the N-CS layer depends on the threshold voltage of the pMOS. Since the N-CS layer acts as the intrinsic drain of the nMOS, maintaining a low clamped potential enables the proposed structure to operate at a reduced saturation current. The higher doped N-CS layer enhances the conductance modulation and reduces the Von in the on-state.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e"},{"header":"III. RESULTS AND DISCUSSION","content":"\u003cp\u003eThe simulations have been completed by using the Sentaurus TCAD tool. Figure\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e describes the fabrication flow of the proposed DT-CSTBT. The key simulation parameters of DT-CSTBT and Conventional CSTBT are listed in Table\u0026nbsp;1. In order to reduce the threshold voltage of the pMOS, the thickness of oxide at the emitter trench is set to 25nm.\u003c/p\u003e \u003cp\u003eTABLE Ⅰ. KEY DEVICE PARAMETERS\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"No\" id=\"Taba\" border=\"1\"\u003e \u003ccolgroup cols=\"3\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eParameter\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eConventional\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eDT-CSTBT\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eGate oxide thickness, \u003cem\u003eT\u003c/em\u003e\u003csub\u003eOX\u003c/sub\u003e (nm)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e120\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e120\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eTrench Emitter depth, \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e (\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6.4\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eP-well depth, \u003cem\u003ed\u003c/em\u003e\u003csub\u003ePW\u003c/sub\u003e (\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e2.5\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e2.5\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eN-CS thickness, \u003cem\u003eT\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e(\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\approx\\)\u003c/span\u003e\u003c/span\u003e1\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\approx\\)\u003c/span\u003e\u003c/span\u003e1\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eN-CS doping, \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e (cm\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e1e16\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1e17\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eP-layer thickness, \u003cem\u003eT\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e(\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eP-layer dose, \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e(cm\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e-\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6e14\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eSubstrate thickness, \u003cem\u003eT\u003c/em\u003e\u003csub\u003eSUB\u003c/sub\u003e(\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e115\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e115\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eN-Drift doping, \u003cem\u003eN\u003c/em\u003e\u003csub\u003eND\u003c/sub\u003e(cm\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e1e14\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1e14\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eN-FS dose, \u003cem\u003eN\u003c/em\u003e\u003csub\u003eFS\u003c/sub\u003e(cm\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e2e16\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e2e16\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eP-collector dose, \u003cem\u003eN\u003c/em\u003e\u003csub\u003ePC\u003c/sub\u003e(cm\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e4e17\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e4e17\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003eCell pitch, \u003cem\u003eW\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e (\u0026micro;m)\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e3\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e3\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003c/br\u003e\n\u003cp\u003e\u003cspan\u003e\u003cem\u003eA. Static characteristics\u003c/em\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003eThe potential distributions at the emitter side in the off-state are shown in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e. The self-biased pMOS in the proposed DT-CSTBT turns on at high reverse bias voltage. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e(b), even if the proposed structure is under a high voltage of 600V, the potentials at each point (A, B, C) are all below 2V. This indicates that the self-biased pMOS functions well as the potential clamping or potential shielding.\u003c/p\u003e\n\u003cp\u003eIn the off-state, the voltage of the proposed DT-CSTBT is mainly sustained by the P-layer/N-Drift junction. Thus, the location of the peak electric field shifts to the right, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e(a). The electric field distributions at the emitter side in both structures are shown in Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e(b) and (c). Thanks to the potential clamping in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e(b), the electric field near the gate in the proposed structure is also significantly reduced. Specifically, the electric field below the trench gate is only 124 V/cm at high reverse bias voltage, which is about 3 orders of magnitude lower than the same position in the conventional structure ( 218498V/cm ). This signifies a notable improvement in gate reliability for the proposed DT-CSTBT.\u003c/p\u003e\n\u003cp\u003eThe tradeoff relationship between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eBV\u003c/em\u003e is studied and the simulation results are shown in Fig. \u003cspan class=\"InternalRef\"\u003e5\u003c/span\u003e. \u003cem\u003eBV\u003c/em\u003e remains almost constant and meets the 1200V voltage class in the proposed structure when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e decreases continuously. Due to the shielding effect of self-biased pMOS in Fig. \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e(c), a low \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of 1.201V is achieved while maintaining \u003cem\u003eBV\u003c/em\u003e at 1600V. In contrast, the conventional structure experiences a decrease in \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e from 1.614V to 1.206V as \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e increases (from 1.0\u0026times;10\u003csup\u003e16\u003c/sup\u003e cm\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e to 5.0\u0026times;10\u003csup\u003e17\u003c/sup\u003e cm\u003csup\u003e\u0026minus;\u0026thinsp;3\u003c/sup\u003e). However, its \u003cem\u003eBV\u003c/em\u003e decreases dramatically from 1762 V to 32 V. The feasibility of higher \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e in the proposed structure is verified.\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e6\u003c/span\u003e shows the distributions of the hole concentration in the on-state along line AA\u0026rsquo; in Fig. \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e ( \u003cem\u003eI\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e = 200 A/cm\u003csup\u003e2\u003c/sup\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eGE\u003c/sub\u003e =15 V ). The DT-CSTBT with a higher \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e forms a more robust hole barrier and can effectively block a greater number of holes. The conductance modulation in the proposed structure is greatly enhanced.\u003c/p\u003e\n\u003cp\u003eAt point A in Fig. \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e, corresponding to the intrinsic drain of nMOS, the potential in the proposed DT-CSTBT is about 6V lower than that in the traditional CSTBT. Figure \u003cspan class=\"InternalRef\"\u003e7\u003c/span\u003e compares the forward conduction characteristics, revealing a 40.3% reduction in the saturation current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e, at \u003cem\u003eV\u003c/em\u003e\u003csub\u003eCE\u003c/sub\u003e =10 V) of the proposed DT-CSTBT attributable to the lower potential at the intrinsic drain of the nMOS. Besides, the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of the proposed structure is 1.447 V, indicating a 10.3% reduction compared to the 1.614 V observed in the conventional CSTBT.\u003c/p\u003e\n\u003cp\u003e\u003cspan\u003e\u003cem\u003eB. Short-circuit characteristics\u003c/em\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e(a) compares the short-circuit characteristics of the two structures. The simulation test circuit of the short-circuit characteristics is shown in Fig. \u003cspan class=\"InternalRef\"\u003e8\u003c/span\u003e(b). The \u003cem\u003et\u003c/em\u003e\u003csub\u003eSC\u003c/sub\u003e of the proposed DT-CSTBT is 13.1 \u0026micro;s, representing a 23.5% improvement over the conventional CSTBT (10.6 \u0026micro;s). The \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e is reduced due to the potential clamping, contributing to the enlargement of the SCSOA for the proposed structure.\u003c/p\u003e\n\u003cp\u003e\u003cspan\u003e\u003cem\u003eC. Transient characteristics\u003c/em\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003eThe turn-off characteristics of the two structures are also studied, with the turn-off waves shown in Fig. \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e(a), and the turn-off test circuit shown in Fig. \u003cspan class=\"InternalRef\"\u003e9\u003c/span\u003e(b). Notably, there is a larger and longer current tail in the conventional CSTBT. This suggests that the self-biased pMOS also promotes the extraction of hole to reduce \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e during the turn-off.\u003c/p\u003e\n\u003cp\u003eBy adjusting the doping dose of P\u003csup\u003e+\u003c/sup\u003e at the collector side (from 5.0\u0026times;10\u003csup\u003e12\u003c/sup\u003e cm\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e to 1.0\u0026times;10\u003csup\u003e14\u003c/sup\u003e cm\u003csup\u003e\u0026minus;\u0026thinsp;2\u003c/sup\u003e), the simulation of the switching characteristics is performed to obtain the tradeoff relationships as shown in Fig. \u003cspan class=\"InternalRef\"\u003e10\u003c/span\u003e. At the same \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e (about 1.45 V), the \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e of the proposed structure is reduced by 23.2% compared to the conventional structure. The \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e is reduced by 10.3% from 1.614V to 1.447V at the same \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e. The tradeoff relationship between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e of the proposed DT-CSTBT is significantly improved.\u003c/p\u003e\n\u003cp\u003e\u003cspan\u003e\u003cem\u003eD. Influence of D\u003c/em\u003e \u003csub\u003ePL\u003c/sub\u003e \u003cem\u003eand d\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e\u003c/span\u003e\u003c/p\u003e\n\u003cp\u003eThe emitter trench and the P-layer are introduced to protect the N-CS layer and form a self-biased pMOS to maintain a low \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e. Since the depth of the emitter trench ( \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e ) affects the position of the withstand voltage junction \u003cem\u003eJ\u003c/em\u003e\u003csub\u003e\u003cem\u003e2\u003c/em\u003e\u003c/sub\u003e, and the dose of P-layer ( \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e ) affects the electric field distribution in the depletion region and charge balance, the performances of DT-CSTBT under different \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e and \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e are also studied.\u003c/p\u003e\n\u003cp\u003eThe depth of the emitter trench hardly affects conductance modulation or hole extraction. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e11\u003c/span\u003e(a), different depths of the emitter trench have little influence on \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e. The deeper emitter also results in an enhanced potential shielding of the self-biased pMOS.\u003c/p\u003e\n\u003cp\u003eThe high potential region is further away from the nMOS. Therefore, \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e of the proposed DT-CSTBT decreases with increasing \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e, as shown in Fig. \u003cspan class=\"InternalRef\"\u003e11\u003c/span\u003e(b). However, the deeper emitter causes the junction that withstands voltage to shift downward, which corresponds to a thinning of the N-Drift region. As a result, the \u003cem\u003eBV\u003c/em\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e inevitably decrease with increasing \u003cem\u003ed\u003c/em\u003e\u003csub\u003e\u003cem\u003eTE\u003c/em\u003e\u003c/sub\u003e, shown in Fig. \u003cspan class=\"InternalRef\"\u003e11\u003c/span\u003e(b).\u003c/p\u003e\n\u003cp\u003eHigh \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e is observed to enhance hole extraction, subsequently weakening the conductance modulation effect. As shown in Fig. \u003cspan class=\"InternalRef\"\u003e12\u003c/span\u003e(a), an increase in \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e results in an elevation of \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e, while \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e concurrently decreases. In Fig. \u003cspan class=\"InternalRef\"\u003e12\u003c/span\u003e(b), a consistent reduction in \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e is observed with increasing \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e. Due to charge imbalance, \u003cem\u003eBV\u003c/em\u003e initially decreases and subsequently rises as \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e increases.\u003c/p\u003e\n\u003cp\u003eThus, a better tradeoff between \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e can be obtained by properly increasing the \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e and \u003cem\u003eD\u003c/em\u003e\u003csub\u003ePL\u003c/sub\u003e. This also leads to smaller \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e, ensuring a larger SCSOA. Although decreases with increasing \u003cem\u003ed\u003c/em\u003e\u003csub\u003eTE\u003c/sub\u003e, \u003cem\u003eBV\u003c/em\u003e still meets the 1200V voltage class.\u003c/p\u003e"},{"header":"IV. CONCLUSION","content":"\u003cp\u003eIn this work, a novel DT-CSTBT features the emitter trenches and P-layer has been proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, exhibits an excellent potential clamping effect. Under the clamping effect, both the potential and the electric field in the region near the gate decrease dramatically. The extremely low potential at the N-CS layer leads to a suppressed \u003cem\u003eI\u003c/em\u003e\u003csub\u003edsat\u003c/sub\u003e and a 23.5% enlarged SCSOA. It ensures the better reliability of the gate and the feasibility of higher \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e due to the high electric field away from the gate. Moreover, the proposed DT-CSTBT achieves a 23.2% reduction in \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e at the same \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e. A \u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e tradeoff is effectively managed with the help of higher \u003cem\u003eN\u003c/em\u003e\u003csub\u003eCS\u003c/sub\u003e and a hole path through the self-biased pMOS. In summary, the improved reliability and reduced losses position the proposed DT-CSTBT as a promising candidate for application in power electronic systems.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003e\"J.Guo, H.Xu and Y. Yang wrote the main manuscript text and Z. Qian, X. Chen prepared the figures. All authors reviewed the manuscript.\"\u003c/p\u003e\u003ch2\u003eData Availability\u003c/h2\u003e\u003cp\u003eAll data generated or analysed during this study are included in this published article.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eN. Iwamuro and T. Laska, \u0026ldquo;IGBT History, State-of-the-Art, and Future Prospects,\u0026rdquo; IEEE Trans. Electron Devices, vol. 64, no. 3, pp. 741\u0026ndash;752, Mar. 2017, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2017.2654599\u003c/span\u003e\u003cspan address=\"10.1109/TED.2017.2654599\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eM. Kitagawa, I. Omura, S. Hasegawa, T. Inoue, and A. Nakagawa, \u0026ldquo;A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor,\u0026rdquo; in \u003cem\u003eProceedings of IEEE International Electron Devices Meeting\u003c/em\u003e, Dec. 1993, pp. 679\u0026ndash;682. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM.1993.347221\u003c/span\u003e\u003cspan address=\"10.1109/IEDM.1993.347221\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eM. Sumitomo, J. Asai, H. Sakane, K. Arakawa, Y. Higuchi, and M. Matsui, \u0026ldquo;Low loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT),\u0026rdquo; in \u003cem\u003e2012 24th International Symposium on Power Semiconductor Devices and ICs\u003c/em\u003e, Bruges, Belgium: IEEE, Jun. 2012, pp. 17\u0026ndash;20. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD.2012.6229012\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD.2012.6229012\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Takahashi, H. Haruguchi, H. Hagino, and T. Yamada, \u0026ldquo;Carrier stored trench-gate bipolar transistor (CSTBT)-a novel power device for high voltage application,\u0026rdquo; in \u003cem\u003e8th International Symposium on Power Semiconductor Devices and ICs. ISPSD \u0026rsquo;96. Proceedings\u003c/em\u003e, May 1996, pp. 349\u0026ndash;352. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD.1996.509513\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD.1996.509513\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eF. D. Bauer, \u0026ldquo;The super junction bipolar transistor: a new silicon power device concept for ultra low loss switching applications at medium to high voltages,\u0026rdquo; Solid-State Electron., vol. 48, no. 5, pp. 705\u0026ndash;714, May 2004, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1016/j.sse.2003.09.017\u003c/span\u003e\u003cspan address=\"10.1016/j.sse.2003.09.017\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eJ. Hu, M. Bobde, H. Yilmaz, and A. Bhalla, \u0026ldquo;Trench shielded planar gate IGBT (TSPG-IGBT) for low loss and robust short-circuit capalibity,\u0026rdquo; in \u003cem\u003e2013 25th International Symposium on Power Semiconductor Devices \u0026amp; IC\u0026rsquo;s (ISPSD)\u003c/em\u003e, May 2013, pp. 25\u0026ndash;28. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD.2013.6694390\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD.2013.6694390\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Xu, Y. Yang, J. Tan, H. Zhu, Q.-Q. Sun, and D. W. Zhang, \u0026ldquo;Carrier Stored Trench-Gate Bipolar Transistor With Stepped Split Trench-Gate Structure,\u0026rdquo; IEEE Trans. Electron Devices, pp. 1\u0026ndash;6, 2022, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2022.3200645\u003c/span\u003e\u003cspan address=\"10.1109/TED.2022.3200645\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eW. Saito and S.-I. Nishizawa, \u0026ldquo;Improvement Design for Turn-On Switching Characteristics in Surface Buffer Insulated Gate Bipolar Transistor,\u0026rdquo; \u003cem\u003eIEEE Electron Device Lett.\u003c/em\u003e, vol. 41, no. 12, pp. 1814\u0026ndash;1816, Dec. 2020, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/LED.2020.3034898\u003c/span\u003e\u003cspan address=\"10.1109/LED.2020.3034898\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eJ. Zhang, X. Xiao, R. Zhu, Q. Zhao, and B. Zhang, \u0026ldquo;Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench,\u0026rdquo; IEEE J. Electron Devices Soc., vol. 9, pp. 704\u0026ndash;712, 2021, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/JEDS.2021.3097388\u003c/span\u003e\u003cspan address=\"10.1109/JEDS.2021.3097388\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eX. Luo \u003cem\u003eet al.\u003c/em\u003e, \u0026ldquo;A Low Loss and On-State Voltage Superjunction IGBT with Depletion Trench,\u0026rdquo; in \u003cem\u003e2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, Vienna, Austria: IEEE, Sep. 2020, pp. 130\u0026ndash;133. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD46842.2020.9170193\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD46842.2020.9170193\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eT. Sakano, K. Takao, Y. Iwakaji, H. Itokazu, and T. Matsudai, \u0026ldquo;Ultra-Low Switching Loss Triple-Gate controlled IGBT,\u0026rdquo; in \u003cem\u003e2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, Nagoya, Japan: IEEE, May 2021, pp. 363\u0026ndash;366. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.23919/ISPSD50666.2021.9452246\u003c/span\u003e\u003cspan address=\"10.23919/ISPSD50666.2021.9452246\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eW. Saito and S.-I. Nishizawa, \u0026ldquo;Alternated Trench-Gate IGBT for Low Loss and Suppressing Negative Gate Capacitance,\u0026rdquo; \u003cem\u003eIEEE Trans. Electron Devices\u003c/em\u003e, vol. 67, no. 8, pp. 3285\u0026ndash;3290, Aug. 2020, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2020.3002510\u003c/span\u003e\u003cspan address=\"10.1109/TED.2020.3002510\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eT. Sakano \u003cem\u003eet al.\u003c/em\u003e, \u0026ldquo;Three-level Gate Drive Technique for Enhancing Switching Loss Reduction in Triple-Gate IGBTs,\u0026rdquo; in \u003cem\u003e2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, May 2022, pp. 117\u0026ndash;120. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD49238.2022.9813666\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD49238.2022.9813666\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eK. Konishi, K. Nishi, K. Sako, and A. Furukawa, \u0026ldquo;Split-Dummy-Active CSTBT\u003csup\u003e\u0026trade;\u003c/sup\u003e for Improving Recovery dV/dt and Turn-on Switching Loss Tradeoff,\u0026rdquo; in \u003cem\u003e2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, May 2022, pp. 273\u0026ndash;276. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD49238.2022.9813634\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD49238.2022.9813634\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eR. Kamibaba, K. Konishi, Y. Fukada, A. Narazaki, and M. Tarutani, \u0026ldquo;Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology,\u0026rdquo; in 2015 \u003cem\u003eIEEE 27th International Symposium on Power Semiconductor Devices \u0026amp; IC\u0026rsquo;s (ISPSD)\u003c/em\u003e, May 2015, pp. 29\u0026ndash;32. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD.2015.7123381\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD.2015.7123381\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eR. Bhojani, J. Lutz, R. Baburske, H.-J. Schulze, and F.-J. Niedemostheide, \u0026ldquo;A novel Injection Enhanced Floating Emitter (IEFE) IGBT structure improving the ruggedness against short-circuit and thermal destruction,\u0026rdquo; in 2017 \u003cem\u003e29th International Symposium on Power Semiconductor Devices and IC\u0026rsquo;s (ISPSD)\u003c/em\u003e, May 2017, pp. 113\u0026ndash;116. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.23919/ISPSD.2017.7988939\u003c/span\u003e\u003cspan address=\"10.23919/ISPSD.2017.7988939\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Xu, D.-H. Zhao, H. Zhu, Q.-Q. Sun, and D. W. Zhang, \u0026ldquo;A process optimization method for carrier stored trench bipolar transistor (CSTBT) device,\u0026rdquo; in 2021 \u003cem\u003eIEEE 14th International Conference on ASIC (ASICON)\u003c/em\u003e, Oct. 2021, pp. 1\u0026ndash;4. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ASICON52560.2021.9620236\u003c/span\u003e\u003cspan address=\"10.1109/ASICON52560.2021.9620236\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eS. Zhang \u003cem\u003eet al.\u003c/em\u003e, \u0026ldquo;A High-voltage Silicon-On-Insulator Lateral IGBT with Segmented Trenches for Improved Short circuit Ruggedness,\u0026rdquo; in \u003cem\u003e2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, May 2022, pp. 309\u0026ndash;312. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD49238.2022.9813658\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD49238.2022.9813658\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eH. Xu et al., \"A Low Conduction Loss IGBT With Hole Path and Temperature Sensing,\" in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5236\u0026ndash;5241, Oct. 2023, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2023.3306734\u003c/span\u003e\u003cspan address=\"10.1109/TED.2023.3306734\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eB. Yi, X. Xie, M. Kong, J. Cheng, and X. Chen, \u0026ldquo;A Novel Diode-Clamped Carrier Stored Trench IGBT With Improved Performances,\u0026rdquo; \u003cem\u003eIEEE Trans. Electron Devices\u003c/em\u003e, vol. 67, no. 1, pp. 243\u0026ndash;248, Jan. 2020, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2019.2955820\u003c/span\u003e\u003cspan address=\"10.1109/TED.2019.2955820\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eP. Li, M. Kong, and X. Chen, \u0026ldquo;A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current,\u0026rdquo; in 2016 \u003cem\u003e28th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\u003c/em\u003e, Jun. 2016, pp. 307\u0026ndash;310. doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ISPSD.2016.7520839\u003c/span\u003e\u003cspan address=\"10.1109/ISPSD.2016.7520839\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eJ. Wei, S. Zhang, X. Luo, D. Fan and B. Zhang, \"Low Switching Loss and EMI Noise IGBT With Self-Adaptive Hole-Extracting Path,\" in IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2572\u0026ndash;2576, May 2021, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/TED.2021.3065898\u003c/span\u003e\u003cspan address=\"10.1109/TED.2021.3065898\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"scientific-reports","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scirep","sideBox":"Learn more about [Scientific Reports](http://www.nature.com/srep/)","snPcode":"","submissionUrl":"","title":"Scientific Reports","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Scientific Reports","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"CSTBT, self-biased pMOS, saturation current, turn-off loss, short-circuit safe operating area","lastPublishedDoi":"10.21203/rs.3.rs-4609119/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4609119/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eIn this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current under the clamping effect, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e) and turn-off loss (\u003cem\u003eE\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e) of the new structure is also improved by 23.2% compared with the conventional CSTBT.\u003c/p\u003e","manuscriptTitle":"A novel Self-Biased pMOS Clamped Deep Trench CSTBT with Enhanced Short-Circuit Capability","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-07-12 08:41:45","doi":"10.21203/rs.3.rs-4609119/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2024-10-29T07:28:03+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2024-10-29T01:33:10+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"165474219485916435686403629078794080797","date":"2024-10-23T01:02:59+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"48262222442208777249872409444734495303","date":"2024-07-10T14:37:02+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2024-06-27T11:24:47+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"85479597162258235376076322522347052979","date":"2024-06-27T02:20:48+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2024-06-24T14:21:25+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2024-06-24T14:13:20+00:00","index":"","fulltext":""},{"type":"editorInvited","content":"","date":"2024-06-24T09:58:49+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2024-06-21T12:06:58+00:00","index":"","fulltext":""},{"type":"submitted","content":"Scientific Reports","date":"2024-06-20T04:40:14+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"scientific-reports","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"scirep","sideBox":"Learn more about [Scientific Reports](http://www.nature.com/srep/)","snPcode":"","submissionUrl":"","title":"Scientific Reports","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Scientific Reports","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"f0adb396-4fed-413f-99bc-1322583e5598","owner":[],"postedDate":"July 12th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":34406936,"name":"Physical sciences/Engineering/Electrical and electronic engineering"},{"id":34406937,"name":"Physical sciences/Physics/Electronics photonics and device physics"}],"tags":[],"updatedAt":"2025-01-13T16:03:16+00:00","versionOfRecord":{"articleIdentity":"rs-4609119","link":"https://doi.org/10.1038/s41598-025-85530-0","journal":{"identity":"scientific-reports","isVorOnly":false,"title":"Scientific Reports"},"publishedOn":"2025-01-08 15:57:46","publishedOnDateReadable":"January 8th, 2025"},"versionCreatedAt":"2024-07-12 08:41:45","video":"","vorDoi":"10.1038/s41598-025-85530-0","vorDoiUrl":"https://doi.org/10.1038/s41598-025-85530-0","workflowStages":[]},"version":"v1","identity":"rs-4609119","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4609119","identity":"rs-4609119","version":["v1"]},"buildId":"qtupq5eGEP_6zYnWcrvyt","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}