Design and Implementation of Full Adder Using Negative Differential Resistance Circuits Based on CMOS Process

Abstract We demonstrate a full adder design based on several MOS-NDR circuits connected in series and in parallel. A basic MOS-NDR circuit is made of thee standard Si-based metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. By adjusting the appropriate parameters of the gate width of the MOSFET, the Λ-type negative differential resistance (NDR) characteristic can be presented in its combined current-voltage (I-V) curve. The operating principle of this 1-bit full adder is based on the theory of monostable-bistable transmission logic gate (MOBILE). The bias voltage of this circuit is a clock signal, and its output voltage is a low or high logic level determined by the relative current peak conditions of the load and driver components of the MOBILE circuit. Most of the NDR-based applications designed in the general literature use resonant tunnel diode (RTD) devices as the main components. Compared with RTD device, our MOS-NDR circuit can be designed with standard CMOS process and simulated with HSPICE. We implement this full adder using 0.18 µm standard CMOS process.