Enhancing luminance response during gray-level transitions at low frequencies in AMOLED displays

Enhancing luminance response during gray-level transitions at low frequencies in AMOLED displays | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Enhancing luminance response during gray-level transitions at low frequencies in AMOLED displays Dong Sup Sim, Sun Min Song, Jun Hwan Noh, I. Sak Lee, Nack Bong Choi, and 2 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7919372/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 9 You are reading this latest preprint version Abstract This study proposes a novel driving method to address temporal response degradation observed during gray-level transitions under low-frequency operation in low-temperature poly-Si and oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) displays. Through experimental investigation, we demonstrate that the delayed response is primarily attributed to the hysteresis behavior of the driving thin-film transistor (D-TFT), leading to a threshold voltage (VTH) shift and delayed recovery during black-to-white transitions (i.e., gray-level transition). Moreover, the VTH shift can distort the parasitic coupling effect during the programming phase, leading to further degradation in temporal response. To mitigate this issue, we evaluate two approaches, increasing a reset voltage and introducing short-duration high-frequency frame insertion during gray-level transitions to facilitate rapid VTH recovery. Through this, we demonstrate that while both methods improve the luminance response, the frame insertion technique achieves superior performance particularly in luminance stability. This frame insertion method improved the first-second luminance response from 68.1% to 98.2%, while achieving this enhancement with only a 0.6% increase in power consumption through power-efficient optimization. This approach significantly enhances display performance under low-refresh-rate operation, such as in always-on display (AoD) modes. Organic light-emitting diode (OLED) Low- temperature poly-Si and oxide (LTPO) Luminance response Hysteresis Parasitic coupling effect Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 1. Introduction The growing adoption of smartwatches, foldable phones, and other portable electronic devices has significantly increased the demand for low-power display technologies [ 1 ]–[ 4 ]. To reduce power consumption while maintaining high display quality, low-temperature poly-Si and oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) displays have emerged as a key solution. As illustrated in Fig. 1 (a), by combining poly-Si-based driving thin-film transistors (D-TFTs) with oxide-based switching TFTs (S-TFTs), LTPO enables dynamic refresh rate control, allowing seamless transitions between high and low frame rates, such as from 120 Hz to 1 Hz [ 5 ]–[ 8 ]. However, as illustrated in Fig. 1 (b), temporal response degradation under low-frequency operation, particularly at 1 Hz in always-on display (AoD) mode, has become a critical issue, leading to visible gray-level transition delays and perceived deterioration in display quality [ 9 ]–[ 11 ]. This degradation primarily originates from the hysteresis behavior of the poly-Si-based D-TFT, which induces threshold voltage (V TH ) shift and delayed recovery [ 12 ]–[ 15 ]. These effects not only delay the restoration of the transistor's operating point but also weaken the parasitic coupling effect during the programming phase due to changes in the gate-to-source voltage range of the oxide-based S-TFT. Consequently, the final gate voltage after black-to-white transitions (i.e., gray-level transition) becomes higher than that of a steady white state, further degrading the temporal luminance response. Various compensation techniques have been proposed to address these issues [ 16 ]–[ 19 ]. However, most are optimized for high-refresh-rate operation and lack effectiveness in low-frequency scenarios. In particular, conventional driving schemes are unable to effectively accelerate V TH recovery within the limited time frame of 1 Hz frame updates. To overcome these limitations, this study proposes a short-duration high-frequency frame insertion technique during gray-level transitions. By momentarily increasing the frame rate during the transition period, the method facilitates rapid V TH recovery in the D-TFT. The proposed approach is validated using actual LTPO AMOLED display panels, and its effectiveness in improving temporal response under 1 Hz operation is experimentally verified. 2. Experiments A 6.7-inch LTPO AMOLED display with quad high definition (QHD) resolution was used in the experiments. Figure 2 (a) illustrates the 8T1C compensation pixel circuit employed in the test panel. In this structure, T2 and T3 transistors, which are connected to the gate node of the D-TFT, are implemented using oxide TFTs with low leakage characteristics, suitable for low-frequency operation. The remaining transistors are composed of p-type low-temperature poly-Si (LTPS) TFTs. V DD and V SS denote the supply voltages, and V INT , V RST , and V DATA represent the initialization voltage, reset voltage, and data voltage, respectively. C STG indicates storage capacitance. Figure 2 (b) shows the gate signal control scheme of the pixel circuit. Each refresh frame is divided into four sequential phases: initialization, programming, reset, and emission. In contrast, each skip frame consists only of the reset and emission phases. During the initialization phase, all internal nodes (Node 1–Node 4) are reset to eliminate the influence of the data voltage stored in the previous frame. In the programming phase, a diode-connection configuration is used to compensate for the V TH of the D-TFT, and the data voltage for the next frame is charged to the D-TFT gate node. In the reset phase, a high voltage is applied to the source node of the D-TFT to mitigate V TH variation caused by hysteresis effects that may occur between refresh and skip frames. When all 120 frames within 1-second period are configured as refresh frames without any skip frames, the display operates at 120 Hz. Conversely, when only one refresh frame is used along with 119 skip frames, the panel operates at 1 Hz. As the number of skip frames increases, power consumption decreases, but visual quality tends to degrade. Figure 3 presents the measured luminance responses during gray-level transitions from black to white. Optical measurements were conducted at the center of the panel using a KONICA MINOLTA CA-427, with a sampling rate of 3 kHz. To eliminate unwanted high-frequency fluctuations, the normalized luminance was smoothed using a moving average filter equivalent to one frame at 120 Hz. As shown in Fig. 3 (a), the panel exhibited a fast luminance response under 120 Hz operation. In contrast, Fig. 3 (b) demonstrates a significantly slower response under 1 Hz operation, with luminance taking several seconds to reach the steady state. To quantify this difference, we define the first-second response (FSR) as follows: FSR = \(\:\frac{{\sum\:}_{t=1}^{2}Measured\:data}{{\sum\:}_{t=8}^{9}Reference\:data}*100\:\left[\%\right]\) Here, the measured data corresponds to the luminance values acquired during the first second after the gray-level transition from black to white, and the reference data corresponds to the steady-state luminance measured at 120 Hz under white display conditions. 3. Results and discussion To investigate the hysteresis behavior of the D-TFT, a transient response measurement was conducted by switching the gate voltage from the off-state to the on-state and monitoring the drain current. As shown in Fig. 4 (a), the drain current initially surged in response to the gate voltage change, then gradually settled to a steady state. This behavior indicates that when the gray-level transitions from black to white, the V TH of the D-TFT experiences a positive shift, followed by a gradual recovery over time. Figure 4 (b) illustrates the luminance response and V TH variation of the D-TFT during the black-to-white transition. During the programming phase, the positive V TH shift increases the D-TFT gate voltage, leading to a reduced luminance peak. Subsequently, during the emission phase, as V TH recovers, the luminance gradually decreases, exhibiting a luminance decay behavior. Figure 5 illustrates the mechanism responsible for the reduced luminance peak during the programming phase and the luminance decay during the emission phase following a black-to-white transition. Figure 5 (a) depicts the gate-to-source capacitance (C GS ) of transistor T3 during the programming phase. As shown in Fig. 5 (b), C GS is not constant but varies with V GS . Due to a positive shift in V TH of the D-TFT, the drain current increases, raising the gate voltage of the D-TFT during programming. Consequently, when the scan signal (Scan 3) transitions from high to low after programming, the V GS transition range experiences a negative shift while maintaining a constant voltage range. This shift leads to a reduction in the on-state capacitance ratio. The resulting voltage shift at node 2 (ΔV S ) of T3 can be described by the following equation: △V S = \(\:\frac{{C}_{GS}}{({C}_{GS}\:+\:{C}_{STG})}*△{V}_{G}\) Given that C STG is significantly larger than C GS , this can be approximated as: △V S = \(\:\frac{{C}_{GS}}{{C}_{STG}}*△{V}_{G}\) As the scan signal V G changes, this transition occurs at a lower C GS region, thereby weakening the kickback noise. Figure 5 (c) shows that due to the reduced kickback, the gate voltage of the D-TFT is set higher than its steady-state value after programming, resulting in a reduced luminance peak. Figure 5 (d) illustrates the mechanism behind the luminance decay observed during the emission phase. As the V TH of the D-TFT gradually recovers with a negative shift, the drain current decreases accordingly, leading to a reduction in luminance. To mitigate the hysteresis-induced effects of the D-TFT, two evaluation experiments were conducted. In the first experiment, the V RST applied through T4 and the Scan 4 signal was increased to investigate its impact on luminance response. Increasing V RST induces a stronger on-bias across the D-TFT before and after programming, which helps to suppress the influence of the previous frame’s black V DATA . As shown in Fig. 6 (a), increasing a reset voltage from 5 V to 6 V improves the reduced luminance peak. However, the luminance decay remains significant during the emission phase. In the second experiment, short-duration high-frequency frame insertion was applied at 10 Hz for a duration of 1 second during the black-to-white transition to increase the number of reset operations. As shown in Fig. 6 (b), although the reduced luminance peak remained in the first frame, the luminance rapidly recovers from the second frame onward, resulting in a significant improvement in the FSR from 59.3% to 95.0%. Figure 6 (c) illustrates this fast driving method, which uses short-duration high-frequency frame insertion. Figure 7 (a) illustrates the correlation between the FSR and the fast-driving conditions, specifically the frequency and insertion duration of high-frequency frames. Measurements were conducted on 30 display panels. The results show that higher driving frequencies and longer insertion durations lead to improved FSR performance. Figure 7 (b) presents the relationship between power consumption and fast-driving conditions over a 1-minute interval, which corresponds to the time update cycle in AoD mode. As with the FSR test, 30 display panels were evaluated. Among the conditions with no visibly noticeable delay, the configuration with a 30 Hz frequency and a 0.6-second insertion time was identified as optimal. Figure 7 (c) shows the 1 Hz luminance response during a black-to-white transition, while Fig. 7 (d) presents the luminance response under the fast-driving condition of 30 Hz for 0.6 s. In this case, power consumption increased by only 0.6%, while the FSR significantly improved from 68.1% to 98.2%. 4. Conclusion This study proposed a short-duration high-frequency frame insertion method to mitigate the temporal luminance degradation observed during gray-level transitions in low-frequency LTPO AMOLED display operation. Through experimental analysis, it was confirmed that the delayed luminance response at 1 Hz operation primarily originates from the hysteresis-induced V TH shift of the p-channel LTPS D-TFT. This shift weakens the parasitic coupling effect during the programming phase, resulting in an increased gate voltage and reduced initial luminance. Furthermore, as V TH gradually recovers during the emission phase, less current flows through the D-TFT and luminance gradually decreases. To address this issue, we introduced a fast-driving scheme by inserting high-frequency frames during the gray-level transition phase. The proposed method facilitates rapid V TH recovery and improves the luminance response without significantly increasing power consumption. Among various driving conditions tested across 30 display panels, the 30 Hz for 0.6 s configuration was identified as optimal, achieving a substantial improvement in the FSR from 68.1% to 98.2% with only a 0.6% increase in power consumption. This approach is especially effective in AoD applications, where low-refresh-rate operation is essential, and can be widely adopted to enhance image quality in advanced low-power display systems. Declarations Author Contribution Dong Sup Sim: conceptualization (lead); data curation (lead); formal analysis (lead); investigation (lead); methodology (lead); resources (equal); software (lead); validation (lead); visualization (lead); writing—original draft (lead); writing—review & editing (lead). Sun Min Song, Jun Hwan Noh, and I. Sak Lee: formal analysis (supporting); investigation (supporting); visualization (supporting); writing—review & editing (supporting). Nack Bong Choi and Sang Yoon Park: funding acquisition (lead); resources (lead); writing—review & editing (supporting).Hyun Jae Kim: funding acquisition (supporting); resources (supporting); supervision (lead). Acknowledgement This work was supported by LG Display Co., Ltd. References L. J. Kim et al., “Image quality enhancement in variable refresh rate LTPO-based AMOLED displays using a gate in panel voltage compensation scheme,” J. Inf. Disp., vol. 26, no. 2, pp. 187–196, Nov. 2024, doi: 10.1080/15980316.2024.2424187 . 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Han, “The hysteresis phenomenon in a Si:H TFT and poly Si TFT in AMOLED,” ECS Trans., vol. 8, no. 1, pp. 77–82, 2007, doi: 10.1149/1.2767290 . D. W. Kim, K. C. Moon, H. Im, and Y. S. Kim, “Hysteresis improvement of LTPS TFTs by N₂O plasma surface treatment,” J. Electr. Eng. Technol., vol. 20, no. 4, pp. 2537–2542, Mar. 2025, doi: 10.1007/s42835-025-02170-0 . Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 08 Nov, 2025 Reviews received at journal 08 Nov, 2025 Reviews received at journal 29 Oct, 2025 Reviewers agreed at journal 27 Oct, 2025 Reviewers agreed at journal 27 Oct, 2025 Reviewers invited by journal 27 Oct, 2025 Editor assigned by journal 23 Oct, 2025 Submission checks completed at journal 23 Oct, 2025 First submitted to journal 21 Oct, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7919372","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":537180608,"identity":"7e247ad9-d145-4a6e-9f77-90949519b521","order_by":0,"name":"Dong Sup Sim","email":"","orcid":"","institution":"Yonsei University","correspondingAuthor":false,"prefix":"","firstName":"Dong","middleName":"Sup","lastName":"Sim","suffix":""},{"id":537180609,"identity":"1818dc29-fceb-4694-ade6-d0880cc6418e","order_by":1,"name":"Sun Min Song","email":"","orcid":"","institution":"Yonsei University","correspondingAuthor":false,"prefix":"","firstName":"Sun","middleName":"Min","lastName":"Song","suffix":""},{"id":537180610,"identity":"fd6a6d9a-d951-41cd-b314-db1178281304","order_by":2,"name":"Jun Hwan Noh","email":"","orcid":"","institution":"LG Display, Co., Ltd.","correspondingAuthor":false,"prefix":"","firstName":"Jun","middleName":"Hwan","lastName":"Noh","suffix":""},{"id":537180611,"identity":"aec6e1dc-da5a-4d9b-b865-02acd05ded76","order_by":3,"name":"I. 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03:21:53","extension":"html","order_by":18,"title":"","display":"","copyAsset":false,"role":"acdc-reference","size":55764,"visible":true,"origin":"","legend":"","description":"","filename":"earlyproof.html","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/ef68acaba9af4b2689049fd3.html"},{"id":95256294,"identity":"5826746e-5ff7-4323-8fbd-41511280c79a","added_by":"auto","created_at":"2025-11-06 03:21:52","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":3042575,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Driving schemes of LTPO AMOLED displays showing the difference in skip frame insertion between 1 Hz and 120 Hz operation and (b) delayed response during digit changes in 1 Hz AoD mode, which does not occur under 120 Hz operation.\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/79e4faf8621b8c8f725dcb54.png"},{"id":95256298,"identity":"06e77b1e-2e36-4334-ac4f-e62ffa08aa23","added_by":"auto","created_at":"2025-11-06 03:21:53","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":387868,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Schematic of the 8T1C compensation pixel circuit used in the LTPO AMOLED panel. (b) Gate signal timing for refresh and skip frames. The refresh frame includes initialization, programming, reset, and emission, while the skip frame includes only reset and emission.\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/373572dcd0572baec0234089.png"},{"id":95312810,"identity":"9838b44a-d2b6-4ac0-919e-cfb678046b79","added_by":"auto","created_at":"2025-11-06 15:50:22","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":142536,"visible":true,"origin":"","legend":"\u003cp\u003eFirst-second response (FSR) to black-to-white transitions at (a) 120 Hz and (b) 1 Hz.\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/eaabed8709c317b2152aa026.png"},{"id":95256296,"identity":"42d995ab-4d37-48ef-a8cd-9ed33ef753c9","added_by":"auto","created_at":"2025-11-06 03:21:52","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":285940,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Drain current transient of the D-TFT during gate voltage change, indicating V\u003csub\u003eTH\u003c/sub\u003e positive shift and gradual recovery. (b) Luminance and V\u003csub\u003eTH\u003c/sub\u003e responses during a black-to-white transition.\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/d50e6975174690767d6484c9.png"},{"id":95256304,"identity":"7e38cfb5-ec82-41ec-9494-ade87e941173","added_by":"auto","created_at":"2025-11-06 03:21:53","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":423808,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Gate-to-source capacitance of T3 in the compensation pixel circuit. (b) Reduced on-capacitance ratio due to V\u003csub\u003eGS\u003c/sub\u003e transition range shift. (c) Reduced luminance peak from weakened kickback effect. (d) Luminance decay from gradual V\u003csub\u003eTH\u003c/sub\u003e recovery during emission.\u003c/p\u003e","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/7e46a0adb44bb6ac426c46ee.png"},{"id":95256299,"identity":"7935e45b-199e-4ca7-a60b-985f319ca25c","added_by":"auto","created_at":"2025-11-06 03:21:53","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":280180,"visible":true,"origin":"","legend":"\u003cp\u003eImprovement of luminance response using two approaches; (a) increasing a reset voltage and (b) fast-driving using short-duration high-frequency frame insertion. (c) Schematic of the fast-driving method.\u003c/p\u003e","description":"","filename":"floatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/b6048be519bfe337796890b1.png"},{"id":95312745,"identity":"bcc1dea8-d0c2-45e3-a841-46ed0899bdcd","added_by":"auto","created_at":"2025-11-06 15:50:09","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":309778,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Correlation between the FSR and fast-driving conditions, including frequency and insertion duration. (b) Power consumption analysis under varying fast-driving conditions during a 1-minute AoD screen update interval. Luminance response at 1 Hz; (c) without fast-driving and (d) with 30 Hz for 0.6 s fast-driving during black-to-white transition.\u003c/p\u003e","description":"","filename":"floatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/a3b547febcf19eb5734d7d37.png"},{"id":95315639,"identity":"0d760731-139f-4cf6-8224-c1769971ac3a","added_by":"auto","created_at":"2025-11-06 15:56:21","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":5248562,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7919372/v1/672def6b-b81d-458b-93f7-0a6485764627.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Enhancing luminance response during gray-level transitions at low frequencies in AMOLED displays","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eThe growing adoption of smartwatches, foldable phones, and other portable electronic devices has significantly increased the demand for low-power display technologies [\u003cspan additionalcitationids=\"CR2 CR3\" citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. To reduce power consumption while maintaining high display quality, low-temperature poly-Si and oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) displays have emerged as a key solution. As illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(a), by combining poly-Si-based driving thin-film transistors (D-TFTs) with oxide-based switching TFTs (S-TFTs), LTPO enables dynamic refresh rate control, allowing seamless transitions between high and low frame rates, such as from 120 Hz to 1 Hz [\u003cspan additionalcitationids=\"CR6 CR7\" citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e].\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003eHowever, as illustrated in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e(b), temporal response degradation under low-frequency operation, particularly at 1 Hz in always-on display (AoD) mode, has become a critical issue, leading to visible gray-level transition delays and perceived deterioration in display quality [\u003cspan additionalcitationids=\"CR10\" citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]. This degradation primarily originates from the hysteresis behavior of the poly-Si-based D-TFT, which induces threshold voltage (V\u003csub\u003eTH\u003c/sub\u003e) shift and delayed recovery [\u003cspan additionalcitationids=\"CR13 CR14\" citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e]. These effects not only delay the restoration of the transistor's operating point but also weaken the parasitic coupling effect during the programming phase due to changes in the gate-to-source voltage range of the oxide-based S-TFT. Consequently, the final gate voltage after black-to-white transitions (i.e., gray-level transition) becomes higher than that of a steady white state, further degrading the temporal luminance response.\u003c/p\u003e\u003cp\u003eVarious compensation techniques have been proposed to address these issues [\u003cspan additionalcitationids=\"CR17 CR18\" citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]\u0026ndash;[\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e]. However, most are optimized for high-refresh-rate operation and lack effectiveness in low-frequency scenarios. In particular, conventional driving schemes are unable to effectively accelerate V\u003csub\u003eTH\u003c/sub\u003e recovery within the limited time frame of 1 Hz frame updates.\u003c/p\u003e\u003cp\u003eTo overcome these limitations, this study proposes a short-duration high-frequency frame insertion technique during gray-level transitions. By momentarily increasing the frame rate during the transition period, the method facilitates rapid V\u003csub\u003eTH\u003c/sub\u003e recovery in the D-TFT. The proposed approach is validated using actual LTPO AMOLED display panels, and its effectiveness in improving temporal response under 1 Hz operation is experimentally verified.\u003c/p\u003e"},{"header":"2. Experiments","content":"\u003cp\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eA 6.7-inch LTPO AMOLED display with quad high definition (QHD) resolution was used in the experiments. Figure\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e(a) illustrates the 8T1C compensation pixel circuit employed in the test panel. In this structure, T2 and T3 transistors, which are connected to the gate node of the D-TFT, are implemented using oxide TFTs with low leakage characteristics, suitable for low-frequency operation. The remaining transistors are composed of p-type low-temperature poly-Si (LTPS) TFTs. V\u003csub\u003eDD\u003c/sub\u003e and V\u003csub\u003eSS\u003c/sub\u003e denote the supply voltages, and V\u003csub\u003eINT\u003c/sub\u003e, V\u003csub\u003eRST\u003c/sub\u003e, and V\u003csub\u003eDATA\u003c/sub\u003e represent the initialization voltage, reset voltage, and data voltage, respectively. C\u003csub\u003eSTG\u003c/sub\u003e indicates storage capacitance.\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e(b) shows the gate signal control scheme of the pixel circuit. Each refresh frame is divided into four sequential phases: initialization, programming, reset, and emission. In contrast, each skip frame consists only of the reset and emission phases. During the initialization phase, all internal nodes (Node 1\u0026ndash;Node 4) are reset to eliminate the influence of the data voltage stored in the previous frame. In the programming phase, a diode-connection configuration is used to compensate for the V\u003csub\u003eTH\u003c/sub\u003e of the D-TFT, and the data voltage for the next frame is charged to the D-TFT gate node. In the reset phase, a high voltage is applied to the source node of the D-TFT to mitigate V\u003csub\u003eTH\u003c/sub\u003e variation caused by hysteresis effects that may occur between refresh and skip frames.\u003c/p\u003e\u003cp\u003eWhen all 120 frames within 1-second period are configured as refresh frames without any skip frames, the display operates at 120 Hz. Conversely, when only one refresh frame is used along with 119 skip frames, the panel operates at 1 Hz. As the number of skip frames increases, power consumption decreases, but visual quality tends to degrade.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e presents the measured luminance responses during gray-level transitions from black to white. Optical measurements were conducted at the center of the panel using a KONICA MINOLTA CA-427, with a sampling rate of 3 kHz. To eliminate unwanted high-frequency fluctuations, the normalized luminance was smoothed using a moving average filter equivalent to one frame at 120 Hz.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eAs shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e(a), the panel exhibited a fast luminance response under 120 Hz operation. In contrast, Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e(b) demonstrates a significantly slower response under 1 Hz operation, with luminance taking several seconds to reach the steady state. To quantify this difference, we define the first-second response (FSR) as follows:\u003c/p\u003e\u003cp\u003e\u003cem\u003eFSR =\u003c/em\u003e \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{{\\sum\\:}_{t=1}^{2}Measured\\:data}{{\\sum\\:}_{t=8}^{9}Reference\\:data}*100\\:\\left[\\%\\right]\\)\u003c/span\u003e\u003c/span\u003e\u003cdiv class=\"BlockQuote\"\u003e\u003cp\u003eHere, the measured data corresponds to the luminance values acquired during the first second after the gray-level transition from black to white, and the reference data corresponds to the steady-state luminance measured at 120 Hz under white display conditions.\u003c/p\u003e\u003c/div\u003e\u003c/p\u003e"},{"header":"3. Results and discussion","content":"\u003cp\u003eTo investigate the hysteresis behavior of the D-TFT, a transient response measurement was conducted by switching the gate voltage from the off-state to the on-state and monitoring the drain current. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e(a), the drain current initially surged in response to the gate voltage change, then gradually settled to a steady state. This behavior indicates that when the gray-level transitions from black to white, the V\u003csub\u003eTH\u003c/sub\u003e of the D-TFT experiences a positive shift, followed by a gradual recovery over time.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e(b) illustrates the luminance response and V\u003csub\u003eTH\u003c/sub\u003e variation of the D-TFT during the black-to-white transition. During the programming phase, the positive V\u003csub\u003eTH\u003c/sub\u003e shift increases the D-TFT gate voltage, leading to a reduced luminance peak. Subsequently, during the emission phase, as V\u003csub\u003eTH\u003c/sub\u003e recovers, the luminance gradually decreases, exhibiting a luminance decay behavior.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e illustrates the mechanism responsible for the reduced luminance peak during the programming phase and the luminance decay during the emission phase following a black-to-white transition. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(a) depicts the gate-to-source capacitance (C\u003csub\u003eGS\u003c/sub\u003e) of transistor T3 during the programming phase. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(b), C\u003csub\u003eGS\u003c/sub\u003e is not constant but varies with V\u003csub\u003eGS\u003c/sub\u003e. Due to a positive shift in V\u003csub\u003eTH\u003c/sub\u003e of the D-TFT, the drain current increases, raising the gate voltage of the D-TFT during programming. Consequently, when the scan signal (Scan 3) transitions from high to low after programming, the V\u003csub\u003eGS\u003c/sub\u003e transition range experiences a negative shift while maintaining a constant voltage range. This shift leads to a reduction in the on-state capacitance ratio. The resulting voltage shift at node 2 (ΔV\u003csub\u003eS\u003c/sub\u003e) of T3 can be described by the following equation:\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cem\u003e△V\u003c/em\u003e\u003csub\u003e\u003cem\u003eS\u003c/em\u003e\u003c/sub\u003e \u003cem\u003e=\u003c/em\u003e \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{{C}_{GS}}{({C}_{GS}\\:+\\:{C}_{STG})}*△{V}_{G}\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e\u003cp\u003eGiven that C\u003csub\u003eSTG\u003c/sub\u003e is significantly larger than C\u003csub\u003eGS\u003c/sub\u003e, this can be approximated as:\u003c/p\u003e\u003cp\u003e\u003cem\u003e△V\u003c/em\u003e\u003csub\u003e\u003cem\u003eS\u003c/em\u003e\u003c/sub\u003e \u003cem\u003e=\u003c/em\u003e \u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(\\:\\frac{{C}_{GS}}{{C}_{STG}}*△{V}_{G}\\)\u003c/span\u003e\u003c/span\u003e\u003c/p\u003e\u003cp\u003eAs the scan signal V\u003csub\u003eG\u003c/sub\u003e changes, this transition occurs at a lower C\u003csub\u003eGS\u003c/sub\u003e region, thereby weakening the kickback noise. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(c) shows that due to the reduced kickback, the gate voltage of the D-TFT is set higher than its steady-state value after programming, resulting in a reduced luminance peak.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(d) illustrates the mechanism behind the luminance decay observed during the emission phase. As the V\u003csub\u003eTH\u003c/sub\u003e of the D-TFT gradually recovers with a negative shift, the drain current decreases accordingly, leading to a reduction in luminance.\u003c/p\u003e\u003cp\u003eTo mitigate the hysteresis-induced effects of the D-TFT, two evaluation experiments were conducted. In the first experiment, the V\u003csub\u003eRST\u003c/sub\u003e applied through T4 and the Scan 4 signal was increased to investigate its impact on luminance response. Increasing V\u003csub\u003eRST\u003c/sub\u003e induces a stronger on-bias across the D-TFT before and after programming, which helps to suppress the influence of the previous frame\u0026rsquo;s black V\u003csub\u003eDATA\u003c/sub\u003e. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a), increasing a reset voltage from 5 V to 6 V improves the reduced luminance peak. However, the luminance decay remains significant during the emission phase.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eIn the second experiment, short-duration high-frequency frame insertion was applied at 10 Hz for a duration of 1 second during the black-to-white transition to increase the number of reset operations. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b), although the reduced luminance peak remained in the first frame, the luminance rapidly recovers from the second frame onward, resulting in a significant improvement in the FSR from 59.3% to 95.0%. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(c) illustrates this fast driving method, which uses short-duration high-frequency frame insertion.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e(a) illustrates the correlation between the FSR and the fast-driving conditions, specifically the frequency and insertion duration of high-frequency frames. Measurements were conducted on 30 display panels. The results show that higher driving frequencies and longer insertion durations lead to improved FSR performance.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e(b) presents the relationship between power consumption and fast-driving conditions over a 1-minute interval, which corresponds to the time update cycle in AoD mode. As with the FSR test, 30 display panels were evaluated. Among the conditions with no visibly noticeable delay, the configuration with a 30 Hz frequency and a 0.6-second insertion time was identified as optimal.\u003c/p\u003e\u003cp\u003eFigure \u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e(c) shows the 1 Hz luminance response during a black-to-white transition, while Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e(d) presents the luminance response under the fast-driving condition of 30 Hz for 0.6 s. In this case, power consumption increased by only 0.6%, while the FSR significantly improved from 68.1% to 98.2%.\u003c/p\u003e"},{"header":"4. Conclusion","content":"\u003cp\u003eThis study proposed a short-duration high-frequency frame insertion method to mitigate the temporal luminance degradation observed during gray-level transitions in low-frequency LTPO AMOLED display operation. Through experimental analysis, it was confirmed that the delayed luminance response at 1 Hz operation primarily originates from the hysteresis-induced V\u003csub\u003eTH\u003c/sub\u003e shift of the p-channel LTPS D-TFT. This shift weakens the parasitic coupling effect during the programming phase, resulting in an increased gate voltage and reduced initial luminance. Furthermore, as V\u003csub\u003eTH\u003c/sub\u003e gradually recovers during the emission phase, less current flows through the D-TFT and luminance gradually decreases.\u003c/p\u003e\u003cp\u003eTo address this issue, we introduced a fast-driving scheme by inserting high-frequency frames during the gray-level transition phase. The proposed method facilitates rapid V\u003csub\u003eTH\u003c/sub\u003e recovery and improves the luminance response without significantly increasing power consumption. Among various driving conditions tested across 30 display panels, the 30 Hz for 0.6 s configuration was identified as optimal, achieving a substantial improvement in the FSR from 68.1% to 98.2% with only a 0.6% increase in power consumption. This approach is especially effective in AoD applications, where low-refresh-rate operation is essential, and can be widely adopted to enhance image quality in advanced low-power display systems.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAuthor Contribution\u003c/h2\u003e\u003cp\u003eDong Sup Sim: conceptualization (lead); data curation (lead); formal analysis (lead); investigation (lead); methodology (lead); resources (equal); software (lead); validation (lead); visualization (lead); writing\u0026mdash;original draft (lead); writing\u0026mdash;review \u0026amp; editing (lead). Sun Min Song, Jun Hwan Noh, and I. Sak Lee: formal analysis (supporting); investigation (supporting); visualization (supporting); writing\u0026mdash;review \u0026amp; editing (supporting). Nack Bong Choi and Sang Yoon Park: funding acquisition (lead); resources (lead); writing\u0026mdash;review \u0026amp; editing (supporting).Hyun Jae Kim: funding acquisition (supporting); resources (supporting); supervision (lead).\u003c/p\u003e\u003ch2\u003eAcknowledgement\u003c/h2\u003e\u003cp\u003eThis work was supported by LG Display Co., Ltd.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eL. J. Kim et al., \u0026ldquo;Image quality enhancement in variable refresh rate LTPO-based AMOLED displays using a gate in panel voltage compensation scheme,\u0026rdquo; J. Inf. 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Kim, \u0026ldquo;Hysteresis improvement of LTPS TFTs by N₂O plasma surface treatment,\u0026rdquo; J. Electr. Eng. Technol., vol. 20, no. 4, pp. 2537\u0026ndash;2542, Mar. 2025, doi: \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1007/s42835-025-02170-0\u003c/span\u003e\u003cspan address=\"10.1007/s42835-025-02170-0\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e.\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"journal-of-information-display","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of Information Display](https://link.springer.com/journal/44469)","snPcode":"44469","submissionUrl":"https://submission.springernature.com/new-submission/44469/3?","title":"Journal of Information Display","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Open","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"Organic light-emitting diode (OLED), Low- temperature poly-Si and oxide (LTPO), Luminance response, Hysteresis, Parasitic coupling effect","lastPublishedDoi":"10.21203/rs.3.rs-7919372/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7919372/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"This study proposes a novel driving method to address temporal response degradation observed during gray-level transitions under low-frequency operation in low-temperature poly-Si and oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) displays. Through experimental investigation, we demonstrate that the delayed response is primarily attributed to the hysteresis behavior of the driving thin-film transistor (D-TFT), leading to a threshold voltage (VTH) shift and delayed recovery during black-to-white transitions (i.e., gray-level transition). Moreover, the VTH shift can distort the parasitic coupling effect during the programming phase, leading to further degradation in temporal response. To mitigate this issue, we evaluate two approaches, increasing a reset voltage and introducing short-duration high-frequency frame insertion during gray-level transitions to facilitate rapid VTH recovery. Through this, we demonstrate that while both methods improve the luminance response, the frame insertion technique achieves superior performance particularly in luminance stability. This frame insertion method improved the first-second luminance response from 68.1% to 98.2%, while achieving this enhancement with only a 0.6% increase in power consumption through power-efficient optimization. This approach significantly enhances display performance under low-refresh-rate operation, such as in always-on display (AoD) modes.","manuscriptTitle":"Enhancing luminance response during gray-level transitions at low frequencies in AMOLED displays","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-11-06 03:21:48","doi":"10.21203/rs.3.rs-7919372/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Revision requested","date":"2025-11-09T02:18:52+00:00","index":"","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-11-08T10:38:11+00:00","index":"hide","fulltext":""},{"type":"editorInvitedReview","content":"","date":"2025-10-30T01:43:19+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"94511039118696903668807903426448196204","date":"2025-10-27T23:45:02+00:00","index":"hide","fulltext":""},{"type":"reviewerAgreed","content":"154728309823083453261578574313764662294","date":"2025-10-27T10:18:22+00:00","index":"hide","fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-10-27T10:04:20+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-10-23T13:07:14+00:00","index":"","fulltext":""},{"type":"checksComplete","content":"","date":"2025-10-23T13:06:57+00:00","index":"","fulltext":""},{"type":"submitted","content":"Journal of Information Display","date":"2025-10-22T00:49:56+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"journal-of-information-display","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [Journal of Information Display](https://link.springer.com/journal/44469)","snPcode":"44469","submissionUrl":"https://submission.springernature.com/new-submission/44469/3?","title":"Journal of Information Display","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Open","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"cc2599b8-d109-4024-a667-beac26d7854f","owner":[],"postedDate":"November 6th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"under-review","subjectAreas":[],"tags":[],"updatedAt":"2025-11-26T13:23:51+00:00","versionOfRecord":[],"versionCreatedAt":"2025-11-06 03:21:48","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-7919372","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-7919372","identity":"rs-7919372","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}