Dynamic Pass Bias Control for Temperature-Resilient Neural Networks Using Vertical NAND Flash Memory

Dynamic Pass Bias Control for Temperature-Resilient Neural Networks Using Vertical NAND Flash Memory | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Dynamic Pass Bias Control for Temperature-Resilient Neural Networks Using Vertical NAND Flash Memory Sung-Ho Park, Jiseong Im, Jonghyun Ko, Joon Hwang, Yeongheon Yang, and 7 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-6798696/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 30 Sep, 2025 Read the published version in Nano Convergence → Version 1 posted 5 You are reading this latest preprint version Abstract Vertical NAND (V-NAND) flash memory has emerged as a promising candidate for neuromorphic computing platforms due to its high density, scalability, and reliability. However, synaptic weights stored in V-NAND cells are highly sensitive to ambient temperature variations, resulting in significant conductance shifts that degrade the inference accuracy of neural networks. To address this challenge, we propose a dynamic pass bias (DPB) control scheme that compensates for temperature-induced weight variations without requiring memory reprogramming or additional hardware overhead. By adaptively adjusting the pass bias applied to unselected word-lines during read operations, the DPB scheme effectively stabilizes the differential conductance representation of weights under thermal fluctuations. In addition, we introduce a temperature-adaptive biasing circuit composed of a single-crystalline silicon MOSFET and V-NAND strings. Exploiting their opposing temperature-dependent resistance characteristics, this passive circuit naturally reduces the pass bias as temperature rises, enabling real-time analog compensation without explicit sensing or digital control logic. Experimental measurements on commercial V-NAND devices fabricated with over 100 WL layers reveal substantial shifts in bit-line currents with increasing temperature. Simulation results based on CIFAR-10 image classification using a VGG-11 network demonstrate that the DPB scheme significantly mitigates accuracy degradation across a wide temperature range. Notably, adjusting pass bias at lower temperatures improves classification accuracy by up to 10.5%p compared to conventional fixed-bias operations. These results highlight the effectiveness of dynamic pass bias control—both digitally and circuit-assisted—as a lightweight and scalable solution for enhancing the temperature resilience of V-NAND flash memory-based neural networks. Neural Network Neuromorphic Computing V-NAND Flash Memory Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 1. Introduction The proliferation of artificial intelligence and machine learning technologies has significantly increased the demand for efficient and scalable hardware platforms capable of supporting large-scale neural network computations [1,2]. However, traditional von Neumann architectures are limited by the fundamental bottleneck of separate memory and processing units, leading to substantial energy and time penalties during data movement [3–5]. Neuromorphic computing has emerged as a promising paradigm to address this challenge by co-locating memory and computation within the same physical array [3–5]. Among various memory candidates for neuromorphic systems—including ReRAM [6], PCM [7], and FeFETs [8]—vertical NAND (V-NAND) flash memory stands out due to its high integration density, mature fabrication infrastructure, excellent retention reliability, and cost-effectiveness [9–11]. These characteristics make V-NAND flash memory an attractive candidate for realizing large-scale and energy-efficient neuromorphic hardware. Despite these advantages, practical implementations of V-NAND flash memory-based neuromorphic systems encounter critical challenges, particularly regarding operational stability under ambient temperature variations. As temperature increases, the carrier mobility in the polycrystalline silicon (poly-Si) channel of V-NAND strings also increases, resulting in higher bit-line (BL) currents even at fixed bias conditions [12]. This temperature-induced change alters the effective conductance values of memory cells, which can distort the weight representation in neural networks and severely degrade inference accuracy. Traditional methods to mitigate such thermal instability involve either complex circuit-based compensation mechanisms or periodic retraining of neural network weights [13]. However, these approaches often introduce significant hardware overhead, increased system complexity, or additional energy consumption—factors that counteract the primary advantages of neuromorphic computing. In this work, we propose a dynamic pass bias (DPB) control scheme as a lightweight and effective strategy for compensating temperature-induced variations in V-NAND flash memory-based neural networks. The key idea is to dynamically adjust the pass bias ( V Pass ) applied to unselected word-lines (WLs) during read operations based on the detected ambient temperature. By fine-tuning V Pass , we can counterbalance the thermal effects on BL current without the need for reprogramming the memory or adding heavy compensation circuitry. To further support practical implementation, we also introduce a temperature-adaptive biasing circuit that autonomously adjusts V Pass in real time without explicit temperature sensing or digital control. This circuit leverages the opposing temperature dependence of a single-crystalline silicon MOSFET and V-NAND strings connected in series. As a result, the voltage drop across the V-NAND string naturally decreases as temperature rises, offering an elegant analog solution for thermal compensation. Extensive electrical measurements using commercial V-NAND flash memory devices fabricated by SK hynix, featuring over 100 stacked WL layers, reveal the impact of temperature on BL current and weight stability. Furthermore, PyTorch-based CIFAR-10 image classification simulations employing a VGG-11 architecture demonstrate that the DPB scheme significantly improves inference accuracy across a wide range of operating temperatures, highlighting its potential for enabling thermally robust and scalable neuromorphic systems. 2. Results and Discussion 2.1 Neural networks using V-NAND flash memory Figure 1 illustrates the architecture of a neural network implemented using V-NAND flash memory [14–16]. In this structure, each V-NAND string is defined by a specific combination of the drain-select-line (DSL) and the bit-line (BL), while multiple word-lines (WLs) are vertically stacked within a string, sharing a common channel [17–22]. The combination of a DSL, BL, and WL determines the basic unit of data storage, referred to as a V-NAND flash cell. The neural network based on V-NAND flash memory operates by storing weight values as conductance levels within the memory cells. To facilitate the representation of negative weights, each synaptic weight is encoded as the conductance difference between two adjacent BLs ( W = G + − G − ). Inputs to the neural network are applied to the DSLs through a pulse width modulation (PWM) circuit, which modulates the pulse width according to the input magnitude. The currents from V-NAND strings connected to the same BL are summed at the BL, enabling efficient vector-matrix multiplication (VMM) operations. The resulting BL current is subsequently processed through an analog-to-digital converter (ADC). Each WL is utilized as a distinct weight layer, and successive VMM operations are performed by sequentially reading different WLs corresponding to subsequent weight layers. 2.2 Temperature dependence of synaptic weights Figure 2 depicts the temperature-dependent variations in the weights stored within V-NAND flash memory. In this work, commercial V-NAND flash memory fabricated by SK hynix, featuring over 100 WL layers, was employed for all electrical measurements. Figure 2(a) presents the measured BL current ( I BL ) versus WL voltage ( V WL ) characteristics at various ambient temperatures. As the temperature increases, carrier mobility within the poly-Si channel improves, leading to a noticeable increase in I BL . Figure 2(b) shows the ratio of the temperature-induced change in I BL relative to the reference current at 25⁰C ( I BL,25⁰C ). The increase in I BL is more pronounced at lower V WL values, where the device operates in the subthreshold region. These temperature-induced changes in I BL result in unintended perturbations in the effective weights, ultimately degrading the inference accuracy of the neural network. Figure 2(c) displays the relationship between the synaptic weight at 25⁰C and its corresponding values at elevated temperatures. As previously mentioned, in V-NAND flash memory-based neural networks, each weight is computed as the conductance difference between two adjacent BLs. The results reveal that larger absolute weight values exhibit greater deviation under elevated temperatures. The inset of Figure 2(c) presents the temperature-dependent trend lines, where a steeper slope (>1) at higher temperatures reflects a larger weight error. Figure 2(d) quantifies the relative change in weight as a function of the baseline weight at 25⁰C. The results indicate that smaller weights tend to experience higher relative variations. Moreover, the deviations observed at 85⁰C are significantly greater than those at 55⁰C, confirming that higher ambient temperatures exacerbate weight errors in V-NAND flash memory-based neural networks. To compensate for temperature-induced variations in synaptic weights, the read conditions of the V-NAND flash memory can be adaptively adjusted based on ambient temperature. Figure 3(a) illustrates the biasing scheme applied during the read operation. A positive voltage ( V BL ) is applied to the BL, while the source-line (SL) is grounded to establish a current path through the selected V-NAND string. The WL corresponding to the selected V-NAND flash cell receives a designated read bias ( V Read ), whereas all unselected WLs are biased with a higher pass voltage ( V Pass ). The use of a pass bias ensures that the unselected cells remain in a conductive state, effectively transmitting the channel potential and minimizing the interference with the selected cell’s readout. Given this configuration, it is feasible to explore the temperature-dependent tuning of V BL , V Read , and V Pass to counteract the thermally induced weight distortions. By appropriately adjusting these read voltages in accordance with ambient temperature, the deviations in current—and hence the effective conductance—can be suppressed, leading to more stable weight representation during inference. Figures 3(b)–(d) present the I BL and the corresponding I BL differences (Δ I BL ) as a function of V WL (= V Read ), V BL , and V Pass , respectively. The read I BL s are shown for three cells with distinct conductance levels, and the current difference between any two I BL values is denoted as Δ I BL . In V-NAND flash memory-based neural network, this Δ I BL serves as an effective representation of synaptic weight, as it reflects the differential conductance that determines the weighted contribution during VMM. From the Δ I BL trends under varying bias conditions, it is observed that increasing V WL initially enhances Δ I BL but eventually leads to a reduction, exhibiting a non-monotonic behavior. In contrast, both V BL and V Pass show a consistent trend where Δ I BL increases monotonically with higher bias levels. Based on this observation, it is feasible to mitigate the temperature-induced increase in effective weight magnitude by applying lower V BL or V Pass values during read operations at elevated temperatures. Figure 4 shows the variation of the normalized weight ( N w ) as a function of V BL , along with the corresponding trend lines. The weights were normalized such that their values were distributed within the range of −1 to 1. Figure 4(a) compares the N w at 55⁰C to that at 25⁰C, while Figure 4(b) compares the N w at 85⁰C to that at 25⁰C. For the high-temperature measurements, V BL was initially set to the typical read bias of 0.4 V, and N w at 25⁰C was measured by incrementally adjusting V BL in 0.1 V steps. When the same V BL as used at high temperatures was applied at 25⁰C (red), a decrease in the absolute magnitude of N w was observed, resulting in a trend line slope less than unity. Conversely, when V BL was increased by 0.1 V to 0.5 V at 25⁰C (green), the absolute value of N w increased, yielding a trend line slope greater than unity. However, the results indicate that adjusting V BL values in discrete 0.1 V increments is insufficient for precisely compensating for the temperature-induced weight variations. Figure 5 presents the variation of N w as a function of V Pass , following a methodology similar to that of Figure 4 but focusing on V Pass instead of V BL . In the high-temperature conditions, V Pass was fixed at 5 V, and at 25⁰C, V Pass was incrementally adjusted in 0.1 V steps. Unlike the case of V BL adjustment, tuning V Pass enabled significantly finer compensation for temperature-induced weight variations, allowing the trend line slope to be closely aligned with the ideal value of unity. These results suggest that dynamic adjustment of V Pass is far more effective and precise than modifying V BL for compensating weight shifts caused by temperature variations. Therefore, V Pass modulation is recommended as a more reliable approach for achieving thermally robust neural network operation using V-NAND flash memory. 2.3 Dynamic pass bias scheme Figure 6 demonstrates the effectiveness of the proposed dynamic pass bias (DPB) scheme. To evaluate the impact of DPB, CIFAR-10 image classification simulations were conducted using the PyTorch framework with a VGG-11 architecture and the stochastic gradient descent (SGD) optimizer. The ADC at the output of the neural network was configured with 4-bit resolution. Figure 6(a) presents the threshold voltage ( V th ) tuning error—defined as the deviation from the target V th —introduced by the incremental step pulse programming (ISPP) method, the conventional programming approach for V-NAND flash memory [23]. Since the weights are programmed into the V-NAND flash memory during weight transfer, the V th error distribution was incorporated into the simulations to reflect realistic device characteristics. Figure 6(b) shows the CIFAR-10 image classification accuracy averaged over ten independent simulation runs as a function of the training epoch. A baseline accuracy of 80.14% was achieved after 200 epochs without temperature effects. Figure 6(c) illustrates the impact of varying V Pass levels at different temperatures on the classification accuracy. For consistency, the V Pass at 85⁰C—the highest temperature measured—was fixed at 5 V, ensuring that the V Pass at lower temperatures remained above 5 V to maintain sufficiently low resistance in the pass cells during read operations. Figure 6(c-1) shows the variation in accuracy at 85⁰C when the V Pass value used at 25⁰C is altered. When V Pass at 25⁰C was increased to 5.9 V, compared to the case where both temperatures used a V Pass of 5.0 V, an improvement of approximately 10.52 percentage points (%p) in classification accuracy was achieved. Figure 6(c-2) examines the accuracy at 55⁰C when the V Pass at 25⁰C is fixed at 5.9 V. Adjusting V Pass at 55⁰C to 5.2 V further enhanced the accuracy by approximately 2.68%p compared to the case with V Pass of 5.9 V at both 25⁰C and 55⁰C. Finally, Figure 6(d) compares the CIFAR-10 classification accuracy as a function of temperature, with and without applying the DPB scheme. Although the DPB-compensated accuracy does not fully recover to the 25⁰C baseline of 80.14%, a substantial improvement in accuracy across different temperatures is clearly observed with the use of DPB. 2.4 Temperature-adaptive circuit for DPB To enable automatic compensation of the V Pass in response to ambient temperature fluctuations, we propose a temperature-adaptive circuit structure as illustrated in Figure 7(a). The proposed circuit consists of a single-crystalline silicon (Si) channel MOSFET in series with a V-NAND flash memory block, followed by an operational amplifier (op-amp) stage that amplifies the voltage across the V-NAND strings. In this configuration, the temperature-dependent resistance behavior of each component plays a crucial role. Specifically, the resistance of the single-crystalline Si channel MOSFET increases with temperature due to enhanced phonon scattering [24], which reduces carrier mobility. In contrast, the resistance of the V-NAND string decreases with temperature, primarily because the poly-Si channel in the string exhibits increased carrier mobility at elevated temperatures. As these two opposing temperature responses are connected in series, the voltage division between them dynamically shifts. With increasing temperature, the growing resistance of the MOSFET causes a larger voltage drop across it, thereby reducing the effective voltage applied to V-NAND strings. However, the use of the MOSFET and V-NAND string alone is insufficient to produce the exact V Pass variation required to match the compensation range observed in neural network inference. Therefore, an op-amp is introduced to amplify the temperature-dependent voltage and generate a tunable output bias. By adjusting the reference voltage ( V Ref ) and the resistor values ( R 1 , R 2 ) in the op-amp feedback network, the output voltage ( V Pass ) can be configured to fall within the desired range over temperature. The V-NAND string block incorporates 200 parallel-connected V-NAND strings, reflecting realistic V-NAND flash memory architecture and reducing variability among individual strings. The proposed temperature-adaptive circuit can be integrated into the peripheral circuitry of the V-NAND flash memory. To verify the feasibility of the proposed temperature-adaptive circuit for DPB, SPICE simulations were conducted using a validated V-NAND flash memory model from prior research [25]. Simulation parameters included V DD = 10 V, V G = 13 V, V Ref = 6 V, and R 1 = R 2 . The MOSFET was modeled with a channel length of 10 μm and width of 500 nm, and the WLs of each V-NAND string were biased with a pass bias of 5 V. The simulated output voltage ( V out )—the generated pass bias—exhibited a controlled decrease with temperature, as shown in Figure 7(b), aligning well with the optimal V Pass profile required for accuracy recovery in CIFAR-10 inference (Figure 6(d)). When this temperature-adaptive circuit was integrated into the DPB framework, CIFAR-10 classification simulations exhibited a substantial improvement in accuracy, confirming the practical effectiveness of the circuit-assisted compensation scheme. This self-regulating mechanism suggests a novel approach to implementing DPB control. Rather than relying on explicit temperature sensing and digital feedback control, the circuit can inherently adjust V Pass in real time according to the ambient thermal condition. This approach offers a compact and energy-efficient solution for enhancing the thermal robustness of V-NAND flash memory-based neural networks. 3. Conclusion In this work, we investigated the impact of temperature variations on synaptic weights stored in vertical NAND (V-NAND) flash memory for neuromorphic computing applications. Electrical measurements revealed that the bit-line current and resulting synaptic conductance exhibit significant sensitivity to ambient temperature changes, leading to substantial degradation in neural network inference accuracy. Traditional compensation techniques for thermal instability often require substantial hardware modifications or reprogramming overhead, which are undesirable for lightweight neuromorphic systems. To address this challenge, we proposed a dynamic pass bias (DPB) control scheme that dynamically adjusts the pass bias ( V Pass ) during read operations based on the operating temperature. Through systematic measurements and simulations, we demonstrated that V Pass modulation effectively counteracts temperature-induced conductance variations without modifying the stored cell states. The effectiveness of the DPB scheme was validated using CIFAR-10 image classification simulations with a VGG-11 architecture and 4-bit ADCs. The results showed that the application of DPB improved inference accuracy by up to 10.5%p compared to conventional fixed-bias operations, significantly enhancing the temperature resilience of the system. To further support practical implementation, we also introduced a temperature-adaptive biasing circuit composed of a single-crystalline silicon MOSFET and V-NAND strings connected in series. By leveraging the opposing temperature dependencies of their resistances, the circuit inherently adjusts V Pass without external sensing or control. This passive analog approach offers a promising direction for realizing real-time, energy-efficient DPB control without additional digital logic or feedback mechanisms. The proposed DPB control method offers a simple, scalable, and hardware-efficient solution for maintaining stable neural network performance across a wide range of temperatures. Future work will focus on further optimizing the V Pass adjustment algorithms, extending the approach to more complex deep learning architectures, and implementing real-time temperature-adaptive control mechanisms for fully integrated V-NAND-based neuromorphic processors. Declarations Acknowledgements This work was supported in part by the BK21 FOUR Program of the Education and Research Program for Future ICT Pioneers, Seoul National University, in 2025; and in part by SK hynix Inc., in 2025; and in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2025-10032968). Availability of data and material The data that support the findings of this study are available from the corresponding author upon reasonable request and with permission of SK hynix Inc. Competing interests The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Funding This work was supported by Seoul National University, SK hynix Inc. and National Research Foundation of Korea (NRF). Author’s contribution S.-H.P., J.I. and J.K. conceived the idea, designed the experiments, and wrote the original draft. S.-H.P., J.I. and J.K. also performed methodology development, investigation, formal analysis, and data curation. J.H. participated in experiments. Y.Y and J.-W.B. contributed to data curation. R.-H.K., I.-S.L., D.S., M.O. and G.J. participated in reviewing and editing the manuscript. J.-H.L participated in manuscript review and editing. All authors have given approval to the final version of the manuscript. References Y. LeCun, Y. Bengio, G. Hinton, “Deep learning.” Nature 521 , 436–444 (2015). https://doi.org/10.1038/nature14539. M. I. Jordan, T. M. Mitchell, “Machine learning: Trends, perspectives, and prospects.” Science 349 , 255–260 (2015). https://doi.org/10.1126/science.aaa8415. G. W. Burr, R. M. Shelby, A. Sebastian, S. Kim, S. Kim, S. Sidler, K. Virwani, M. Ishii et al., “Neuromorphic computing using non-volatile memory.” Adv. Phys. X 2 , 89–124 (2017). https://doi.org/10.1080/23746149.2016.1259585. D. Markovic, A. Mizrahi, D. Querlioz, J. Grollier, “Physics for neuromorphic computing.” Nat. Rev. Phys. 2 , 499–510 (2020). https://doi.org/10.1038/s42254-020-0208-2. C. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. Date, B. Kay, “Opportunities for neuromorphic computing algorithms and applications.” Nat. Comput. Sci. 2 , 10–19 (2022). https://doi.org/10.1038/s43588-021-00184-y. S. Park, A. Sheri, J. Kim, J. Noh, J. Jang, M. Jeon, B. Lee, B. R. Lee et al., “Neuromorphic speech systems using advanced ReRAM-based synapse.” in 2013 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2013, pp. 25.6.1–25.6.4. https://doi.org/10.1109/IEDM.2013.6724692. O. Bichler, M. Suri, D. Querlioz, D. Vuillaume, B. Desalvo, C. Gamrat, “Visual Pattern Extraction Using Energy-Efficient “2-PCM Synapse” Neuromorphic Architecture.” IEEE Trans. Electron Devices 59 , 2206–2214 (2012). https://doi.org/10.1109/TED.2012.2197951. H. Mulaosmanovic, J. Ocker, S. Muller, M. Noack, J. Muller, P. Polakowski, T. Mikolajick, S. Slesazeck, “Novel ferroelectric FET based synapse for neuromorphic systems.” in 2017 IEEE Symposium on VLSI Technology (VLSI), Kyoto, Japan, 2017, pp. T176–177. https://doi.org/10.23919/VLSIT.2017.7998165. W. Jung, H. Kim, D. B. Kim, T. H. Kim, N. Lee, D. Shin, M. Kim, Y. Rho et al., “A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.” in 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 236–237. https://doi.org/10.1109/ISSCC49657.2024.10454343. S. H. Park, D. Kwon, H. N. Yoo, J. W. Back, J. Hwang, Y. Yang, J. J. Kim, J. H. Lee, “Retention Improvement in Vertical NAND Flash Memory Using 1-bit Soft Erase Scheme and its Effects on Neural Networks.” in 2022 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 5.5.1–5.5.4. https://doi.org/10.1109/IEDM45625.2022.10019529. S. T. Lee, H. Kim, J. H. Bae, H. Yoo, N. Y. Choi, D. Kwon, S. Lim, B. G. Park et al., “High-Density and Highly-Reliable Binary Neural Networks Using NAND Flash Memory Cells as Synaptic Devices.” in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 38.4.1–38.4.4. https://doi.org/10.1109/IEDM19573.2019.8993478. S. S. Li, W. R. Thurber, “The dopant density and temperature dependence of electron mobility and resistivity in n-type silicon.” Solid State Electron. 20 , 609–616 (1977). https://doi.org/10.1016/0038-1101(77)90100-9. I. Giannopoulos, M. L. Gallo, V. P. Jonnalagadda, E. Eleftheriou, A. Sebastian, “Temperature Compensation Schemes for In-Memory Computing using Phase-Change Memory.” in 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Genova, Italy, 2020, pp. 286–290. https://doi.org/10.1109/AICAS48895.2020.9074003. S. H. Park, J. Ko, I. S. Lee, R. H. Koo, J. H. Kim, Y. Yang, D. Kwon, J. J. Kim et al., “On-Chip Learning in Vertical NAND Flash Memory Using Forward–Forward Algorithm.” IEEE Trans. Electron Devices 71 , 3640–3644 (2024). https://doi.org/10.1109/TED.2024.3392170. S. T. Lee, G. Yeom, H. Yoo, H. S. Kim, S. Lim, J. H. Bae, B. G. Park, J. H. Lee, “Novel Method Enabling Forward and Backward Propagations in NAND Flash Memory for On-Chip Learning.” IEEE Trans. Electron Devices 68 , 3365–3370 (2021). https://doi.org/10.1109/TED.2021.3081610. J. Ko, S. H. Park, J. Im, J. Kim, R. H. Koo, Y. Yang, J. H. Lee, “Vertical NAND flash memory-based matrix-matrix multiplication scheme for energy-efficient attention score computation.” Neurocomputing 619 , 129210 (2025). https://doi.org/10.1016/j.neucom.2024.129210. S. H. Park, H. N. Yoo, Y. Yang, J. W. Back, R. H. Koo, D. Kwon, J. J. Kim, J. H. Lee, “Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash.” Appl. Phys. Lett. 123 , 142101 (2023). https://doi.org/10.1063/5.0161000. C. M. Compagnoni, A. Goda, A. S. Spinelli, P. Feeley, A. L. Lacaita, A. Visconti. “Reviewing the Evolution of the NAND Flash Technology.” Proc. IEEE 105 , 1609–1633 (2017). https://doi.org/10.1109/JPROC.2017.2665781. S. H. Park, H. N. Yoo, J. W. Back, J. Cho, Y. Yang, J. Im, R. H. Koo, J. Ko et al., “Retention Improvement in Vertical NAND Flash Memory Using Electron Back-Tunneling.” IEEE Electron Device Lett. 46 , 203–206 (2025). https://doi.org/10.1109/LED.2024.3506507. S. H. Park, H. N. Yoo, Y. Yang, J. J. Kim, J. H. Lee, “Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE).” IEEE Trans. Electron Devices 71 , 1834–1838 (2024). https://doi.org/10.1109/TED.2024.3350000. C. Caillat, K. Beaman, A. Bicksler, E. Camozzi, T. Ghilardi, G. Huang, H. Liu, Y. Liu et al., “3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture.” in 2017 IEEE International Memory Workshop (IMW), Monterey, CA, USA, 2017, pp. 1–4. https://doi.org/10.1109/IMW.2017.7939067. H. N. Yoo, J. W. Back, N. H. Kim, D. Kwon, B. G. Park, J. H. Lee. “First Demonstration of 1-bit Erase in Vertical NAND Flash Memory.” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, 2022, pp. 304–305. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830445. K. D. Suh, B. H. Suh, Y. H. Lim, J. K. Kim, Y. J. Choi, Y. N. Koh, S. S. Lee, S. C. Kwon et al., “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme.” IEEE J. Solid State Circuits 30 , 1149–1156 (1995). https://doi.org/10.1109/4.475701. G. W. Ludwig, R. L. Watters, “Drift and Conductivity Mobility in Silicon.” Phys. Rev. 101 , 1699 (1956). https://doi.org/10.1103/PhysRev.101.1699. J. Hwang, H. N. Yoo, K. H. Lee, J. W. Back, M. K. Park, Y. Yang, W. Y. Choi, J. H. Lee, “Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory.” IEEE Trans. Electron Devices 70 , 5469–5474 (2023). https://doi.org/10.1109/TED.2023.3308086. Cite Share Download PDF Status: Published Journal Publication published 30 Sep, 2025 Read the published version in Nano Convergence → Version 1 posted Editorial decision: Major revision 27 Jul, 2025 Reviewers agreed at journal 09 Jul, 2025 Reviewers invited by journal 09 Jul, 2025 Editor assigned by journal 02 Jun, 2025 First submitted to journal 01 Jun, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-6798696","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":483014208,"identity":"da1f7c36-c8ce-4fbb-9152-f8112d5116a6","order_by":0,"name":"Sung-Ho Park","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Sung-Ho","middleName":"","lastName":"Park","suffix":""},{"id":483014209,"identity":"7003b76e-8cb3-4315-8065-4c8c17f3a7c9","order_by":1,"name":"Jiseong Im","email":"","orcid":"","institution":"Seoul National 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Inc","correspondingAuthor":false,"prefix":"","firstName":"Yeongheon","middleName":"","lastName":"Yang","suffix":""},{"id":483014213,"identity":"39b4fd9a-e342-41fb-8fcc-004d96464b89","order_by":5,"name":"Jong-Won Back","email":"","orcid":"","institution":"SK Hynix Inc","correspondingAuthor":false,"prefix":"","firstName":"Jong-Won","middleName":"","lastName":"Back","suffix":""},{"id":483014214,"identity":"bd0a3521-493a-44b5-b189-4999d523ecf7","order_by":6,"name":"Ryun-Han Koo","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Ryun-Han","middleName":"","lastName":"Koo","suffix":""},{"id":483014215,"identity":"1ec61870-1a33-42df-b956-df209bc27bbd","order_by":7,"name":"In-Seok Lee","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"In-Seok","middleName":"","lastName":"Lee","suffix":""},{"id":483014216,"identity":"4cafd729-534b-479e-ad88-d65bf93b60ca","order_by":8,"name":"Dongbeen Shin","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Dongbeen","middleName":"","lastName":"Shin","suffix":""},{"id":483014217,"identity":"d0d9cb60-09f9-40cb-9dd8-759a587cad88","order_by":9,"name":"Mingyun Oh","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Mingyun","middleName":"","lastName":"Oh","suffix":""},{"id":483014218,"identity":"7804f975-1aaa-43fb-b99d-19e3a12b44c6","order_by":10,"name":"Gyuweon Jung","email":"","orcid":"","institution":"Seoul National University","correspondingAuthor":false,"prefix":"","firstName":"Gyuweon","middleName":"","lastName":"Jung","suffix":""},{"id":483014219,"identity":"89707422-0b5e-48c8-a2ac-a9488233190d","order_by":11,"name":"Jong-Ho Lee","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAoUlEQVRIiWNgGAWjYBACxhnMjQ+gbGZitTA2G5CmhUGCsU2CNC3MsxvbKn/uOMzA336A2biCKIfNOdh2m/fMYQaJMwnMiWeI0jIjse02Y9thBoYbDMwHG4jVUvgTqEWeJC0MvEAtBkAticRqaZbmbUvnMTyT2GxIlBbDGckHP/5ss5aTO374sCRxWqCqeIAWEqWBgUGeOGWjYBSMglEwogEASAEwqAMCOhoAAAAASUVORK5CYII=","orcid":"https://orcid.org/0000-0003-3559-9802","institution":"Seoul National University","correspondingAuthor":true,"prefix":"","firstName":"Jong-Ho","middleName":"","lastName":"Lee","suffix":""}],"badges":[],"createdAt":"2025-06-02 04:37:18","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-6798696/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-6798696/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1186/s40580-025-00513-1","type":"published","date":"2025-09-30T15:57:09+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":86675475,"identity":"02800113-ae2f-4f07-b68a-1c43cc265c9c","added_by":"auto","created_at":"2025-07-14 11:59:29","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":98720,"visible":true,"origin":"","legend":"\u003cp\u003eSchematic illustration of the neural network architecture implemented using V-NAND flash memory.\u003c/p\u003e","description":"","filename":"1.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/1af78076bd29e8099b7a1051.png"},{"id":86671055,"identity":"23502264-ab34-4360-b295-1441a76c1405","added_by":"auto","created_at":"2025-07-14 11:35:29","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":41016,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Measured \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e versus \u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e characteristics at different ambient temperatures. (b) Ratio of \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e increase relative to \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e at 25°C. (c) Temperature-dependent weight values compared to those at 25°C. A linear trend line is also shown. (d) Relative weight change as a function of initial weight.\u003c/p\u003e","description":"","filename":"2.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/12f175f371f9cc10473a32b2.png"},{"id":86672875,"identity":"db45f519-30b5-4bba-b928-fc773eb2ab5e","added_by":"auto","created_at":"2025-07-14 11:43:29","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":45198,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Read bias configuration for V-NAND flash memory operation. (b–d) \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e and BL current difference (Δ\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e) measured under varying (b) \u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e, (c) \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e, and (d) \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e conditions.\u003c/p\u003e","description":"","filename":"3.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/47e76f76b241ec0816fcb957.png"},{"id":86671059,"identity":"81761325-dd44-471b-8675-0f9426fc5d2d","added_by":"auto","created_at":"2025-07-14 11:35:29","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":58497,"visible":true,"origin":"","legend":"\u003cp\u003e(a-1, a-2) Normalized weights (\u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e) at 55°C compared to those at 25°C for different \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e values. (b-1, b-2) Normalized weights at 85°C compared to 25°C. The \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e at high temperature was fixed at 0.4 V, and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e at 25°C was varied in 0.1 V increments.\u003c/p\u003e","description":"","filename":"4.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/532785007bfe5204ecdd4d16.png"},{"id":86671062,"identity":"ea14b2f2-c9be-46cb-8a86-61c52d5495ae","added_by":"auto","created_at":"2025-07-14 11:35:29","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":56694,"visible":true,"origin":"","legend":"\u003cp\u003e(a-1, a-2) Normalized weights (\u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e) at 55°C compared to those at 25°C for different \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e values. (b-1, b-2) Normalized weights at 85°C compared to 25°C. The \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at high temperature was fixed at 5.0 V, and \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at 25°C was varied in 0.1 V increments.\u003c/p\u003e","description":"","filename":"5.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/b738466c65df5fdd9946d514.png"},{"id":86672879,"identity":"c697e094-03fd-4300-a216-70968deddc9c","added_by":"auto","created_at":"2025-07-14 11:43:29","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":52310,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Distribution of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e tuning error after ISPP with a step voltage of 0.5 V. (b) CIFAR-10 classification accuracy over epochs using a VGG-11 network, achieving a baseline of 80.14% with 4-bit ADCs. (c-1) Accuracy at 85°C versus \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e adjusted at 25°C. (c-2) Accuracy at 55°C with \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e optimization. (d) Comparison of classification accuracy across temperatures with and without DPB compensation.\u003c/p\u003e","description":"","filename":"6.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/b3ae9ab0e3405585f296e8d6.png"},{"id":86672878,"identity":"0bae37a1-9bc8-4cb2-909b-c3877bef5542","added_by":"auto","created_at":"2025-07-14 11:43:29","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":26012,"visible":true,"origin":"","legend":"\u003cp\u003e(a) Conceptual schematic of a temperature-adaptive circuit that automatically adjusts \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e using the opposing temperature dependence of a single-crystalline Si MOSFET and V-NAND strings. (b) Temperature-dependent output voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eout\u003c/sub\u003e, corresponding to \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e) obtained through SPICE simulation, along with the resulting CIFAR-10 classification accuracy when the temperature-adaptive circuit is applied.\u003c/p\u003e","description":"","filename":"7.png","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/7360acae30259e1df13fed4b.png"},{"id":92884648,"identity":"df43ae6b-4d01-446f-b9b8-fb9bfb47c4bb","added_by":"auto","created_at":"2025-10-06 16:13:47","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":777951,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-6798696/v1/c8a623cc-2216-41a8-844e-d1255227014a.pdf"}],"financialInterests":"","formattedTitle":"Dynamic Pass Bias Control for Temperature-Resilient Neural Networks Using Vertical NAND Flash Memory","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eThe proliferation of artificial intelligence and machine learning technologies has significantly increased the demand for efficient and scalable hardware platforms capable of supporting large-scale neural network computations [1,2]. However, traditional von Neumann architectures are limited by the fundamental bottleneck of separate memory and processing units, leading to substantial energy and time penalties during data movement [3\u0026ndash;5].\u003c/p\u003e\n\u003cp\u003eNeuromorphic computing has emerged as a promising paradigm to address this challenge by co-locating memory and computation within the same physical array [3\u0026ndash;5]. Among various memory candidates for neuromorphic systems\u0026mdash;including ReRAM [6], PCM [7], and FeFETs [8]\u0026mdash;vertical NAND (V-NAND) flash memory stands out due to its high integration density, mature fabrication infrastructure, excellent retention reliability, and cost-effectiveness [9\u0026ndash;11]. These characteristics make V-NAND flash memory an attractive candidate for realizing large-scale and energy-efficient neuromorphic hardware.\u003c/p\u003e\n\u003cp\u003eDespite these advantages, practical implementations of V-NAND flash memory-based neuromorphic systems encounter critical challenges, particularly regarding operational stability under ambient temperature variations. As temperature increases, the carrier mobility in the polycrystalline silicon (poly-Si) channel of V-NAND strings also increases, resulting in higher bit-line (BL) currents even at fixed bias conditions [12]. This temperature-induced change alters the effective conductance values of memory cells, which can distort the weight representation in neural networks and severely degrade inference accuracy.\u003c/p\u003e\n\u003cp\u003eTraditional methods to mitigate such thermal instability involve either complex circuit-based compensation mechanisms or periodic retraining of neural network weights [13]. However, these approaches often introduce significant hardware overhead, increased system complexity, or additional energy consumption\u0026mdash;factors that counteract the primary advantages of neuromorphic computing.\u003c/p\u003e\n\u003cp\u003eIn this work, we propose a dynamic pass bias (DPB) control scheme as a lightweight and effective strategy for compensating temperature-induced variations in V-NAND flash memory-based neural networks. The key idea is to dynamically adjust the pass bias (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e) applied to unselected word-lines (WLs) during read operations based on the detected ambient temperature. By fine-tuning \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e, we can counterbalance the thermal effects on BL current without the need for reprogramming the memory or adding heavy compensation circuitry.\u003c/p\u003e\n\u003cp\u003eTo further support practical implementation, we also introduce a temperature-adaptive biasing circuit that autonomously adjusts \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e in real time without explicit temperature sensing or digital control. This circuit leverages the opposing temperature dependence of a single-crystalline silicon MOSFET and V-NAND strings connected in series. As a result, the voltage drop across the V-NAND string naturally decreases as temperature rises, offering an elegant analog solution for thermal compensation.\u003c/p\u003e\n\u003cp\u003eExtensive electrical measurements using commercial V-NAND flash memory devices fabricated by SK hynix, featuring over 100 stacked WL layers, reveal the impact of temperature on BL current and weight stability. Furthermore, PyTorch-based CIFAR-10 image classification simulations employing a VGG-11 architecture demonstrate that the DPB scheme significantly improves inference accuracy across a wide range of operating temperatures, highlighting its potential for enabling thermally robust and scalable neuromorphic systems.\u003c/p\u003e"},{"header":"2. Results and Discussion","content":"\u003cp\u003e2.1 Neural networks using V-NAND flash memory\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eFigure 1 illustrates the architecture of a neural network implemented using V-NAND flash memory [14\u0026ndash;16]. In this structure, each V-NAND string is defined by a specific combination of the drain-select-line (DSL) and the bit-line (BL), while multiple word-lines (WLs) are vertically stacked within a string, sharing a common channel [17\u0026ndash;22]. The combination of a DSL, BL, and WL determines the basic unit of data storage, referred to as a V-NAND flash cell. The neural network based on V-NAND flash memory operates by storing weight values as conductance levels within the memory cells. To facilitate the representation of negative weights, each synaptic weight is encoded as the conductance difference between two adjacent BLs (\u003cem\u003eW\u003c/em\u003e=\u003cem\u003eG\u003c/em\u003e\u003csup\u003e+\u003c/sup\u003e\u0026minus;\u003cem\u003eG\u003c/em\u003e\u003csup\u003e\u0026minus;\u003c/sup\u003e). Inputs to the neural network are applied to the DSLs through a pulse width modulation (PWM) circuit, which modulates the pulse width according to the input magnitude. The currents from V-NAND strings connected to the same BL are summed at the BL, enabling efficient vector-matrix multiplication (VMM) operations. The resulting BL current is subsequently processed through an analog-to-digital converter (ADC). Each WL is utilized as a distinct weight layer, and successive VMM operations are performed by sequentially reading different WLs corresponding to subsequent weight layers.\u003c/p\u003e\n\u003cp\u003e2.2 Temperature dependence of synaptic weights\u003c/p\u003e\n\u003cp\u003eFigure 2 depicts the temperature-dependent variations in the weights stored within V-NAND flash memory. In this work, commercial V-NAND flash memory fabricated by SK hynix, featuring over 100 WL layers, was employed for all electrical measurements. Figure 2(a) presents the measured BL current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e) versus WL voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e) characteristics at various ambient temperatures. As the temperature increases, carrier mobility within the poly-Si channel improves, leading to a noticeable increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e. Figure 2(b) shows the ratio of the temperature-induced change in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e relative to the reference current at 25⁰C (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL,25⁰C\u003c/sub\u003e). The increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e is more pronounced at lower \u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e values, where the device operates in the subthreshold region. These temperature-induced changes in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e result in unintended perturbations in the effective weights, ultimately degrading the inference accuracy of the neural network. Figure 2(c) displays the relationship between the synaptic weight at 25⁰C and its corresponding values at elevated temperatures. As previously mentioned, in V-NAND flash memory-based neural networks, each weight is computed as the conductance difference between two adjacent BLs. The results reveal that larger absolute weight values exhibit greater deviation under elevated temperatures. The inset of Figure 2(c) presents the temperature-dependent trend lines, where a steeper slope (\u0026gt;1) at higher temperatures reflects a larger weight error. Figure 2(d) quantifies the relative change in weight as a function of the baseline weight at 25⁰C. The results indicate that smaller weights tend to experience higher relative variations. Moreover, the deviations observed at 85⁰C are significantly greater than those at 55⁰C, confirming that higher ambient temperatures exacerbate weight errors in V-NAND flash memory-based neural networks.\u003c/p\u003e\n\u003cp\u003eTo compensate for temperature-induced variations in synaptic weights, the read conditions of the V-NAND flash memory can be adaptively adjusted based on ambient temperature. Figure 3(a) illustrates the biasing scheme applied during the read operation. A positive voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e) is applied to the BL, while the source-line (SL) is grounded to establish a current path through the selected V-NAND string. The WL corresponding to the selected V-NAND flash cell receives a designated read bias (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eRead\u003c/sub\u003e), whereas all unselected WLs are biased with a higher pass voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e). The use of a pass bias ensures that the unselected cells remain in a conductive state, effectively transmitting the channel potential and minimizing the interference with the selected cell\u0026rsquo;s readout. Given this configuration, it is feasible to explore the temperature-dependent tuning of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eRead\u003c/sub\u003e, and \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e to counteract the thermally induced weight distortions. By appropriately adjusting these read voltages in accordance with ambient temperature, the deviations in current\u0026mdash;and hence the effective conductance\u0026mdash;can be suppressed, leading to more stable weight representation during inference.\u003c/p\u003e\n\u003cp\u003eFigures 3(b)\u0026ndash;(d) present the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e and the corresponding \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e differences (\u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e) as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e(=\u003cem\u003eV\u003c/em\u003e\u003csub\u003eRead\u003c/sub\u003e), \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e, and \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e, respectively. The read \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003es are shown for three cells with distinct conductance levels, and the current difference between any two \u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e values is denoted as \u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e. In V-NAND flash memory-based neural network, this \u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e serves as an effective representation of synaptic weight, as it reflects the differential conductance that determines the weighted contribution during VMM. From the \u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e trends under varying bias conditions, it is observed that increasing \u003cem\u003eV\u003c/em\u003e\u003csub\u003eWL\u003c/sub\u003e initially enhances \u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e but eventually leads to a reduction, exhibiting a non-monotonic behavior. In contrast, both \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e show a consistent trend where \u0026Delta;\u003cem\u003eI\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e increases monotonically with higher bias levels. Based on this observation, it is feasible to mitigate the temperature-induced increase in effective weight magnitude by applying lower \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e or \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e values during read operations at elevated temperatures.\u003c/p\u003e\n\u003cp\u003eFigure 4 shows the variation of the normalized weight (\u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e) as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e, along with the corresponding trend lines. The weights were normalized such that their values were distributed within the range of \u0026minus;1 to 1. Figure 4(a) compares the \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e at 55⁰C to that at 25⁰C, while Figure 4(b) compares the \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e at 85⁰C to that at 25⁰C. For the high-temperature measurements, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e was initially set to the typical read bias of 0.4 V, and \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e at 25⁰C was measured by incrementally adjusting \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e in 0.1 V steps. When the same \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e as used at high temperatures was applied at 25⁰C (red), a decrease in the absolute magnitude of \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e was observed, resulting in a trend line slope less than unity. Conversely, when \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e was increased by 0.1 V to 0.5 V at 25⁰C (green), the absolute value of \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e increased, yielding a trend line slope greater than unity. However, the results indicate that adjusting \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e values in discrete 0.1 V increments is insufficient for precisely compensating for the temperature-induced weight variations.\u003c/p\u003e\n\u003cp\u003eFigure 5 presents the variation of \u003cem\u003eN\u003c/em\u003e\u003csub\u003ew\u003c/sub\u003e as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e, following a methodology similar to that of Figure 4 but focusing on \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e instead of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e. In the high-temperature conditions, \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e was fixed at 5 V, and at 25⁰C, \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e was incrementally adjusted in 0.1 V steps. Unlike the case of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e adjustment, tuning \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e enabled significantly finer compensation for temperature-induced weight variations, allowing the trend line slope to be closely aligned with the ideal value of unity. These results suggest that dynamic adjustment of \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e is far more effective and precise than modifying \u003cem\u003eV\u003c/em\u003e\u003csub\u003eBL\u003c/sub\u003e for compensating weight shifts caused by temperature variations. Therefore, \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e modulation is recommended as a more reliable approach for achieving thermally robust neural network operation using V-NAND flash memory.\u003c/p\u003e\n\u003cp\u003e2.3 Dynamic pass bias scheme\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eFigure 6 demonstrates the effectiveness of the proposed dynamic pass bias (DPB) scheme. To evaluate the impact of DPB, CIFAR-10 image classification simulations were conducted using the PyTorch framework with a VGG-11 architecture and the stochastic gradient descent (SGD) optimizer. The ADC at the output of the neural network was configured with 4-bit resolution. Figure 6(a) presents the threshold voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e) tuning error\u0026mdash;defined as the deviation from the target \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e\u0026mdash;introduced by the incremental step pulse programming (ISPP) method, the conventional programming approach for V-NAND flash memory [23]. Since the weights are programmed into the V-NAND flash memory during weight transfer, the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e error distribution was incorporated into the simulations to reflect realistic device characteristics. Figure 6(b) shows the CIFAR-10 image classification accuracy averaged over ten independent simulation runs as a function of the training epoch. A baseline accuracy of 80.14% was achieved after 200 epochs without temperature effects. Figure 6(c) illustrates the impact of varying \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e levels at different temperatures on the classification accuracy. For consistency, the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at 85⁰C\u0026mdash;the highest temperature measured\u0026mdash;was fixed at 5 V, ensuring that the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at lower temperatures remained above 5 V to maintain sufficiently low resistance in the pass cells during read operations. Figure 6(c-1) shows the variation in accuracy at 85⁰C when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e value used at 25⁰C is altered. When \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at 25⁰C was increased to 5.9 V, compared to the case where both temperatures used a \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e of 5.0 V, an improvement of approximately 10.52 percentage points (%p) in classification accuracy was achieved. Figure 6(c-2) examines the accuracy at 55⁰C when the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at 25⁰C is fixed at 5.9 V. Adjusting \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e at 55⁰C to 5.2 V further enhanced the accuracy by approximately 2.68%p compared to the case with \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e of 5.9 V at both 25⁰C and 55⁰C. Finally, Figure 6(d) compares the CIFAR-10 classification accuracy as a function of temperature, with and without applying the DPB scheme. Although the DPB-compensated accuracy does not fully recover to the 25⁰C baseline of 80.14%, a substantial improvement in accuracy across different temperatures is clearly observed with the use of DPB.\u003c/p\u003e\n\u003cp\u003e2.4 Temperature-adaptive circuit for DPB\u0026nbsp;\u003c/p\u003e\n\u003cp\u003eTo enable automatic compensation of the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e in response to ambient temperature fluctuations, we propose a temperature-adaptive circuit structure as illustrated in Figure 7(a). The proposed circuit consists of a single-crystalline silicon (Si) channel MOSFET in series with a V-NAND flash memory block, followed by an operational amplifier (op-amp) stage that amplifies the voltage across the V-NAND strings. In this configuration, the temperature-dependent resistance behavior of each component plays a crucial role. Specifically, the resistance of the single-crystalline Si channel MOSFET increases with temperature due to enhanced phonon scattering [24], which reduces carrier mobility. In contrast, the resistance of the V-NAND string decreases with temperature, primarily because the poly-Si channel in the string exhibits increased carrier mobility at elevated temperatures. As these two opposing temperature responses are connected in series, the voltage division between them dynamically shifts. With increasing temperature, the growing resistance of the MOSFET causes a larger voltage drop across it, thereby reducing the effective voltage applied to V-NAND strings. However, the use of the MOSFET and V-NAND string alone is insufficient to produce the exact \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e variation required to match the compensation range observed in neural network inference. Therefore, an op-amp is introduced to amplify the temperature-dependent voltage and generate a tunable output bias. By adjusting the reference voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eRef\u003c/sub\u003e) and the resistor values (\u003cem\u003eR\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e, \u003cem\u003eR\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e) in the op-amp feedback network, the output voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e) can be configured to fall within the desired range over temperature. The V-NAND string block incorporates 200 parallel-connected V-NAND strings, reflecting realistic V-NAND flash memory architecture and reducing variability among individual strings. The proposed temperature-adaptive circuit can be integrated into the peripheral circuitry of the V-NAND flash memory.\u003c/p\u003e\n\u003cp\u003eTo verify the feasibility of the proposed temperature-adaptive circuit for DPB, SPICE simulations were conducted using a validated V-NAND flash memory model from prior research [25]. Simulation parameters included \u003cem\u003eV\u003c/em\u003e\u003csub\u003eDD\u003c/sub\u003e = 10 V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eG\u003c/sub\u003e = 13 V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003eRef\u003c/sub\u003e = 6 V, and \u003cem\u003eR\u003c/em\u003e\u003csub\u003e1\u003c/sub\u003e=\u003cem\u003eR\u003c/em\u003e\u003csub\u003e2\u003c/sub\u003e. The MOSFET was modeled with a channel length of 10 \u0026mu;m and width of 500 nm, and the WLs of each V-NAND string were biased with a pass bias of 5 V. The simulated output voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eout\u003c/sub\u003e)\u0026mdash;the generated pass bias\u0026mdash;exhibited a controlled decrease with temperature, as shown in Figure 7(b), aligning well with the optimal \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e profile required for accuracy recovery in CIFAR-10 inference (Figure 6(d)). When this temperature-adaptive circuit was integrated into the DPB framework, CIFAR-10 classification simulations exhibited a substantial improvement in accuracy, confirming the practical effectiveness of the circuit-assisted compensation scheme.\u003c/p\u003e\n\u003cp\u003eThis self-regulating mechanism suggests a novel approach to implementing DPB control. Rather than relying on explicit temperature sensing and digital feedback control, the circuit can inherently adjust \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e in real time according to the ambient thermal condition. This approach offers a compact and energy-efficient solution for enhancing the thermal robustness of V-NAND flash memory-based neural networks.\u003c/p\u003e"},{"header":"3. Conclusion","content":"\u003cp\u003eIn this work, we investigated the impact of temperature variations on synaptic weights stored in vertical NAND (V-NAND) flash memory for neuromorphic computing applications. Electrical measurements revealed that the bit-line current and resulting synaptic conductance exhibit significant sensitivity to ambient temperature changes, leading to substantial degradation in neural network inference accuracy. Traditional compensation techniques for thermal instability often require substantial hardware modifications or reprogramming overhead, which are undesirable for lightweight neuromorphic systems.\u003c/p\u003e\u003cp\u003eTo address this challenge, we proposed a dynamic pass bias (DPB) control scheme that dynamically adjusts the pass bias (\u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e) during read operations based on the operating temperature. Through systematic measurements and simulations, we demonstrated that \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e modulation effectively counteracts temperature-induced conductance variations without modifying the stored cell states. The effectiveness of the DPB scheme was validated using CIFAR-10 image classification simulations with a VGG-11 architecture and 4-bit ADCs. The results showed that the application of DPB improved inference accuracy by up to 10.5%p compared to conventional fixed-bias operations, significantly enhancing the temperature resilience of the system.\u003c/p\u003e\u003cp\u003eTo further support practical implementation, we also introduced a temperature-adaptive biasing circuit composed of a single-crystalline silicon MOSFET and V-NAND strings connected in series. By leveraging the opposing temperature dependencies of their resistances, the circuit inherently adjusts \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e without external sensing or control. This passive analog approach offers a promising direction for realizing real-time, energy-efficient DPB control without additional digital logic or feedback mechanisms.\u003c/p\u003e\u003cp\u003eThe proposed DPB control method offers a simple, scalable, and hardware-efficient solution for maintaining stable neural network performance across a wide range of temperatures. Future work will focus on further optimizing the \u003cem\u003eV\u003c/em\u003e\u003csub\u003ePass\u003c/sub\u003e adjustment algorithms, extending the approach to more complex deep learning architectures, and implementing real-time temperature-adaptive control mechanisms for fully integrated V-NAND-based neuromorphic processors.\u003c/p\u003e"},{"header":"Declarations","content":"\u003ch2\u003eAcknowledgements\u003c/h2\u003e\n\u003cp\u003eThis work was supported in part by the BK21 FOUR Program of the Education and Research Program for Future ICT Pioneers, Seoul National University, in 2025; and in part by SK hynix Inc., in 2025; and in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2025-10032968).\u003c/p\u003e\n\u003ch2\u003eAvailability of data and material\u003c/h2\u003e\n\u003cp\u003eThe data that support the findings of this study are available from the corresponding author upon reasonable request and with permission of SK hynix Inc.\u003c/p\u003e\n\u003ch2\u003eCompeting interests\u003c/h2\u003e\n\u003cp\u003eThe authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.\u003c/p\u003e\n\u003ch2\u003eFunding\u003c/h2\u003e\n\u003cp\u003eThis work was supported by Seoul National University, SK hynix Inc. and National Research Foundation of Korea (NRF).\u003c/p\u003e\n\u003ch2\u003eAuthor\u0026rsquo;s contribution\u003c/h2\u003e\n\u003cp\u003eS.-H.P., J.I. and J.K. conceived the idea, designed the experiments, and wrote the original draft. S.-H.P., J.I. and J.K. also performed methodology development, investigation, formal analysis, and data curation. J.H. participated in experiments. Y.Y and J.-W.B. contributed to data curation. R.-H.K., I.-S.L., D.S., M.O. and G.J. participated in reviewing and editing the manuscript. J.-H.L participated in manuscript review and editing. All authors have given approval to the final version of the manuscript.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n \u003cli\u003eY. LeCun, Y. Bengio, G. Hinton, \u0026ldquo;Deep learning.\u0026rdquo; Nature \u003cstrong\u003e521\u003c/strong\u003e, 436\u0026ndash;444 (2015). https://doi.org/10.1038/nature14539.\u003c/li\u003e\n \u003cli\u003eM. I. Jordan, T. M. Mitchell, \u0026ldquo;Machine learning: Trends, perspectives, and prospects.\u0026rdquo; Science \u003cstrong\u003e349\u003c/strong\u003e, 255\u0026ndash;260 (2015). https://doi.org/10.1126/science.aaa8415.\u003c/li\u003e\n \u003cli\u003eG. W. Burr, R. M. Shelby, A. Sebastian, S. Kim, S. Kim, S. Sidler, K. Virwani, M. Ishii et al., \u0026ldquo;Neuromorphic computing using non-volatile memory.\u0026rdquo; Adv. Phys. X \u003cstrong\u003e2\u003c/strong\u003e, 89\u0026ndash;124 (2017). https://doi.org/10.1080/23746149.2016.1259585.\u003c/li\u003e\n \u003cli\u003eD. Markovic, A. Mizrahi, D. Querlioz, J. Grollier, \u0026ldquo;Physics for neuromorphic computing.\u0026rdquo; Nat. Rev. Phys. \u003cstrong\u003e2\u003c/strong\u003e, 499\u0026ndash;510 (2020). https://doi.org/10.1038/s42254-020-0208-2.\u003c/li\u003e\n \u003cli\u003eC. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. Date, B. Kay, \u0026ldquo;Opportunities for neuromorphic computing algorithms and applications.\u0026rdquo; Nat. Comput. Sci. \u003cstrong\u003e2\u003c/strong\u003e, 10\u0026ndash;19 (2022). https://doi.org/10.1038/s43588-021-00184-y.\u003c/li\u003e\n \u003cli\u003eS. Park, A. Sheri, J. Kim, J. Noh, J. Jang, M. Jeon, B. Lee, B. R. Lee et al., \u0026ldquo;Neuromorphic speech systems using advanced ReRAM-based synapse.\u0026rdquo; in 2013 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2013, pp. 25.6.1\u0026ndash;25.6.4. https://doi.org/10.1109/IEDM.2013.6724692.\u003c/li\u003e\n \u003cli\u003eO. Bichler, M. Suri, D. Querlioz, D. Vuillaume, B. Desalvo, C. Gamrat, \u0026ldquo;Visual Pattern Extraction Using Energy-Efficient \u0026ldquo;2-PCM Synapse\u0026rdquo; Neuromorphic Architecture.\u0026rdquo; IEEE Trans. Electron Devices \u003cstrong\u003e59\u003c/strong\u003e, 2206\u0026ndash;2214 (2012). https://doi.org/10.1109/TED.2012.2197951.\u003c/li\u003e\n \u003cli\u003eH. Mulaosmanovic, J. Ocker, S. Muller, M. Noack, J. Muller, P. Polakowski, T. Mikolajick, S. Slesazeck, \u0026ldquo;Novel ferroelectric FET based synapse for neuromorphic systems.\u0026rdquo; in 2017 IEEE Symposium on VLSI Technology (VLSI), Kyoto, Japan, 2017, pp. T176\u0026ndash;177. https://doi.org/10.23919/VLSIT.2017.7998165.\u003c/li\u003e\n \u003cli\u003eW. Jung, H. Kim, D. B. Kim, T. H. Kim, N. Lee, D. Shin, M. Kim, Y. Rho et al., \u0026ldquo;A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.\u0026rdquo; in 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 236\u0026ndash;237. https://doi.org/10.1109/ISSCC49657.2024.10454343.\u003c/li\u003e\n \u003cli\u003eS. H. Park, D. Kwon, H. N. Yoo, J. W. Back, J. Hwang, Y. Yang, J. J. Kim, J. H. Lee, \u0026ldquo;Retention Improvement in Vertical NAND Flash Memory Using 1-bit Soft Erase Scheme and its Effects on Neural Networks.\u0026rdquo; in 2022 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 5.5.1\u0026ndash;5.5.4. https://doi.org/10.1109/IEDM45625.2022.10019529.\u003c/li\u003e\n \u003cli\u003eS. T. Lee, H. Kim, J. H. Bae, H. Yoo, N. Y. Choi, D. Kwon, S. Lim, B. G. Park et al., \u0026ldquo;High-Density and Highly-Reliable Binary Neural Networks Using NAND Flash Memory Cells as Synaptic Devices.\u0026rdquo; in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 38.4.1\u0026ndash;38.4.4. https://doi.org/10.1109/IEDM19573.2019.8993478.\u003c/li\u003e\n \u003cli\u003eS. S. Li, W. R. Thurber, \u0026ldquo;The dopant density and temperature dependence of electron mobility and resistivity in n-type silicon.\u0026rdquo; Solid State Electron. \u003cstrong\u003e20\u003c/strong\u003e, 609\u0026ndash;616 (1977). https://doi.org/10.1016/0038-1101(77)90100-9.\u003c/li\u003e\n \u003cli\u003eI. Giannopoulos, M. L. Gallo, V. P. Jonnalagadda, E. Eleftheriou, A. Sebastian, \u0026ldquo;Temperature Compensation Schemes for In-Memory Computing using Phase-Change Memory.\u0026rdquo; in 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Genova, Italy, 2020, pp. 286\u0026ndash;290. https://doi.org/10.1109/AICAS48895.2020.9074003.\u003c/li\u003e\n \u003cli\u003eS. H. Park, J. Ko, I. S. Lee, R. H. Koo, J. H. Kim, Y. Yang, D. Kwon, J. J. Kim et al., \u0026ldquo;On-Chip Learning in Vertical NAND Flash Memory Using Forward\u0026ndash;Forward Algorithm.\u0026rdquo; IEEE Trans. Electron Devices \u003cstrong\u003e71\u003c/strong\u003e, 3640\u0026ndash;3644 (2024). https://doi.org/10.1109/TED.2024.3392170.\u003c/li\u003e\n \u003cli\u003eS. T. Lee, G. Yeom, H. Yoo, H. S. Kim, S. Lim, J. H. Bae, B. G. Park, J. H. Lee, \u0026ldquo;Novel Method Enabling Forward and Backward Propagations in NAND Flash Memory for On-Chip Learning.\u0026rdquo; IEEE Trans. Electron Devices \u003cstrong\u003e68\u003c/strong\u003e, 3365\u0026ndash;3370 (2021). https://doi.org/10.1109/TED.2021.3081610.\u003c/li\u003e\n \u003cli\u003eJ. Ko, S. H. Park, J. Im, J. Kim, R. H. Koo, Y. Yang, J. H. Lee, \u0026ldquo;Vertical NAND flash memory-based matrix-matrix multiplication scheme for energy-efficient attention score computation.\u0026rdquo; Neurocomputing \u003cstrong\u003e619\u003c/strong\u003e, 129210 (2025). https://doi.org/10.1016/j.neucom.2024.129210.\u003c/li\u003e\n \u003cli\u003eS. H. Park, H. N. Yoo, Y. Yang, J. W. Back, R. H. Koo, D. Kwon, J. J. Kim, J. H. Lee, \u0026ldquo;Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash.\u0026rdquo; Appl. Phys. Lett. \u003cstrong\u003e123\u003c/strong\u003e, 142101 (2023). https://doi.org/10.1063/5.0161000.\u003c/li\u003e\n \u003cli\u003eC. M. Compagnoni, A. Goda, A. S. Spinelli, P. Feeley, A. L. Lacaita, A. Visconti. \u0026ldquo;Reviewing the Evolution of the NAND Flash Technology.\u0026rdquo; Proc. IEEE \u003cstrong\u003e105\u003c/strong\u003e, 1609\u0026ndash;1633 (2017). https://doi.org/10.1109/JPROC.2017.2665781.\u003c/li\u003e\n \u003cli\u003eS. H. Park, H. N. Yoo, J. W. Back, J. Cho, Y. Yang, J. Im, R. H. Koo, J. Ko et al., \u0026ldquo;Retention Improvement in Vertical NAND Flash Memory Using Electron Back-Tunneling.\u0026rdquo; IEEE Electron Device Lett. \u003cstrong\u003e46\u003c/strong\u003e, 203\u0026ndash;206 (2025). https://doi.org/10.1109/LED.2024.3506507.\u003c/li\u003e\n \u003cli\u003eS. H. Park, H. N. Yoo, Y. Yang, J. J. Kim, J. H. Lee, \u0026ldquo;Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE).\u0026rdquo; IEEE Trans. Electron Devices \u003cstrong\u003e71\u003c/strong\u003e, 1834\u0026ndash;1838 (2024). https://doi.org/10.1109/TED.2024.3350000.\u003c/li\u003e\n \u003cli\u003eC. Caillat, K. Beaman, A. Bicksler, E. Camozzi, T. Ghilardi, G. Huang, H. Liu, Y. Liu et al., \u0026ldquo;3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture.\u0026rdquo; in 2017 IEEE International Memory Workshop (IMW), Monterey, CA, USA, 2017, pp. 1\u0026ndash;4. https://doi.org/10.1109/IMW.2017.7939067.\u003c/li\u003e\n \u003cli\u003eH. N. Yoo, J. W. Back, N. H. Kim, D. Kwon, B. G. Park, J. H. Lee. \u0026ldquo;First Demonstration of 1-bit Erase in Vertical NAND Flash Memory.\u0026rdquo; in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, 2022, pp. 304\u0026ndash;305. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830445.\u003c/li\u003e\n \u003cli\u003eK. D. Suh, B. H. Suh, Y. H. Lim, J. K. Kim, Y. J. Choi, Y. N. Koh, S. S. Lee, S. C. Kwon et al., \u0026ldquo;A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme.\u0026rdquo; IEEE J. Solid State Circuits \u003cstrong\u003e30\u003c/strong\u003e, 1149\u0026ndash;1156 (1995). https://doi.org/10.1109/4.475701.\u003c/li\u003e\n \u003cli\u003eG. W. Ludwig, R. L. Watters, \u0026ldquo;Drift and Conductivity Mobility in Silicon.\u0026rdquo; Phys. Rev. \u003cstrong\u003e101\u003c/strong\u003e, 1699 (1956). https://doi.org/10.1103/PhysRev.101.1699.\u003c/li\u003e\n \u003cli\u003eJ. Hwang, H. N. Yoo, K. H. Lee, J. W. Back, M. K. Park, Y. Yang, W. Y. Choi, J. H. Lee, \u0026ldquo;Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory.\u0026rdquo; IEEE Trans. Electron Devices \u003cstrong\u003e70\u003c/strong\u003e, 5469\u0026ndash;5474 (2023). https://doi.org/10.1109/TED.2023.3308086.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nano-convergence","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"ncon","sideBox":"Learn more about [Nano Convergence](https://www.springer.com/journal/40580)","snPcode":"40580","submissionUrl":"https://www.editorialmanager.com/ncon/default2.aspx","title":"Nano Convergence","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Open","inReviewEnabled":true,"inReviewRevisionsEnabled":true},"keywords":"Neural Network, Neuromorphic Computing, V-NAND Flash Memory","lastPublishedDoi":"10.21203/rs.3.rs-6798696/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-6798696/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eVertical NAND (V-NAND) flash memory has emerged as a promising candidate for neuromorphic computing platforms due to its high density, scalability, and reliability. However, synaptic weights stored in V-NAND cells are highly sensitive to ambient temperature variations, resulting in significant conductance shifts that degrade the inference accuracy of neural networks. To address this challenge, we propose a dynamic pass bias (DPB) control scheme that compensates for temperature-induced weight variations without requiring memory reprogramming or additional hardware overhead. By adaptively adjusting the pass bias applied to unselected word-lines during read operations, the DPB scheme effectively stabilizes the differential conductance representation of weights under thermal fluctuations. In addition, we introduce a temperature-adaptive biasing circuit composed of a single-crystalline silicon MOSFET and V-NAND strings. Exploiting their opposing temperature-dependent resistance characteristics, this passive circuit naturally reduces the pass bias as temperature rises, enabling real-time analog compensation without explicit sensing or digital control logic. Experimental measurements on commercial V-NAND devices fabricated with over 100 WL layers reveal substantial shifts in bit-line currents with increasing temperature. Simulation results based on CIFAR-10 image classification using a VGG-11 network demonstrate that the DPB scheme significantly mitigates accuracy degradation across a wide temperature range. Notably, adjusting pass bias at lower temperatures improves classification accuracy by up to 10.5%p compared to conventional fixed-bias operations. These results highlight the effectiveness of dynamic pass bias control\u0026mdash;both digitally and circuit-assisted\u0026mdash;as a lightweight and scalable solution for enhancing the temperature resilience of V-NAND flash memory-based neural networks.\u003c/p\u003e","manuscriptTitle":"Dynamic Pass Bias Control for Temperature-Resilient Neural Networks Using Vertical NAND Flash Memory","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2025-07-14 11:35:24","doi":"10.21203/rs.3.rs-6798696/v1","editorialEvents":[{"type":"communityComments","content":0},{"type":"decision","content":"Major revision","date":"2025-07-27T19:32:13+00:00","index":"","fulltext":""},{"type":"reviewerAgreed","content":"","date":"2025-07-10T00:32:15+00:00","index":0,"fulltext":""},{"type":"reviewersInvited","content":"","date":"2025-07-09T14:16:13+00:00","index":"","fulltext":""},{"type":"editorAssigned","content":"","date":"2025-06-02T12:28:27+00:00","index":"","fulltext":""},{"type":"submitted","content":"Nano Convergence","date":"2025-06-02T00:36:37+00:00","index":"","fulltext":""}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nano-convergence","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"ncon","sideBox":"Learn more about [Nano Convergence](https://www.springer.com/journal/40580)","snPcode":"40580","submissionUrl":"https://www.editorialmanager.com/ncon/default2.aspx","title":"Nano Convergence","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"em","reportingPortfolio":"Springer Open","inReviewEnabled":true,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"b2b7051d-e1a2-4469-abd7-b492b81fbb88","owner":[],"postedDate":"July 14th, 2025","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[],"tags":[],"updatedAt":"2025-10-06T16:12:26+00:00","versionOfRecord":{"articleIdentity":"rs-6798696","link":"https://doi.org/10.1186/s40580-025-00513-1","journal":{"identity":"nano-convergence","isVorOnly":false,"title":"Nano Convergence"},"publishedOn":"2025-09-30 15:57:09","publishedOnDateReadable":"September 30th, 2025"},"versionCreatedAt":"2025-07-14 11:35:24","video":"","vorDoi":"10.1186/s40580-025-00513-1","vorDoiUrl":"https://doi.org/10.1186/s40580-025-00513-1","workflowStages":[]},"version":"v1","identity":"rs-6798696","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-6798696","identity":"rs-6798696","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}