Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications Ram Murti Rawat, Vinod Kumar This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3992933/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Static random access memory (SRAM) is the typical memory for very large scale integrated (VLSI) circuits. A major reason for this is the high speed operation for SRAM in comparison to its previous counterparts, a major trade off for the circuit is its high power consumption. With the growing importance of memory architectures, it is crucial to lower the power consumption of SRAM cells. This major goal of this paper is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). SRAM is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The paper is organized into the following sections: 1. Introduction, Section 2 describes related work. The suggested work is explained in section 3, while the results and discussion are included in section 4. The results for all the sections are concluded in section 5 conclusions. SRAM Stability Energy efficient power High speed and Low-Power VLSI applications Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 1. Introduction More than five decades have passed since the scaling of semiconductor process technology began. The catalyst that has been propelling the semiconductor industry is the advancements in process technology. The semiconductor industry introduces a new process technology every two to three years, in response to growing customer demand for enhanced performance and functionality at reduced cost [ 1 ]. All electrical systems, including mainframes, microcomputers, mobile phones, and other devices, heavily rely on memory. Energy-efficient CPUs are becoming essential due to the rising demand for portable battery-operated systems. The dimensions, weight, and battery life of these gadgets have an impact on their performance. The IC design community has been actively seeking out new approaches and methodologies that result in more power-efficient designs, which means significant reductions in power consumption for the same level of performance, as a result of serious reliability issues, rising design costs, and battery-operated applications. Every system design includes memory circuits, which greatly increase system-level power consumption as Dynamic RAMs, Static RAMs, Ferroelectric RAMs, ROMs, or Flash Memories have significant power consumption. System performance, reliability, and costs may all be considerably increased by reducing the power dissipation of memory. Due to the rise in popularity of notebooks, laptops, hand-held communication devices, and IC memory cards in recent years, RAMs have developed extremely quickly in terms of low-power, low-voltage memory architecture. To decrease power dissipation, a number of strategies are used, including power gating, the sleepy technique, and the design of circuits with power supply (VDD) scaling. A lower VDD voltage quadratically and exponentially lowers dynamic power and leakage power, respectively. However, scaling of the VDD reduces the noise margin. A lot of SRAM arrays are built around lowering the swing voltage and active capacitance. Gate leakage and sub threshold leakage current are the major causes of leakage currents in the sub-100 nm area. Technology with high dielectric constant gates reduces gate leakage current. To lessen sub threshold leakage current, dual Vt approaches and forward body biassing are employed. The operational current in sub threshold SRAMs is the sub threshold leakage current since the VDD is lower than the transistor threshold voltage (Vt) [ 2 ]. Computer data storage, often called storage or memory, refers to computer components and recording media that retain digital data used for computing for some interval of time. The main purpose of storage is that without a significant amount of memory, a computer would merely be able to perform fixed operations and immediately output the result [ 3 ]. There are two types of memories: volatile and non-volatile. In the storage array or core, the straightforward cell circuits are stacked in horizontal rows and columns to share connections. Word-lines are the horizontal lines that are exclusively driven from the external storage array, while bit-lines are the vertical lines that carry data into and out of the cells. For reading or writing, access is made to the row and column that have been specifically chosen in a cell. Either "0" or "1" can be stored in each cell. Read-Write Random-Access Memory (RW RAM) refers to the storage of data in flip-flop circuits or simply as charge on capacitors (RAM). Because the data is volatile, there is about an equivalent delay while reading or writing it. Read-Write memories store data in an active circuit, meaning that if the power source is stopped, the recorded data will be lost. Since Read-Write Random-Access Memory is frequently referred to as RAM, RWM is the obvious shorthand for this type of memory. This research proposes a novel SRAM cell with differential write and single-ended read capabilities for IoT applications. For enhanced stability and rail to rail voltage swing, the transmission gate is employed as an access transistor. The suggested SRAM cell's analysis of leakage power and stability for VDD ranging from 0.9V to 0.5V is contrasted with that of the current 5T and 6T SRAM bit cells at 32nm technology. The transistor stacking effect is employed to reduce the SRAM cell's leakage current. By separating the read line from the node that is responsible for the read disturbance problem, stability is increased[ 4 ]. This article explains the low-power 8T SRAM cell memory cell suggested design. In the suggested method, two PMOS transistors are used, one of which is linked to the node voltage Q and the other to the Qbar. the bit and bit bar lines' swing voltage must be eliminated. The swing voltage is reduced when the cell is operating, which lowers the dynamic power dissipation. A sequence of leakage current decreases occurs when the transistors go from being inactive to being active and vice versa thanks to the precharge voltage level approach, which uses an NMOS transistor as a resister and a PMOS transistor as a switchThe comparison's results demonstrate that the proposed 8T SRAM cell's read, write, and hold mode operation is superior to that of the 6T SRAM cell. This occurs regularly as a result of the increased static noise margins produced, which guarantee good bit cell write ability [ 5 ]. 2. Related Work Several schemes have been proposed about the improved stability as well as energy efficient for SRAMs in present-day low power analysis. Following is a discussion about the work done in improved stability and energy efficient SRAMs. Since the speed of early days electronic system was very slow, because the speed of memory was not comparable to the processor speed. Hence the cache memory is used for enhancing the speed of overall system. Currently, On static random access memory, the cache memory is built. SRAM cell count on a single chip for a domain-specific architecture ‖ (DSA) is reaching to hundreds of megabits. This is resulted in two crucial challenges. The first challenge is the increasing inefficiency in SRAM array size with the newest CMOS technologies while the second challenge is the static power dissipation due to various leakage current which flows from the higher VDD through the SRAM cell to the lower VDD [ 6 ]. This necessitates the need to design SRAM with minimal leakage since this reduces static power dissipation significantly. One of the suggested solutions to the power dissipation problem is to scale back the VDD, but the reliability of the SRAM cell poses another challenge in this. Besides this, issues like data stability, delay and high sensitivity to process variation [ 7 – 12 ] also contributes to overall performance of SRAM. Figure 2.1 depicts the conventional 6T SRAM cell consisting of four NMOS (NM 4 , NM 5 , NM 6 and NM 7 ) and two PMOS (PM 3 and PM 4 ) transistors. At scaled cell VDD, the 6T SRAM cell encounters several issues like stability, delay, high sensitivity to process variation etc. [ 11 ]. The SRAM cell stability is mainly affected by the strength of transistors which form internal latch and access transistors. Hence, the weak pull-up transistor of the internal latch and strong access transistor are required for maintaining the write ability, while a strong pull-down transistor of the internal latch and weak access transistor is required for read stability [ 10 ]. During the write operation in the SRAM cell, the conventional 6T SRAM cell provides a poor write ability due to disturbance in the node voltage at the down scaled cell VDD [ 13 ]. Several write assist techniques are known in the literature currently in use to improve the write capabilities of SRAM cells. Among them the popular ones are negative bit line, V DD collapse, boosted V SS , word-line boosting etc. [ 14 – 18 ]. The negative bit-line write assist circuit technique has been proposed by Y. H. Chen, et al. [ 16 ]. When the bit lines of SRAM cells are used with a negative voltage rather than with ground, the gate to source voltage (VGS) of the access transistors is increased as a result. Therefore, increasing the voltage increases the SRAM cell's access transistors' driving capacity without affecting the inside latch. However, in this technique, the bit-line capacitance has been increased by boosted capacitor which eventually increases the access time [ 16 ]. On the contrary, in V DD collapse technique, proposed by E. Karl, et al. [ 17 ], the weakening of the internal latch during a write operation is performed for improving the write ability, but the reduction in cell VDD in the technique disturbs the stored node voltage, thereby resulting in data loss during read or hold operation. In boosted word-line write assist technique [ 18 ], the word-line voltage is increased which also increases the gate to source voltage of access transistors, thereby increasing the static power dissipation. As a result, this method is likewise not appropriate for low voltage operation. In addition to this, attempts were also made by B. Wang, et al. [ 19 ] proposing ultra-low voltage 9T SRAM cell (9T UV SRAM), M. H. Tu, et al. [ 20 ], A. Banerjee, S. Kamineni and B. H. Calhoun [ 21 ] etc. to reduce the static power dissipation and for improvement of read/write operation. However, the results obtained are not promising. To address stability and delay difficulties in SRAM, an unique negative bit-line (NBL) circuit is proposed then put into action using an 8T SRAM cell. In the recommended architecture, one of the bit lines produces a negative voltage during the write operation (due to the NBL circuit), which enhances the access transistors' driving capacity and, as a result, the writing ability. To increase the cell's stability during read operation, a separate or isolated read port is employed. As a consequence, the suggested improvement has improved cell stability and decreased its latency. 3. Proposed Work The following is a description of the proposed work.. 3.1 Negative Bit-line generator circuit (NBL) Applying a negative voltage to one of the bit lines (BL or BLB) of the SRAM cell decreases the gate to source voltage (VGS) of the access transistor in the proposed circuit. The major function of the NBL circuit is to deliver a negative voltage instead of 0V at the BL/BLB of an SRAM cell, depending on the operating conditions. The suggested NBL generator circuit is depicted in Fig. 3.1 (a) and is constructed utilising four NMOS, three PMOS, and two NOR gates. The NOR gate's inputs in the NBL circuit are the Din, Dinb, and WR signals, while the NOR gate's output is connected to the inputs of the NMOS and PMOS transistors [ 27 ]. The NBL circuit performs the following operations: Case 1 NBL circuit in write mode when logic "1" is used. While applying logic levels "1" and "0," respectively, to the Din and Dinb signals, logic level "0" is applied to WR in a write logic "1" operation. Inverted Din and Dinb signals are always the NOR gate's output signals. As a result, NOR1 and NOR2 output "0" and "1," respectively. Transistor NM1 would turn to an OFF state, and NM2 would go into an ON state. Transistor PM1 would also be ON and PM2 would be OFF in addition to this. As a result, the bit-line (BL) would change to logic high (VDD), and the bit-line bar's (BLB) state would rely on two additional scenarios related to the status of the WE and WEN signals. Case A The WEN signal's counterpart logic "1" is applied when the WE signal is at logic "0" (as shown in Fig. 3.1 (b))[ 27 ]. As a result, the transistor NM0 is turned off by the WE signal, and the transistor PM0 is turned on, which then turns on the transistor NM3. The triode region in which the ON transistor NM3 works provides a resistance across it. The RC network is made up of a capacitor (C) and the transistor NM3 (RON) resistance (the circuit works as a RC differentiator). Because the WEN signal (at the starting point) is a rising pulse and the slope at the positive edge is particularly large, the capacitor acts as a short circuit, the input voltage (the voltage of the WEN signal) and the voltage at node X (the voltage across the RON or VX) are equal at this point. When the WEN signal reaches logic "1" after the positive edge, the capacitor starts to charge through resistance RON. As a result, until the capacitor is fully charged, the voltage at node X or VX quickly decreases (as shown in Fig. 3.1 (b)) (charging of capacitor depends on time constant RONC). As a result, in this circumstance, the voltage at BLB and VX are equal. Case B The WEN signal's counterpart, logic "0," is applied when the WE signal is at logic "1." As a result, the transistor PM0 is turned off by the WE signal, while the transistor NM0 and NM3 are turned on (because capacitor does not allow the sudden change in voltage thus the gate of NM3 is connected to node X through NM0 transistor). An RC network is created in a manner similar to scenario A. The negative edge of the WEN signal has a very steep slope, and since the WEN signal is a falling pulse, the capacitor does not react well to steep slopes. As a result, a negative spike develops at this point. The capacitor discharges when the WEN signal reaches logic "0" following a negative edge. As the capacitor drains, the voltage at node X or VX increases exponentially (as seen in Fig. 3.1 (b)) (discharging of capacitor also depends on time constant RONC). As a result, in this instance, the voltage at BLB is also equal to the negative voltage, or VX voltage. Case II When writing logic "0," the NBL circuit. The Din and Dinb signals are respectively, at logic levels "0" and "1," the logic "0" is applied to WR in order to perform a write logic "0" operation. The output signals of the NOR1 and NOR2 gates are, respectively, at logic "1" and "0." Transistor NM1 would go to the ON state, whereas NM2 would go into the OFF state. Additionally, transistors PM1 and PM2 would be ON and OFF respectively. As a result, the bit-line bar (BLB) would change to logic high (VDD), and the bit-line (BL) state would likewise rely on the WE and WEN signal states for the additional two instances A and B (as mentioned for scenario I). As a result, when WEN is set to logic "0," the bit-line (BL) receives a negative voltage. Case III The NOR gate would always produce a zero output during a read and hold operation, which would then activate the PMOS (PM1 and PM2) and deactivate the NMOS (NM1 and NM2) transistors. The WR signal is always at logic "1" during a read and hold operation, hence the NOR gate would always output zero regardless of Din and Dinb values. The PMOS (PM1 and PM2) transistors are used to link the BL or BLB and VDD. The aforementioned Cases A and B have no impact on the read and hold operation since the NMOS (NM1 and NM2) transistors are in the OFF state and the node X disconnects from the bit-lines (BL/BLB). Since the bit-lines (BL/BLB) are switched to VDD during read and hold operations, the proposed NBL circuit provides a negative voltage at one of the bit-lines (BL/BLB) during the write operation [ 22 ]. 3.2 Proposed design (NBL circuit with 8T SRAM cell) The suggested design (PD), which implements an NBL circuit with an 8T SRAM cell, is shown in Fig. 3.2 . There are eight transistors in an 8T SRAM cell. The SRAM's internal latch, where the data is kept, is built using the transistors NM4, NM5, PM3, and PM4. The separate read port for accessing data from the SRAM cell is formed by transistors NM8 and NM9. The data-storing nodes of an SRAM cell are node Q and node Qb. While transistor NM9 functions as an access transistor during read operation and is triggered by the read word line (RWL) signal, transistors NM6 and NM7 function as write access transistors. The read bit line (RBL) functions as an input/output line under read operation, whereas the bit lines (BL/BLB) function as an input for write operation. The following is a discussion of the different operations of the proposed design: 3.2.1 Write Operation Figure 3.3 shows the circuit's behaviour during write operations. (In this instance, a dotted line represents an OFF transistor.) The WWL signal is given the write operation logic "1," which activates the access transistors NM6 and NM7. Write logic "1" for at node Q. The nodes Qb and Q, respectively, are initially where logic "1" and "0" are stored. 1. At the nodes Qb and Q, respectively, logic "1" and "0" are initially stored. 2. BL and BLB are given the logic values "1" and "0," respectively. In the suggested architecture, the NBL circuit is linked to the bit-lines. The WR signal is at logic "0" for write operation in the NBL circuit, whereas the Din and Dinb signals are at logic "1" and "0," respectively. As a result, the BLB is driven at negative potential while the BL is driven at VDD (as discussed in section 3.1). The negative voltage at the BLB causes the gate to source voltage (VGS) of the access transistor (NM7) to rise, which in turn raises NM7's driving capacity. Due to node Qb being forced to discharge quickly and acquire 0V as a result of transistor NM7 acting much faster than transistor NM6 in Fig. 3.3 (a), transistor PM3 is turned ON and transistor NM4 is turned OFF. Thus, transistor PM3 connects the storing node Q to the VDD, whereupon the logic "1" is afterwards stored. 3.2.2 Read Operation Figure 3.4 shows the circuit behaviour of the proposed design (with the OFF transistor shown by the dotted line) during a read operation. The output of the NOR gate would always be at a low voltage, activating the PMOS, because the WR must always be at logic "1" in order to read data from the SRAM cell. As a result, the bit lines (BL or BLB) have always been set to logic "1". During a read operation, RBL is pre-charged at logic "1," the WWL signal is at logic "0," RWL is at logic "1," and so on. Assume initially that nodes Q and Qb are where logic level "0" and "1" are kept for read logic "0" operations. The transistor NM8 turns ON owing to logic "1" stored at node Qb, which is coupled to the transistor NM8's gate (as illustrated in Fig. 3.3 (b)). With the help of transistors NM8, and NM9, a route (depicted by an arrow) is created between RBL and ground. Thus, as seen in Fig. 3.4, the RBL is discharged to 0 V. The read logic "0" operation has therefore been carried out. 3.2.3 Hold operation The access transistors NM6, NM7, and NM9 are turned off as a result of the RWL and WWL being maintained at logic "0" during the hold operation. The BL, BLB, and RBL are constantly at logic "1" because the WR in the NBL circuit is always at logic "1." The internal latch of the SRAM cell is disconnected from the bit-lines in hold mode of operation, preserving the data stored inside. A large amount of static power was also lost by the SRAM cell during the hold mode due to leakage current, mostly sub-threshold leakage current because the bulk of the transistors are still in the OFF state. Consequently, the suggested design reduces static power dissipation. The NM9 transistor Y node generates a positive voltage as a result of self-reverse biassing. This positive voltage lowers the drain to source (VDS) and gate to source (VGS) voltages of OFF transistors (NM5 and NM9) while raising their threshold voltages (NM5 and NM9). 4. Results and Discussion The performance of the given design has been predicted using the cadence virtuoso tool for circuit design and simulation utilising the UMC 28 nm CMOS technology node. The following are the simulated findings for the proposed design's different performance parameters: 4.1 Write ability The stability of the SRAM cell is defined as the greatest noise voltage that cannot flip the state of the storing node in the SRAM cell. Write static noise margin (WSNM), which is acquired via a sweeping approach, serves to define the SRAM's write capability. This technique sweeps the voltage at one node (Q) from zero to the VDD, then plots it against the analogous voltage at another node (Qb) to get the voltage transfer characteristic curve (VTC). The process is then repeated, but this time to generate a comparable graph to the analogical VTC at node Q, the voltage at node Qb is swept from 0V to the maximum VDD. Last but not least, the two VTC curves are blended into a graphic called a butterfly plot. The butterfly plot, in which a square is produced and the longest vertical side is taken into account as the WSNM value, determines the WSNM [ 23 – 24 ]. Figure 4.1 illustrates the butterfly curve of the suggested design for calculating the write-operational WSNM value at 1V cell VDD and 27°C temperature with TT corner. When compared to an 8T SRAM cell without an NBL circuit, the suggested design's WSNM is 490 mV. Since the 8T SRAM cell with the NBL circuit improves the WSNM value by 1.53x over the SRAM cell without the NBL circuit, it is preferable to have this feature included. Figure 4.2 shows the comparison of the proposed design with the standard 6T SRAM cell, the VDD collapse write assist approach, the NBL write help technique, and the 9T UV SRAM cell at various cell VDDs. Because there is a significant likelihood of flipping the data of SRAM cells at lower VDDs, it has been shown that WSNM rises with VDD. As a result, the cell is less stable at lower VDDs than it is at higher VDDs. Additionally, when developed at 1V using the same technology node, the WSNM of the suggested design is improved by 48%, 11%, 19%, and 32.4% over basic 6T SRAM cell [ 11 ], NBL [ 16 ], VDD collapse [ 17 ], and 9T UV SRAM [ 19 ], respectively. This increase was made possible by a negative bit-increased line's ability to boost the access transistor's VGS. The WSNM of the suggested design is shown in Fig. 4.3 at various temperatures. When the temperature rises from − 40°C to 120°C at 1V, it can be shown that the WSNM value of the suggested design falls from 580 mV to 430 mV. This is due to the threshold voltage decreasing with temperature. As a result, the SRAM cell's data values deteriorate. So, at high temperatures, the SRAM cell is less stable. Comparing the suggested design to the basic 6T and other current designs, as shown in Fig. 4.3, the proposed design exhibits nominal performance in terms of WSNM even with the increase in temperature. The yield of the suggested design has been determined and validated using a Monte Carlo simulation for process variation and mismatch. For transistor parameters that are normally distributed and uncorrelated, the Monte Carlo simulation approach replaces the fixed Gaussian distribution with a random value. The simulation result for WSNM demonstrates that the proposed design is lesser sensitive to mismatching and process variations as standard deviation (σ) is only 0.09V (as depicted in Fig. 4.4 ) when 200 number of samples have been considered for the analysis. The mean value (µ) of proposed design is 490 mV whereas the variability (σ/µ) is 0.18. 4.2 Read Stability The read stability of the SRAM cell is defined through the read static noise margin (RSNM), which is also obtained using the butterfly plot [ 25 ]. The butterfly curve for the read stability in the read operation is shown in Fig. 4.5 . The greatest side length of the square produced inside the smaller lobe of the butterfly curve is used to evaluate the proposed design's RSNM value. It should be noted that the suggested design's RSNM value is 400 mV at 1V for the cell. The fluctuation in RSNM values for the proposed design and prior published studies at various cell VDDs are shown in Fig. 4.6 . The RSNM is very low at the lower VDD, and as the voltage rises, the RSNM likewise rises. It can be noticed that there is an enhancement in RSNM of proposed design by 81%, 42%, 29%, over basic 6T SRAM cell [11] , NBL [16] , V DD collapse [17] respectively, whereas decrement by 4.8% over 9T UV SRAM [19] when designed at 1V using same technology node. In the suggested architecture, a dedicated or isolated read port is used to accomplish this increase in RSNM. The WWL signal is at logic "0" during the read operation, isolating the storage nodes from the bit-lines (BL/BLB). As a result, there has been no disruption or degradation of the data held in nodes (Q/Qb). As a result, the suggested design is quite stable when being read. The RSNM value of the suggested design is shown in Fig. 4.7 at various temperatures. Due to the lower threshold voltage of transistors when temperature rises, the suggested design's RSNM value lowers. Additionally, Fig. 4.7 compares the suggested architecture to different SRAM designs. It is clear that the suggested design delivers the best results for read operation at a specific temperature. 4.3 Hold Stability Hold static noise margin is used to measure the SRAM cell's stability in hold mode (HSNM). This is possible using the butterfly plot, as seen in Fig. 4.8 . It has also been highlighted that the HSNM value of the proposed design is 350 mV at 1V for the cell. At various cell VDDs, Fig. 4.9 compares the HSNM value of the proposed design to that of other current designs. In the hold mode of the proposed architecture, the internal latch is isolated from the bit-lines. As a result, there is no data loss and the SRAM cell is more stable in hold mode. Also, it can be noticed that there is an enhancement in HSNM of proposed design by 28%, 13%, 40%, and 8.5% over basic 6T SRAM cell [11] , NBL [16] , V DD collapse [17] and 9T UV SRAM [19] respectively when designed at 1V using similar technology node. The HSNM of the suggested design is shown in Fig. 4.10 at various temperatures. It has been noted that the HSNM value of the suggested design, when operating at 1V cell, reduces when temperature increases from − 40°C to 120°C. Additionally, a comparison of the suggested architecture with a standard 6T SRAM cell and other cutting-edge work is shown. This may be used to show that the proposed design's HSNM performs better than alternative designs at different temperatures. 4.4 Static Power Dissipation At lower technology node SRAM cell also faces the issue of static power dissipation. The numerous leakage currents in a circuit are the major cause of static power dissipation. The leakage current includes sub-threshold leakage current, junction leakage current, gate leakage current, and so on [ 26 ]. Figure 4.11 displays the dynamic power dissipation of the proposed architecture at different VDDs. The static power dissipates more when the cell VDD is increased. The recommended design's static power dissipation is 430 pW at a cell VDD of 1 V. (190 pW by an 8T SRAM cell and 240 pW by an NBL circuit). The suggested design has been compared to other state-of-the-art work as well as a simple 6T SRAM cell. This can be noticed that the proposed design consumes 30%, 11% and 20% more power than 6T SRAM cell [11] , V DD collapse [17] and 9T UV SRAM [19] respectively while 17% less than NBL [16] , at 1V. Due to the NBL circuit's usage of just one SRAM cell, the suggested design has a little higher static power dissipation than usual. However, by combining a single NBL circuit to several SRAM cells, static power can be reduced. The fluctuation in static power dissipation at various temperatures is seen in Fig. 4.12. Because the sub-threshold leakage current exponentially relies on the temperature and threshold voltage, the suggested device loses power as the temperature rises. As the temperature rises, the threshold voltage falls, increasing the sub-threshold leakage current. As a result, the suggested design loses more static power. 4.5 Write Delay The amount of time needed to write data at storage nodes (Q/Qb) is computed as the time interval starting when the WWL signal reaches 50% of its highest value during the write operation. At a 1V cell VDD, the suggested design's write latency is 140 ps. The write delay of the suggested design at various VDDs is shown in Fig. 4.13 , along with a comparison to other existing SRAM. This can be detected that the write delay of proposed design is reduced by 33%, 39%, 48%, and 22% when compared to 6T SRAM cell [11] , NBL [16] , V DD collapse [17] and 9T UV SRAM [19] respectively at 1V. Since the source of the access transistor is at a negative voltage during a write operation, the write latency is reduced thanks to the high driving capabilities of the access transistor. The cross coupled inverter state is flipped as a result of the node storing logic "1" discharging relatively quickly, making it simple to send data to the storage nodes. Additionally, a Monte Carlo study of the suggested design's write latency was completed and is shown in Fig. 4.14. For 200 samples, the standard deviation and mean write delay values are 32.2 and 140 ps, respectively, with a variability of 0.26. 4.6 Read Delay The period of time between the RWL signal being triggered and the RBL signal discharging to 50% of its highest value is known as the calculated read delay. At a 1V cell power source, the suggested design's read latency is 80 ps. The read latency of the suggested design at various voltages is shown in Fig. 4.15 . This can be detected that the read delay of proposed design is reduced by 52%, 33%, and 38% while increased by 18% when compared to basic 6T SRAM cell [11] , NBL [16] , V DD collapse [17] and 9T UV SRAM [19] respectively. Using an isolated read port for read operation allows for this decrease in read time. Table 4.1 Read and Write Power at Different supply Voltages. Supply Voltage (V) Read Power Write Power 0.2 59 nW 278 nW 0.4 505 nW 1.39 uW 0.6 2.16 uW 4.22 uW 0.8 6.4 uW 11.82 uW 1.0 12.5 uW 26.3 uW 4.7 Dynamic power dissipation The SRAM cell's dynamic power dissipation may be measured while it is used in write and read mode. The suggested design's write power is raised due to the NBL circuit's rise in gate to source transistor voltage, which causes access and pull-down transistor current to increase. The proposed design's read power, however, is minimal. Table 4.1 displays the dynamic power dissipation of the proposed architecture, including parasitic components, during read and write operations at various VDDs. 5. Conclusions Since low power integrated circuits are widely used in portable electronic devices, their necessity is well understood. Static Random Access Memory (SRAM) on the SoC (System on Chip) controls both the speed and power consumption of the device. Therefore, having low power SRAMs is crucial. We have been reducing the size of CMOS devices for more than 50 years in order to make them portable, small, and to achieve superior performance in terms of access time, power consumption, latency, etc. As a result, there is a greater need for memory that is small and low-powered. Working on low VDD and energy leakage has become a top priority since there is a lot of room for power consumption reduction. The oxide thickness and operating voltage continue to drop as IC manufacturing technology scales. Lower operating voltage will reduce the SRAM cell's stability, resulting in a lower static noise margin value. Certain essential factors, including static noise margin, read and write latency, static power dissipation, etc., regulate the SRAM cell. Designing an SRAM cell that performs better while taking into account all of the aforementioned characteristics at once is difficult. The designers have always had to make concessions in order to improve certain criteria at the expense of others. The necessity and application of the SRAM will determine which characteristics must be increased and which parameters can be compromised. This study offers a negative bit-line (NBL) write assist circuit for increasing the write stability of SRAM cells and a separate (isolated) read port for improving the read stability in order to increase stability and speed. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other factors, the suggested design has been compared to previous state-of-the-art work. When designed with a 1V cell, it has been shown that the WSNM has improved by 48, 11%, 19%, and 32.4%, while the write latency has decreased by 33%, 39%, 48%, and 22% when compared to standard 6T SRAM cell, NBL, VDD collapse, and 9T UV SRAM, respectively. 6. Statements and Declarations 6.1 Funding The authors affirm that they did not accept any money, grants, or other assistance for the creation of this manuscript. 6.2 Conflicts of Interest There are no material financial or non-financial interests to report for the authors. 6.3 Contributions of the Authors Prof Dr. Vinod Kumar: Conceptualization, Supervision, Methodology, Validation, Review and Editing Mr. Ram Murti Rawat: Conceptualization, Methodology, Writing, Validation, Review and Editing 6.4 Data Availability Statement We currently have no additional data. 6.5 The withdrawal notification has now been placed on your preprint, and the title has been hidden from the platform search function. Here is the link to the withdrawn preprint: https://doi.org/10.21203/rs.3.rs-2296617/v1 References J.M. Rabies, Digital integrated circuits, Prentice Hall, (1996). K . Itch, VLSI Memory Chip Design,Springer-Verlag, NY, 2001. K. Roy and S.C. Prasad. Low-Power CMOS VLSI Circuit Design. John Wiley and Sons, 2000. Chusen Duari et al.," Low Leakage SRAM Cell With Improved Stability for IoT Applications," Third International Conference on Computing and Network Communications (CoCoNet’19), pp. 1469-1478, Trivandrum, Kerala, India, 2020. R. M. Rawat and V. Kumar, “Low power pre-charge voltage level and low swing logic based 8T SRAM cell for high speed CMOS circuits," 32nd International Conference on Microelectronics (MIEL), pp. 243-246, Nis, Serbia, 2021. M. F. Chang et al., "A Compact-Area Low-V DDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme," IEEE Journal of Solid-State Circuits , vol. PP, no.99, pp.1-17, 2017. N. Zheng and P. Mazumder, "Modeling and Mitigation of Static Noise Margin Variation in Sub-threshold SRAM Cells," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. PP, no.99, pp.1-11, 2017. M. Elangovan and K. Gunavathi, "High Stable and Low Power 8T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 05, 2020. R. Lorenzo and S. Chaudhury, "Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell." Journal of Circuits, Systems and Computers 25, no. 08, 2016. C. I. Kumar and B. Anand, "Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell‖ Electronics Letters, vol. 54, no. 25, pp. 1423-1424, 2018. G. Torrens et al., "A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors," IEEE Transactions on Emerging Topics in Computing, 2017. S. R. Mansore, R. S. Gamad, and D. K. Mishra. "A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability." Journal of Circuits, Systems and Computers 29, no. 05, 2020. G. Prasad et al., "Design and statistical analysis of low power and high speed 10T static random access memory cell." International Journal of Circuit Theory and Applications, 2020. E. Karl et al., "The impact of assist-circuit design for 22nm SRAM and beyond", International Electron Devices Meeting, pp. 25-1. IEEE, 2012. J. Kulkarni, et al., ―Dual VCC 8T bitcell SRAM array in 22nm trigate CMOS for energy efficient operation across wide dynamic voltage range,‖ Symp. VLSI Circuits, pp. C126–C127, Jun. 2013. Y. H. Chen, et al., A 16nm 128Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low VMIN applications,‖ IEEE Int. Solid-State Circuits Conf., pp. 238–239, Feb. 2014. E. Karl, et al., ―A 4.6GHz 162Mb SRAM design in 22nm trigate CMOS technology with integrated active V MIN -enhancing assist circuitry,‖ IEEE Int. Solid-State Circuits Conf., pp. 230–232, Feb. 2012. A. J. Bhavnagarwala, et al., ―A sub-600-mv, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing,‖ IEEE J. Solid State Circuits, vol. 43, no. 4, pp. 946–955, Apr. 2008. B. Wang, et al., "Design of an Ultra-low Voltage 9T SRAM with Equalized Bit-line Leakage and CAM-Assisted Energy Efficiency Improvement," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 2, pp. 441-448, Feb. 2015. M. H. Tu, et al., ―Single ended sub-threshold SRAM with asymmetric a write/read-assist,‖ IEEE Trans. on Circuits Syst. I, vol. 57, no. 12, pp. 3039–3047, Dec. 2010. A. Banerjee, S. Kamineni, and B. H. Calhoun. "Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low- VMIN IoT and Cognitive Applications." In Proceedings of the International Symposium on Low Power Electronics and Design, p. 32. ACM, 2018. J. M. Rabaey, A. Chandrakasan, and B.Nikolic, Digital integrated circuit: A Design Perspective (2nd edition). Englewood Cliffs, NJ: Prentice hall. E. Grossar, M. Stucchi, K. Maex and W. Dehaene, "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies," IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006. H. Makino, et al., ―Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration." Circuits and Systems 3, 2012. C. B. Kushwah and S. K. Vishvakarma, "A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 373-377, Jan. 2016. P. S. Grace and N. M. Sivamangai, "Design of 10T SRAM cell for high SNM and low power," 3rd International Conference on Devices, Circuits and Systems (ICDCS), pp. 281-285, Coimbatore, 2016. J. K. Mishra, et al.,-Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications. "Journal of Circuits, Systems and Computers", Vol. 30, No. 15, 2150270 (2021). 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-3992933","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":275520777,"identity":"85af439a-e72a-48c0-bf4c-78a0e9340f3f","order_by":0,"name":"Ram Murti Rawat","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA4ElEQVRIiWNgGAWjYBADHghVwQzlGxDUYQDRcuAMswTRWiDUwTaYFjzAvP106mbePX9kzNvPGH7+OM+6zuAA88MPDAV3cGqROZO77TbPMwMemTM5xhIHt6VLGBxgM5ZgMHiGU4sEA0jLAQMeIGMDUMthoBYGM6BLD+PWwv8WqoX/7eYfB+eAtLB/w69FAmYLkCFxsAGkhYeALRJvt92cc8AYqOX9N4szx9IlZx7mKZZIwOuw3G033hyQs5fgT0u+UVFjzc93vH3jhw9/cGvBAkAJIIEUDaNgFIyCUTAKMAAALAtSTS8bhRsAAAAASUVORK5CYII=","orcid":"","institution":"Delhi Technological University","correspondingAuthor":true,"submittingAuthor":false,"prefix":"","firstName":"Ram","middleName":"Murti","lastName":"Rawat","suffix":""},{"id":275520778,"identity":"f0a65044-3b39-4102-81fb-58cd378406d2","order_by":1,"name":"Vinod Kumar","email":"","orcid":"","institution":"Delhi Technological University","correspondingAuthor":false,"submittingAuthor":false,"prefix":"","firstName":"Vinod","middleName":"","lastName":"Kumar","suffix":""}],"badges":[],"createdAt":"2024-02-27 05:29:48","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-3992933/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-3992933/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":51833304,"identity":"26dc86ef-56e0-4ba4-a6f2-95df3811d6c0","added_by":"auto","created_at":"2024-02-29 19:27:24","extension":"jpg","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":73106,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 2.1 Conventional 6T SRAM cell\u003c/p\u003e","description":"","filename":"21.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/5a07458b834cd3e7bfa908d6.jpg"},{"id":51833303,"identity":"a1f5421a-b2a3-46c4-bbe8-a4cd02b9595f","added_by":"auto","created_at":"2024-02-29 19:27:24","extension":"jpg","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":116072,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 3.1 (a) Circuit of negative bit line generator [27], and (b) (b) Output voltage at node X [27].\u003c/p\u003e","description":"","filename":"31.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/a02116669344198656220ebb.jpg"},{"id":51833309,"identity":"8a89ca91-d597-4ae2-84db-de0ab89e831a","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":117859,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 3.2 Proposed Design\u003c/p\u003e","description":"","filename":"32.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/827d1f961e90a3f268410015.jpg"},{"id":51833313,"identity":"b5543dd6-9cdf-4ebe-b4db-aefdc15702db","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":212890,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 3.3 Proposed design during (a) write operation, and (b) read operation.\u003c/p\u003e","description":"","filename":"33.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/57773c8b9c7c0a5c4f89d2b2.jpg"},{"id":51833305,"identity":"500bf1ea-9c25-4932-b4cf-449857746ac3","added_by":"auto","created_at":"2024-02-29 19:27:24","extension":"jpg","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":66537,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.1 Butterfly curve for write stability\u003c/p\u003e","description":"","filename":"41.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/745760516a3a6d7e453a8642.jpg"},{"id":51833307,"identity":"a62eb4b6-e7bd-4739-ab3b-6083a63f8593","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":99211,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.2. Variation in WSNM vs supply voltage\u003c/p\u003e","description":"","filename":"42.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/390f421b0a3afcf28ecc626e.jpg"},{"id":51833312,"identity":"d7d88703-8830-4659-a293-32c6f7217a05","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":107765,"visible":true,"origin":"","legend":"\u003cp\u003eFig.4.3. Variation of WSNM vs temperature\u003c/p\u003e","description":"","filename":"43.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/15c7585fa83e68ea0acb9360.jpg"},{"id":51833317,"identity":"bd558b13-2f3f-4e5b-a129-486d90f8d6b1","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":125914,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.4 Monte Carlo of WSNM for proposed design\u003c/p\u003e","description":"","filename":"44.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/3fc2ace83ca1ae68581efe81.jpg"},{"id":51833315,"identity":"63e0b0b1-fdc7-437a-baf7-d9027a32ce6f","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":65060,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.5. Butterfly curve for the read stability\u003c/p\u003e","description":"","filename":"45.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/9f848a79231297da6a147859.jpg"},{"id":51833589,"identity":"bd165015-503b-4dfc-a2f6-49d891702c2b","added_by":"auto","created_at":"2024-02-29 19:35:25","extension":"jpg","order_by":10,"title":"Figure 10","display":"","copyAsset":false,"role":"figure","size":113849,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.6. RSNM vs supply voltage\u003c/p\u003e","description":"","filename":"46.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/7e1b41061730abf49a7b473a.jpg"},{"id":51833587,"identity":"76c547a7-17ed-46a7-9d9a-8ee400ae5419","added_by":"auto","created_at":"2024-02-29 19:35:25","extension":"jpg","order_by":11,"title":"Figure 11","display":"","copyAsset":false,"role":"figure","size":107724,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.7. Variation of RSNM vs temperature\u003c/p\u003e","description":"","filename":"47.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/a9a1f69fab8ada546e5a9ee7.jpg"},{"id":51833318,"identity":"22cf0699-9bc1-40b7-9d0e-fbc7ee25908a","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":12,"title":"Figure 12","display":"","copyAsset":false,"role":"figure","size":67283,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.8. HSNM of proposed design\u003c/p\u003e","description":"","filename":"48.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/16a4b9fc2e4a172b06fd560d.jpg"},{"id":51833588,"identity":"8e1ffc82-8624-4e04-aef7-c9ee4aa38b98","added_by":"auto","created_at":"2024-02-29 19:35:25","extension":"jpg","order_by":13,"title":"Figure 13","display":"","copyAsset":false,"role":"figure","size":116821,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.9. Variation of HSNM vs supply voltage\u003c/p\u003e","description":"","filename":"49.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/a9f1d6f7e3c3e7a254a2ffd2.jpg"},{"id":51833320,"identity":"2c79b457-a42d-4a82-9f11-673a68af21cc","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":14,"title":"Figure 14","display":"","copyAsset":false,"role":"figure","size":105234,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.10. Variation of HSNM vs temperature\u003c/p\u003e","description":"","filename":"410.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/e66614c51f0eb72ae56dacb4.jpg"},{"id":51833321,"identity":"a1f7f38b-a528-4b05-bbfd-cef173e0eeb6","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":15,"title":"Figure 15","display":"","copyAsset":false,"role":"figure","size":129573,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.11. Static power dissipation at various VDD\u003c/p\u003e","description":"","filename":"411.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/ce969bbb32a9da2d71bf8772.jpg"},{"id":51833590,"identity":"6f6233b7-a00d-4b30-898d-14fc98a76d64","added_by":"auto","created_at":"2024-02-29 19:35:25","extension":"jpg","order_by":16,"title":"Figure 16","display":"","copyAsset":false,"role":"figure","size":132293,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.12. Variation of static power dissipation vs temperature\u003c/p\u003e","description":"","filename":"412.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/2b6e0d8abea58cc04e74f39d.jpg"},{"id":51833316,"identity":"b3de04d3-9008-43f4-b1d8-0147dd3440e0","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":17,"title":"Figure 17","display":"","copyAsset":false,"role":"figure","size":121884,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.13. Variation of write delay vs supply voltage\u003c/p\u003e","description":"","filename":"413.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/c1a43c281baed5c0f2650701.jpg"},{"id":51833308,"identity":"2b5b35ca-99a6-45df-91ac-5d1b622bf44b","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":18,"title":"Figure 18","display":"","copyAsset":false,"role":"figure","size":105188,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.14. Monte Carlo of write delay for proposed design\u003c/p\u003e","description":"","filename":"414.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/03f72dbb198f5113bcc29caf.jpg"},{"id":51833322,"identity":"a32cdca0-c7ee-4db3-a2c1-18d01cdb3490","added_by":"auto","created_at":"2024-02-29 19:27:25","extension":"jpg","order_by":19,"title":"Figure 19","display":"","copyAsset":false,"role":"figure","size":105242,"visible":true,"origin":"","legend":"\u003cp\u003eFig. 4.15. Variation of read delay vs supply voltage\u003c/p\u003e","description":"","filename":"415.jpg","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/ce8f5e199a862afe48ff7620.jpg"},{"id":75975512,"identity":"6a3dafa8-3227-4fa4-b1b4-e225ad05b6ab","added_by":"auto","created_at":"2025-02-11 06:32:27","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2802613,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-3992933/v1/a3e4032d-2a17-43b6-aece-6653eb80a956.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eMore than five decades have passed since the scaling of semiconductor process technology began. The catalyst that has been propelling the semiconductor industry is the advancements in process technology. The semiconductor industry introduces a new process technology every two to three years, in response to growing customer demand for enhanced performance and functionality at reduced cost [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e]. All electrical systems, including mainframes, microcomputers, mobile phones, and other devices, heavily rely on memory. Energy-efficient CPUs are becoming essential due to the rising demand for portable battery-operated systems. The dimensions, weight, and battery life of these gadgets have an impact on their performance. The IC design community has been actively seeking out new approaches and methodologies that result in more power-efficient designs, which means significant reductions in power consumption for the same level of performance, as a result of serious reliability issues, rising design costs, and battery-operated applications. Every system design includes memory circuits, which greatly increase system-level power consumption as Dynamic RAMs, Static RAMs, Ferroelectric RAMs, ROMs, or Flash Memories have significant power consumption. System performance, reliability, and costs may all be considerably increased by reducing the power dissipation of memory. Due to the rise in popularity of notebooks, laptops, hand-held communication devices, and IC memory cards in recent years, RAMs have developed extremely quickly in terms of low-power, low-voltage memory architecture. To decrease power dissipation, a number of strategies are used, including power gating, the sleepy technique, and the design of circuits with power supply (VDD) scaling. A lower VDD voltage quadratically and exponentially lowers dynamic power and leakage power, respectively. However, scaling of the VDD reduces the noise margin. A lot of SRAM arrays are built around lowering the swing voltage and active capacitance. Gate leakage and sub threshold leakage current are the major causes of leakage currents in the sub-100 nm area. Technology with high dielectric constant gates reduces gate leakage current. To lessen sub threshold leakage current, dual Vt approaches and forward body biassing are employed. The operational current in sub threshold SRAMs is the sub threshold leakage current since the VDD is lower than the transistor threshold voltage (Vt) [\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e]. Computer data storage, often called storage or memory, refers to computer components and recording media that retain digital data used for computing for some interval of time. The main purpose of storage is that without a significant amount of memory, a computer would merely be able to perform fixed operations and immediately output the result [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e]. There are two types of memories: volatile and non-volatile. In the storage array or core, the straightforward cell circuits are stacked in horizontal rows and columns to share connections. Word-lines are the horizontal lines that are exclusively driven from the external storage array, while bit-lines are the vertical lines that carry data into and out of the cells. For reading or writing, access is made to the row and column that have been specifically chosen in a cell. Either \"0\" or \"1\" can be stored in each cell. Read-Write Random-Access Memory (RW RAM) refers to the storage of data in flip-flop circuits or simply as charge on capacitors (RAM). Because the data is volatile, there is about an equivalent delay while reading or writing it. Read-Write memories store data in an active circuit, meaning that if the power source is stopped, the recorded data will be lost. Since Read-Write Random-Access Memory is frequently referred to as RAM, RWM is the obvious shorthand for this type of memory. This research proposes a novel SRAM cell with differential write and single-ended read capabilities for IoT applications. For enhanced stability and rail to rail voltage swing, the transmission gate is employed as an access transistor. The suggested SRAM cell's analysis of leakage power and stability for VDD ranging from 0.9V to 0.5V is contrasted with that of the current 5T and 6T SRAM bit cells at 32nm technology. The transistor stacking effect is employed to reduce the SRAM cell's leakage current. By separating the read line from the node that is responsible for the read disturbance problem, stability is increased[\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. This article explains the low-power 8T SRAM cell memory cell suggested design. In the suggested method, two PMOS transistors are used, one of which is linked to the node voltage Q and the other to the Qbar. the bit and bit bar lines' swing voltage must be eliminated. The swing voltage is reduced when the cell is operating, which lowers the dynamic power dissipation. A sequence of leakage current decreases occurs when the transistors go from being inactive to being active and vice versa thanks to the precharge voltage level approach, which uses an NMOS transistor as a resister and a PMOS transistor as a switchThe comparison's results demonstrate that the proposed 8T SRAM cell's read, write, and hold mode operation is superior to that of the 6T SRAM cell. This occurs regularly as a result of the increased static noise margins produced, which guarantee good bit cell write ability [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e].\u003c/p\u003e"},{"header":"2. Related Work","content":"\u003cp\u003eSeveral schemes have been proposed about the improved stability as well as energy efficient for SRAMs in present-day low power analysis. Following is a discussion about the work done in improved stability and energy efficient SRAMs. Since the speed of early days electronic system was very slow, because the speed of memory was not comparable to the processor speed. Hence the cache memory is used for enhancing the speed of overall system. Currently, On static random access memory, the cache memory is built. SRAM cell count on a single chip for a domain-specific architecture ‖ (DSA) is reaching to hundreds of megabits. This is resulted in two crucial challenges. The first challenge is the increasing inefficiency in SRAM array size with the newest CMOS technologies while the second challenge is the static power dissipation due to various leakage current which flows from the higher VDD through the SRAM cell to the lower VDD [\u003cspan class=\"CitationRef\"\u003e6\u003c/span\u003e]. This necessitates the need to design SRAM with minimal leakage since this reduces static power dissipation significantly. One of the suggested solutions to the power dissipation problem is to scale back the VDD, but the reliability of the SRAM cell poses another challenge in this. Besides this, issues like data stability, delay and high sensitivity to process variation [\u003cspan class=\"CitationRef\"\u003e7\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e12\u003c/span\u003e] also contributes to overall performance of SRAM.\u003c/p\u003e\n\u003cp\u003eFigure 2.1 depicts the conventional 6T SRAM cell consisting of four NMOS (NM\u003csub\u003e4\u003c/sub\u003e, NM\u003csub\u003e5\u003c/sub\u003e, NM\u003csub\u003e6\u003c/sub\u003e and NM\u003csub\u003e7\u003c/sub\u003e) and two PMOS (PM\u003csub\u003e3\u003c/sub\u003e and PM\u003csub\u003e4\u003c/sub\u003e) transistors. At scaled cell VDD, the 6T SRAM cell encounters several issues like stability, delay, high sensitivity to process variation etc. [\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e]. The SRAM cell stability is mainly affected by the strength of transistors which form internal latch and access transistors. Hence, the weak pull-up transistor of the internal latch and strong access transistor are required for maintaining the write ability, while a strong pull-down transistor of the internal latch and weak access transistor is required for read stability [\u003cspan class=\"CitationRef\"\u003e10\u003c/span\u003e]. During the write operation in the SRAM cell, the conventional 6T SRAM cell provides a poor write ability due to disturbance in the node voltage at the down scaled cell VDD [\u003cspan class=\"CitationRef\"\u003e13\u003c/span\u003e]. Several write assist techniques are known in the literature currently in use to improve the write capabilities of SRAM cells. Among them the popular ones are negative bit line, V\u003csub\u003eDD\u003c/sub\u003e collapse, boosted V\u003csub\u003eSS\u003c/sub\u003e, word-line boosting etc. [\u003cspan class=\"CitationRef\"\u003e14\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e]. The negative bit-line write assist circuit technique has been proposed by Y. H. Chen, et al. [\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e]. When the bit lines of SRAM cells are used with a negative voltage rather than with ground, the gate to source voltage (VGS) of the access transistors is increased as a result. Therefore, increasing the voltage increases the SRAM cell\u0026apos;s access transistors\u0026apos; driving capacity without affecting the inside latch. However, in this technique, the bit-line capacitance has been increased by boosted capacitor which eventually increases the access time [\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e]. On the contrary, in V\u003csub\u003eDD\u003c/sub\u003e collapse technique, proposed by E. Karl, et al. [\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e], the weakening of the internal latch during a write operation is performed for improving the write ability, but the reduction in cell VDD in the technique disturbs the stored node voltage, thereby resulting in data loss during read or hold operation. In boosted word-line write assist technique [\u003cspan class=\"CitationRef\"\u003e18\u003c/span\u003e], the word-line voltage is increased which also increases the gate to source voltage of access transistors, thereby increasing the static power dissipation. As a result, this method is likewise not appropriate for low voltage operation. In addition to this, attempts were also made by B. Wang, et al. [\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e] proposing ultra-low voltage 9T SRAM cell (9T UV SRAM), M. H. Tu, et al. [\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e], A. Banerjee, S. Kamineni and B. H. Calhoun [\u003cspan class=\"CitationRef\"\u003e21\u003c/span\u003e] etc. to reduce the static power dissipation and for improvement of read/write operation. However, the results obtained are not promising.\u003c/p\u003e\n\u003col\u003e\n \u003cli\u003e\n \u003cp\u003eTo address stability and delay difficulties in SRAM, an unique negative bit-line (NBL) circuit is proposed then put into action using an 8T SRAM cell.\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003eIn the recommended architecture, one of the bit lines produces a negative voltage during the write operation (due to the NBL circuit), which enhances the access transistors\u0026apos; driving capacity and, as a result, the writing ability.\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003eTo increase the cell\u0026apos;s stability during read operation, a separate or isolated read port is employed.\u003c/p\u003e\n \u003c/li\u003e\n \u003cli\u003e\n \u003cp\u003eAs a consequence, the suggested improvement has improved cell stability and decreased its latency.\u003c/p\u003e\n \u003c/li\u003e\n\u003c/ol\u003e"},{"header":"3. Proposed Work","content":"\u003cp\u003eThe following is a description of the proposed work..\u003c/p\u003e\n\u003cdiv id=\"Sec3\" class=\"Section2\"\u003e\n\u003ch2\u003e3.1 Negative Bit-line generator circuit (NBL)\u003c/h2\u003e\n\u003cp\u003eApplying a negative voltage to one of the bit lines (BL or BLB) of the SRAM cell decreases the gate to source voltage (VGS) of the access transistor in the proposed circuit. The major function of the NBL circuit is to deliver a negative voltage instead of 0V at the BL/BLB of an SRAM cell, depending on the operating conditions. The suggested NBL generator circuit is depicted in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.1\u003c/span\u003e(a) and is constructed utilising four NMOS, three PMOS, and two NOR gates. The NOR gate's inputs in the NBL circuit are the Din, Dinb, and WR signals, while the NOR gate's output is connected to the inputs of the NMOS and PMOS transistors [\u003cspan class=\"CitationRef\"\u003e27\u003c/span\u003e].\u003c/p\u003e\n\u003cp\u003eThe NBL circuit performs the following operations:\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCase 1\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eNBL circuit in write mode when logic \"1\" is used.\u003c/p\u003e\n\u003cp\u003eWhile applying logic levels \"1\" and \"0,\" respectively, to the Din and Dinb signals, logic level \"0\" is applied to WR in a write logic \"1\" operation. Inverted Din and Dinb signals are always the NOR gate's output signals. As a result, NOR1 and NOR2 output \"0\" and \"1,\" respectively. Transistor NM1 would turn to an OFF state, and NM2 would go into an ON state. Transistor PM1 would also be ON and PM2 would be OFF in addition to this. As a result, the bit-line (BL) would change to logic high (VDD), and the bit-line bar's (BLB) state would rely on two additional scenarios related to the status of the WE and WEN signals.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCase A\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe WEN signal's counterpart logic \"1\" is applied when the WE signal is at logic \"0\" (as shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.1\u003c/span\u003e(b))[\u003cspan class=\"CitationRef\"\u003e27\u003c/span\u003e]. As a result, the transistor NM0 is turned off by the WE signal, and the transistor PM0 is turned on, which then turns on the transistor NM3. The triode region in which the ON transistor NM3 works provides a resistance across it. The RC network is made up of a capacitor (C) and the transistor NM3 (RON) resistance (the circuit works as a RC differentiator). Because the WEN signal (at the starting point) is a rising pulse and the slope at the positive edge is particularly large, the capacitor acts as a short circuit, the input voltage (the voltage of the WEN signal) and the voltage at node X (the voltage across the RON or VX) are equal at this point. When the WEN signal reaches logic \"1\" after the positive edge, the capacitor starts to charge through resistance RON. As a result, until the capacitor is fully charged, the voltage at node X or VX quickly decreases (as shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.1\u003c/span\u003e(b)) (charging of capacitor depends on time constant RONC). As a result, in this circumstance, the voltage at BLB and VX are equal.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCase B\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe WEN signal's counterpart, logic \"0,\" is applied when the WE signal is at logic \"1.\" As a result, the transistor PM0 is turned off by the WE signal, while the transistor NM0 and NM3 are turned on (because capacitor does not allow the sudden change in voltage thus the gate of NM3 is connected to node X through NM0 transistor). An RC network is created in a manner similar to scenario A. The negative edge of the WEN signal has a very steep slope, and since the WEN signal is a falling pulse, the capacitor does not react well to steep slopes. As a result, a negative spike develops at this point. The capacitor discharges when the WEN signal reaches logic \"0\" following a negative edge. As the capacitor drains, the voltage at node X or VX increases exponentially (as seen in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.1\u003c/span\u003e(b)) (discharging of capacitor also depends on time constant RONC). As a result, in this instance, the voltage at BLB is also equal to the negative voltage, or VX voltage.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCase II\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWhen writing logic \"0,\" the NBL circuit. The Din and Dinb signals are respectively, at logic levels \"0\" and \"1,\" the logic \"0\" is applied to WR in order to perform a write logic \"0\" operation. The output signals of the NOR1 and NOR2 gates are, respectively, at logic \"1\" and \"0.\" Transistor NM1 would go to the ON state, whereas NM2 would go into the OFF state. Additionally, transistors PM1 and PM2 would be ON and OFF respectively. As a result, the bit-line bar (BLB) would change to logic high (VDD), and the bit-line (BL) state would likewise rely on the WE and WEN signal states for the additional two instances A and B (as mentioned for scenario I). As a result, when WEN is set to logic \"0,\" the bit-line (BL) receives a negative voltage.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCase III\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe NOR gate would always produce a zero output during a read and hold operation, which would then activate the PMOS (PM1 and PM2) and deactivate the NMOS (NM1 and NM2) transistors. The WR signal is always at logic \"1\" during a read and hold operation, hence the NOR gate would always output zero regardless of Din and Dinb values. The PMOS (PM1 and PM2) transistors are used to link the BL or BLB and VDD. The aforementioned Cases A and B have no impact on the read and hold operation since the NMOS (NM1 and NM2) transistors are in the OFF state and the node X disconnects from the bit-lines (BL/BLB). Since the bit-lines (BL/BLB) are switched to VDD during read and hold operations, the proposed NBL circuit provides a negative voltage at one of the bit-lines (BL/BLB) during the write operation [\u003cspan class=\"CitationRef\"\u003e22\u003c/span\u003e].\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec4\" class=\"Section2\"\u003e\n\u003ch2\u003e3.2 Proposed design (NBL circuit with 8T SRAM cell)\u003c/h2\u003e\n\u003cp\u003eThe suggested design (PD), which implements an NBL circuit with an 8T SRAM cell, is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.2\u003c/span\u003e. There are eight transistors in an 8T SRAM cell. The SRAM's internal latch, where the data is kept, is built using the transistors NM4, NM5, PM3, and PM4. The separate read port for accessing data from the SRAM cell is formed by transistors NM8 and NM9. The data-storing nodes of an SRAM cell are node Q and node Qb. While transistor NM9 functions as an access transistor during read operation and is triggered by the read word line (RWL) signal, transistors NM6 and NM7 function as write access transistors. The read bit line (RBL) functions as an input/output line under read operation, whereas the bit lines (BL/BLB) function as an input for write operation.\u003c/p\u003e\n\u003cp\u003eThe following is a discussion of the different operations of the proposed design:\u003c/p\u003e\n\u003cdiv id=\"Sec5\" class=\"Section3\"\u003e\n\u003ch2\u003e3.2.1 Write Operation\u003c/h2\u003e\n\u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e3.3\u003c/span\u003e shows the circuit's behaviour during write operations. (In this instance, a dotted line represents an OFF transistor.) The WWL signal is given the write operation logic \"1,\" which activates the access transistors NM6 and NM7. Write logic \"1\" for at node Q. The nodes Qb and Q, respectively, are initially where logic \"1\" and \"0\" are stored.\u003c/p\u003e\n\u003c/div\u003e\n\u003c/div\u003e\n\u003cp\u003e1. At the nodes Qb and Q, respectively, logic \"1\" and \"0\" are initially stored.\u003c/p\u003e\n\u003cp\u003e2. BL and BLB are given the logic values \"1\" and \"0,\" respectively.\u003c/p\u003e\n\u003cp\u003eIn the suggested architecture, the NBL circuit is linked to the bit-lines. The WR signal is at logic \"0\" for write operation in the NBL circuit, whereas the Din and Dinb signals are at logic \"1\" and \"0,\" respectively. As a result, the BLB is driven at negative potential while the BL is driven at VDD (as discussed in section 3.1).\u003c/p\u003e\n\u003cp\u003eThe negative voltage at the BLB causes the gate to source voltage (VGS) of the access transistor (NM7) to rise, which in turn raises NM7's driving capacity. Due to node Qb being forced to discharge quickly and acquire 0V as a result of transistor NM7 acting much faster than transistor NM6 in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.3\u003c/span\u003e (a), transistor PM3 is turned ON and transistor NM4 is turned OFF. Thus, transistor PM3 connects the storing node Q to the VDD, whereupon the logic \"1\" is afterwards stored.\u003c/p\u003e\n\u003cdiv id=\"Sec8\" class=\"Section2\"\u003e\n\u003ch2\u003e3.2.2 Read Operation\u003c/h2\u003e\n\u003cp\u003eFigure 3.4 shows the circuit behaviour of the proposed design (with the OFF transistor shown by the dotted line) during a read operation. The output of the NOR gate would always be at a low voltage, activating the PMOS, because the WR must always be at logic \"1\" in order to read data from the SRAM cell. As a result, the bit lines (BL or BLB) have always been set to logic \"1\". During a read operation, RBL is pre-charged at logic \"1,\" the WWL signal is at logic \"0,\" RWL is at logic \"1,\" and so on. Assume initially that nodes Q and Qb are where logic level \"0\" and \"1\" are kept for read logic \"0\" operations. The transistor NM8 turns ON owing to logic \"1\" stored at node Qb, which is coupled to the transistor NM8's gate (as illustrated in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e3.3\u003c/span\u003e (b)). With the help of transistors NM8, and NM9, a route (depicted by an arrow) is created between RBL and ground. Thus, as seen in Fig.\u0026nbsp;3.4, the RBL is discharged to 0 V. The read logic \"0\" operation has therefore been carried out.\u003c/p\u003e\n\u003cdiv id=\"Sec9\" class=\"Section3\"\u003e\n\u003ch2\u003e3.2.3 Hold operation\u003c/h2\u003e\n\u003cp\u003eThe access transistors NM6, NM7, and NM9 are turned off as a result of the RWL and WWL being maintained at logic \"0\" during the hold operation. The BL, BLB, and RBL are constantly at logic \"1\" because the WR in the NBL circuit is always at logic \"1.\" The internal latch of the SRAM cell is disconnected from the bit-lines in hold mode of operation, preserving the data stored inside. A large amount of static power was also lost by the SRAM cell during the hold mode due to leakage current, mostly sub-threshold leakage current because the bulk of the transistors are still in the OFF state. Consequently, the suggested design reduces static power dissipation. The NM9 transistor Y node generates a positive voltage as a result of self-reverse biassing. This positive voltage lowers the drain to source (VDS) and gate to source (VGS) voltages of OFF transistors (NM5 and NM9) while raising their threshold voltages (NM5 and NM9).\u003c/p\u003e\n\u003c/div\u003e\n\u003c/div\u003e"},{"header":"4. Results and Discussion","content":"\u003cp\u003eThe performance of the given design has been predicted using the cadence virtuoso tool for circuit design and simulation utilising the UMC 28 nm CMOS technology node. The following are the simulated findings for the proposed design's different performance parameters:\u003c/p\u003e\n\u003cdiv id=\"Sec11\" class=\"Section2\"\u003e\n\u003ch2\u003e4.1 Write ability\u003c/h2\u003e\n\u003cp\u003eThe stability of the SRAM cell is defined as the greatest noise voltage that cannot flip the state of the storing node in the SRAM cell. Write static noise margin (WSNM), which is acquired via a sweeping approach, serves to define the SRAM's write capability. This technique sweeps the voltage at one node (Q) from zero to the VDD, then plots it against the analogous voltage at another node (Qb) to get the voltage transfer characteristic curve (VTC). The process is then repeated, but this time to generate a comparable graph to the analogical VTC at node Q, the voltage at node Qb is swept from 0V to the maximum VDD. Last but not least, the two VTC curves are blended into a graphic called a butterfly plot. The butterfly plot, in which a square is produced and the longest vertical side is taken into account as the WSNM value, determines the WSNM [\u003cspan class=\"CitationRef\"\u003e23\u003c/span\u003e\u0026ndash;\u003cspan class=\"CitationRef\"\u003e24\u003c/span\u003e]. Figure\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.1\u003c/span\u003e illustrates the butterfly curve of the suggested design for calculating the write-operational WSNM value at 1V cell VDD and 27\u0026deg;C temperature with TT corner. When compared to an 8T SRAM cell without an NBL circuit, the suggested design's WSNM is 490 mV. Since the 8T SRAM cell with the NBL circuit improves the WSNM value by 1.53x over the SRAM cell without the NBL circuit, it is preferable to have this feature included.\u003c/p\u003e\n\u003cp\u003eFigure\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.2\u003c/span\u003e shows the comparison of the proposed design with the standard 6T SRAM cell, the VDD collapse write assist approach, the NBL write help technique, and the 9T UV SRAM cell at various cell VDDs. Because there is a significant likelihood of flipping the data of SRAM cells at lower VDDs, it has been shown that WSNM rises with VDD. As a result, the cell is less stable at lower VDDs than it is at higher VDDs. Additionally, when developed at 1V using the same technology node, the WSNM of the suggested design is improved by 48%, 11%, 19%, and 32.4% over basic 6T SRAM cell [\u003cspan class=\"CitationRef\"\u003e11\u003c/span\u003e], NBL [\u003cspan class=\"CitationRef\"\u003e16\u003c/span\u003e], VDD collapse [\u003cspan class=\"CitationRef\"\u003e17\u003c/span\u003e], and 9T UV SRAM [\u003cspan class=\"CitationRef\"\u003e19\u003c/span\u003e], respectively. This increase was made possible by a negative bit-increased line's ability to boost the access transistor's VGS. The WSNM of the suggested design is shown in Fig.\u0026nbsp;4.3 at various temperatures. When the temperature rises from \u0026minus;\u0026thinsp;40\u0026deg;C to 120\u0026deg;C at 1V, it can be shown that the WSNM value of the suggested design falls from 580 mV to 430 mV. This is due to the threshold voltage decreasing with temperature.\u003c/p\u003e\n\u003cp\u003eAs a result, the SRAM cell's data values deteriorate. So, at high temperatures, the SRAM cell is less stable. Comparing the suggested design to the basic 6T and other current designs, as shown in Fig.\u0026nbsp;4.3, the proposed design exhibits nominal performance in terms of WSNM even with the increase in temperature. The yield of the suggested design has been determined and validated using a Monte Carlo simulation for process variation and mismatch. For transistor parameters that are normally distributed and uncorrelated, the Monte Carlo simulation approach replaces the fixed Gaussian distribution with a random value. The simulation result for WSNM demonstrates that the proposed design is lesser sensitive to mismatching and process variations as standard deviation (\u0026sigma;) is only 0.09V (as depicted in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.4\u003c/span\u003e) when 200 number of samples have been considered for the analysis. The mean value (\u0026micro;) of proposed design is 490 mV whereas the variability (\u0026sigma;/\u0026micro;) is 0.18.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec12\" class=\"Section2\"\u003e\n\u003ch2\u003e4.2 Read Stability\u003c/h2\u003e\n\u003cp\u003eThe read stability of the SRAM cell is defined through the read static noise margin (RSNM), which is also obtained using the butterfly plot [\u003cspan class=\"CitationRef\"\u003e25\u003c/span\u003e]. The butterfly curve for the read stability in the read operation is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.5\u003c/span\u003e. The greatest side length of the square produced inside the smaller lobe of the butterfly curve is used to evaluate the proposed design's RSNM value. It should be noted that the suggested design's RSNM value is 400 mV at 1V for the cell. The fluctuation in RSNM values for the proposed design and prior published studies at various cell VDDs are shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.6\u003c/span\u003e. The RSNM is very low at the lower VDD, and as the voltage rises, the RSNM likewise rises. It can be noticed that there is an enhancement in RSNM of proposed design by 81%, 42%, 29%, over basic 6T SRAM cell\u003csup\u003e[11]\u003c/sup\u003e, NBL\u003csup\u003e[16]\u003c/sup\u003e, V\u003csub\u003eDD\u003c/sub\u003e collapse\u003csup\u003e[17]\u003c/sup\u003e respectively, whereas decrement by 4.8% over 9T UV SRAM\u003csup\u003e[19]\u003c/sup\u003e when designed at 1V using same technology node.\u003c/p\u003e\n\u003cp\u003eIn the suggested architecture, a dedicated or isolated read port is used to accomplish this increase in RSNM. The WWL signal is at logic \"0\" during the read operation, isolating the storage nodes from the bit-lines (BL/BLB). As a result, there has been no disruption or degradation of the data held in nodes (Q/Qb). As a result, the suggested design is quite stable when being read. The RSNM value of the suggested design is shown in Fig.\u0026nbsp;4.7 at various temperatures. Due to the lower threshold voltage of transistors when temperature rises, the suggested design's RSNM value lowers. Additionally, Fig.\u0026nbsp;4.7 compares the suggested architecture to different SRAM designs. It is clear that the suggested design delivers the best results for read operation at a specific temperature.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec13\" class=\"Section2\"\u003e\n\u003ch2\u003e4.3 Hold Stability\u003c/h2\u003e\n\u003cp\u003eHold static noise margin is used to measure the SRAM cell's stability in hold mode (HSNM). This is possible using the butterfly plot, as seen in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.8\u003c/span\u003e. It has also been highlighted that the HSNM value of the proposed design is 350 mV at 1V for the cell. At various cell VDDs, Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.9\u003c/span\u003e compares the HSNM value of the proposed design to that of other current designs. In the hold mode of the proposed architecture, the internal latch is isolated from the bit-lines. As a result, there is no data loss and the SRAM cell is more stable in hold mode. Also, it can be noticed that there is an enhancement in HSNM of proposed design by 28%, 13%, 40%, and 8.5% over basic 6T SRAM cell \u003csup\u003e[11]\u003c/sup\u003e, NBL \u003csup\u003e[16]\u003c/sup\u003e, V\u003csub\u003eDD\u003c/sub\u003e collapse \u003csup\u003e[17]\u003c/sup\u003e and 9T UV SRAM \u003csup\u003e[19]\u003c/sup\u003e respectively when designed at 1V using similar technology node.\u003c/p\u003e\n\u003cp\u003eThe HSNM of the suggested design is shown in Fig.\u0026nbsp;4.10 at various temperatures. It has been noted that the HSNM value of the suggested design, when operating at 1V cell, reduces when temperature increases from \u0026minus;\u0026thinsp;40\u0026deg;C to 120\u0026deg;C. Additionally, a comparison of the suggested architecture with a standard 6T SRAM cell and other cutting-edge work is shown. This may be used to show that the proposed design's HSNM performs better than alternative designs at different temperatures.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec14\" class=\"Section2\"\u003e\n\u003ch2\u003e4.4 Static Power Dissipation\u003c/h2\u003e\n\u003cp\u003eAt lower technology node SRAM cell also faces the issue of static power dissipation. The numerous leakage currents in a circuit are the major cause of static power dissipation. The leakage current includes sub-threshold leakage current, junction leakage current, gate leakage current, and so on [\u003cspan class=\"CitationRef\"\u003e26\u003c/span\u003e]. Figure\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.11\u003c/span\u003e displays the dynamic power dissipation of the proposed architecture at different VDDs. The static power dissipates more when the cell VDD is increased. The recommended design's static power dissipation is 430 pW at a cell VDD of 1 V. (190 pW by an 8T SRAM cell and 240 pW by an NBL circuit). The suggested design has been compared to other state-of-the-art work as well as a simple 6T SRAM cell. This can be noticed that the proposed design consumes 30%, 11% and 20% more power than 6T SRAM cell\u003csup\u003e[11]\u003c/sup\u003e, V\u003csub\u003eDD\u003c/sub\u003e collapse\u003csup\u003e[17]\u003c/sup\u003e and 9T UV SRAM\u003csup\u003e[19]\u003c/sup\u003e respectively while 17% less than NBL\u003csup\u003e[16]\u003c/sup\u003e, at 1V. Due to the NBL circuit's usage of just one SRAM cell, the suggested design has a little higher static power dissipation than usual. However, by combining a single NBL circuit to several SRAM cells, static power can be reduced. The fluctuation in static power dissipation at various temperatures is seen in Fig.\u0026nbsp;4.12. Because the sub-threshold leakage current exponentially relies on the temperature and threshold voltage, the suggested device loses power as the temperature rises. As the temperature rises, the threshold voltage falls, increasing the sub-threshold leakage current. As a result, the suggested design loses more static power.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec15\" class=\"Section2\"\u003e\n\u003ch2\u003e4.5 Write Delay\u003c/h2\u003e\n\u003cp\u003eThe amount of time needed to write data at storage nodes (Q/Qb) is computed as the time interval starting when the WWL signal reaches 50% of its highest value during the write operation. At a 1V cell VDD, the suggested design's write latency is 140 ps. The write delay of the suggested design at various VDDs is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.13\u003c/span\u003e, along with a comparison to other existing SRAM. This can be detected that the write delay of proposed design is reduced by 33%, 39%, 48%, and 22% when compared to 6T SRAM cell\u003csup\u003e[11]\u003c/sup\u003e, NBL\u003csup\u003e[16]\u003c/sup\u003e, V\u003csub\u003eDD\u003c/sub\u003e collapse\u003csup\u003e[17]\u003c/sup\u003e and 9T UV SRAM\u003csup\u003e[19]\u003c/sup\u003e respectively at 1V.\u003c/p\u003e\n\u003cp\u003eSince the source of the access transistor is at a negative voltage during a write operation, the write latency is reduced thanks to the high driving capabilities of the access transistor. The cross coupled inverter state is flipped as a result of the node storing logic \"1\" discharging relatively quickly, making it simple to send data to the storage nodes. Additionally, a Monte Carlo study of the suggested design's write latency was completed and is shown in Fig.\u0026nbsp;4.14. For 200 samples, the standard deviation and mean write delay values are 32.2 and 140 ps, respectively, with a variability of 0.26.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec16\" class=\"Section2\"\u003e\n\u003ch2\u003e4.6 Read Delay\u003c/h2\u003e\n\u003cp\u003eThe period of time between the RWL signal being triggered and the RBL signal discharging to 50% of its highest value is known as the calculated read delay. At a 1V cell power source, the suggested design's read latency is 80 ps. The read latency of the suggested design at various voltages is shown in Fig.\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.15\u003c/span\u003e. This can be detected that the read delay of proposed design is reduced by 52%, 33%, and 38% while increased by 18% when compared to basic 6T SRAM cell\u003csup\u003e[11]\u003c/sup\u003e, NBL\u003csup\u003e[16]\u003c/sup\u003e, V\u003csub\u003eDD\u003c/sub\u003e collapse\u003csup\u003e[17]\u003c/sup\u003e and 9T UV SRAM\u003csup\u003e[19]\u003c/sup\u003e respectively. Using an isolated read port for read operation allows for this decrease in read time.\u003c/p\u003e\n\u003cdiv class=\"gridtable\"\u003e\n\u003ctable id=\"Tab1\" border=\"1\"\u003e\u003ccaption\u003e\n\u003cdiv class=\"CaptionNumber\"\u003eTable 4.1\u003c/div\u003e\n\u003cdiv class=\"CaptionContent\"\u003e\n\u003cp\u003eRead and Write Power at Different supply Voltages.\u003c/p\u003e\n\u003c/div\u003e\n\u003c/caption\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth align=\"left\"\u003e\n\u003cp\u003eSupply Voltage (V)\u003c/p\u003e\n\u003c/th\u003e\n\u003cth align=\"left\"\u003e\n\u003cp\u003eRead Power\u003c/p\u003e\n\u003c/th\u003e\n\u003cth align=\"left\"\u003e\n\u003cp\u003eWrite Power\u003c/p\u003e\n\u003c/th\u003e\n\u003c/tr\u003e\n\u003c/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e0.2\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e59 nW\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e278 nW\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e0.4\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e505 nW\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e1.39 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e0.6\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e2.16 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e4.22 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e0.8\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e6.4 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e11.82 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e1.0\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e12.5 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003ctd align=\"left\"\u003e\n\u003cp\u003e26.3 uW\u003c/p\u003e\n\u003c/td\u003e\n\u003c/tr\u003e\n\u003c/tbody\u003e\n\u003c/table\u003e\n\u003c/div\u003e\n\u003c/div\u003e\n\u003cdiv id=\"Sec17\" class=\"Section2\"\u003e\n\u003ch2\u003e4.7 Dynamic power dissipation\u003c/h2\u003e\n\u003cp\u003eThe SRAM cell's dynamic power dissipation may be measured while it is used in write and read mode. The suggested design's write power is raised due to the NBL circuit's rise in gate to source transistor voltage, which causes access and pull-down transistor current to increase. The proposed design's read power, however, is minimal. Table\u0026nbsp;\u003cspan class=\"InternalRef\"\u003e4.1\u003c/span\u003e displays the dynamic power dissipation of the proposed architecture, including parasitic components, during read and write operations at various VDDs.\u003c/p\u003e\n\u003c/div\u003e"},{"header":"5. Conclusions","content":"\u003cp\u003eSince low power integrated circuits are widely used in portable electronic devices, their necessity is well understood. Static Random Access Memory (SRAM) on the SoC (System on Chip) controls both the speed and power consumption of the device. Therefore, having low power SRAMs is crucial. We have been reducing the size of CMOS devices for more than 50 years in order to make them portable, small, and to achieve superior performance in terms of access time, power consumption, latency, etc. As a result, there is a greater need for memory that is small and low-powered. Working on low VDD and energy leakage has become a top priority since there is a lot of room for power consumption reduction. The oxide thickness and operating voltage continue to drop as IC manufacturing technology scales. Lower operating voltage will reduce the SRAM cell's stability, resulting in a lower static noise margin value. Certain essential factors, including static noise margin, read and write latency, static power dissipation, etc., regulate the SRAM cell. Designing an SRAM cell that performs better while taking into account all of the aforementioned characteristics at once is difficult. The designers have always had to make concessions in order to improve certain criteria at the expense of others. The necessity and application of the SRAM will determine which characteristics must be increased and which parameters can be compromised. This study offers a negative bit-line (NBL) write assist circuit for increasing the write stability of SRAM cells and a separate (isolated) read port for improving the read stability in order to increase stability and speed. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other factors, the suggested design has been compared to previous state-of-the-art work. When designed with a 1V cell, it has been shown that the WSNM has improved by 48, 11%, 19%, and 32.4%, while the write latency has decreased by 33%, 39%, 48%, and 22% when compared to standard 6T SRAM cell, NBL, VDD collapse, and 9T UV SRAM, respectively.\u003c/p\u003e"},{"header":"6. Statements and Declarations","content":"\u003cp\u003e\u003cstrong\u003e6.1 Funding\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors affirm that they did not accept any money, grants, or other assistance for the creation of this manuscript.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e6.2 Conflicts of Interest\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThere are no material financial or non-financial interests to report for the authors.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e6.3 Contributions of the Authors\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eProf Dr. Vinod Kumar: Conceptualization, Supervision, Methodology, Validation, Review and Editing\u003c/p\u003e\n\u003cp\u003eMr. Ram Murti Rawat: Conceptualization, Methodology, Writing, Validation, Review and Editing\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e6.4\u0026nbsp;\u003c/strong\u003e\u003cstrong\u003eData Availability Statement\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eWe currently have no additional data.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003e6.5\u003c/strong\u003e \u003cstrong\u003e\u003cem\u003eThe withdrawal notification has now been placed on your preprint, and the title has been hidden from the platform search function. Here is the link to the withdrawn preprint:\u003c/em\u003e\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003ehttps://doi.org/10.21203/rs.3.rs-2296617/v1\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eJ.M. Rabies, Digital integrated circuits, Prentice Hall, (1996).\u003c/li\u003e\n\u003cli\u003eK . Itch, VLSI Memory Chip Design,Springer-Verlag, NY, 2001.\u003c/li\u003e\n\u003cli\u003eK. Roy and S.C. Prasad. Low-Power CMOS VLSI Circuit Design. John Wiley and Sons, 2000.\u003c/li\u003e\n\u003cli\u003eChusen Duari et al.,\u0026quot; Low Leakage SRAM Cell With Improved Stability for IoT Applications,\u0026quot; Third International Conference on Computing and Network Communications (CoCoNet\u0026rsquo;19), pp. 1469-1478, Trivandrum, Kerala, India, 2020.\u003c/li\u003e\n\u003cli\u003eR. M. Rawat and V. Kumar, \u0026ldquo;Low power pre-charge voltage level and low swing logic based 8T SRAM cell for high speed CMOS circuits,\u0026quot; 32nd International Conference on Microelectronics (MIEL), pp. 243-246, Nis, Serbia, 2021.\u003c/li\u003e\n\u003cli\u003eM. F. Chang et al., \u0026quot;A Compact-Area Low-V\u003csub\u003eDDmin\u003c/sub\u003e 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme,\u0026quot; IEEE Journal of Solid-State Circuits , vol. PP, no.99, pp.1-17, 2017.\u003c/li\u003e\n\u003cli\u003eN. Zheng and P. Mazumder, \u0026quot;Modeling and Mitigation of Static Noise Margin Variation in Sub-threshold SRAM Cells,\u0026quot; IEEE Transactions on Circuits and Systems I: Regular Papers, vol. PP, no.99, pp.1-11, 2017.\u003c/li\u003e\n\u003cli\u003eM. Elangovan and K. Gunavathi, \u0026quot;High Stable and Low Power 8T CNTFET SRAM Cell.\u0026quot; Journal of Circuits, Systems and Computers 29, no. 05, 2020.\u003c/li\u003e\n\u003cli\u003eR. Lorenzo and S. Chaudhury, \u0026quot;Optimal Body Bias to Control Stability, Leakage and Speed in SRAM Cell.\u0026quot; Journal of Circuits, Systems and Computers 25, no. 08, 2016.\u003c/li\u003e\n\u003cli\u003eC. I. Kumar and B. Anand, \u0026quot;Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell‖ Electronics Letters, vol. 54, no. 25, pp. 1423-1424, 2018.\u003c/li\u003e\n\u003cli\u003eG. Torrens et al., \u0026quot;A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors,\u0026quot; IEEE Transactions on Emerging Topics in Computing, 2017.\u003c/li\u003e\n\u003cli\u003eS. R. Mansore, R. S. Gamad, and D. K. Mishra. \u0026quot;A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability.\u0026quot; Journal of Circuits, Systems and Computers 29, no. 05, 2020.\u003c/li\u003e\n\u003cli\u003eG. Prasad et al., \u0026quot;Design and statistical analysis of low power and high speed 10T static random access memory cell.\u0026quot; International Journal of Circuit Theory and Applications, 2020.\u003c/li\u003e\n\u003cli\u003eE. Karl et al., \u0026quot;The impact of assist-circuit design for 22nm SRAM and beyond\u0026quot;, International Electron Devices Meeting, pp. 25-1. IEEE, 2012.\u003c/li\u003e\n\u003cli\u003eJ. Kulkarni, et al., ―Dual VCC 8T bitcell SRAM array in 22nm trigate CMOS for energy efficient operation across wide dynamic voltage range,‖ Symp. VLSI Circuits, pp. C126\u0026ndash;C127, Jun. 2013.\u003c/li\u003e\n\u003cli\u003eY. H. Chen, et al., A 16nm 128Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low VMIN applications,‖ IEEE Int. Solid-State Circuits Conf., pp. 238\u0026ndash;239, Feb. 2014.\u003c/li\u003e\n\u003cli\u003eE. Karl, et al., ―A 4.6GHz 162Mb SRAM design in 22nm trigate CMOS technology with integrated active V\u003csub\u003eMIN\u003c/sub\u003e-enhancing assist circuitry,‖ IEEE Int. Solid-State Circuits Conf., pp. 230\u0026ndash;232, Feb. 2012.\u003c/li\u003e\n\u003cli\u003eA. J. Bhavnagarwala, et al., ―A sub-600-mv, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing,‖ IEEE J. Solid State Circuits, vol. 43, no. 4, pp. 946\u0026ndash;955, Apr. 2008.\u003c/li\u003e\n\u003cli\u003eB. Wang, et al., \u0026quot;Design of an Ultra-low Voltage 9T SRAM with Equalized Bit-line Leakage and CAM-Assisted Energy Efficiency Improvement,\u0026quot; IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 2, pp. 441-448, Feb. 2015.\u003c/li\u003e\n\u003cli\u003eM. H. Tu, et al., ―Single ended sub-threshold SRAM with asymmetric a write/read-assist,‖ IEEE Trans. on Circuits Syst. I, vol. 57, no. 12, pp. 3039\u0026ndash;3047, Dec. 2010.\u003c/li\u003e\n\u003cli\u003eA. Banerjee, S. Kamineni, and B. H. Calhoun. \u0026quot;Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low- VMIN IoT and Cognitive Applications.\u0026quot; In Proceedings of the International Symposium on Low Power Electronics and Design, p. 32. ACM, 2018.\u003c/li\u003e\n\u003cli\u003eJ. M. Rabaey, A. Chandrakasan, and B.Nikolic, Digital integrated circuit: A Design Perspective (2nd edition). Englewood Cliffs, NJ: Prentice hall.\u003c/li\u003e\n\u003cli\u003eE. Grossar, M. Stucchi, K. Maex and W. Dehaene, \u0026quot;Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,\u0026quot; IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006.\u003c/li\u003e\n\u003cli\u003eH. Makino, et al., ―Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration.\u0026quot; Circuits and Systems 3, 2012.\u003c/li\u003e\n\u003cli\u003eC. B. Kushwah and S. K. Vishvakarma, \u0026quot;A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell,\u0026quot; IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 373-377, Jan. 2016.\u003c/li\u003e\n\u003cli\u003eP. S. Grace and N. M. Sivamangai, \u0026quot;Design of 10T SRAM cell for high SNM and low power,\u0026quot; 3rd International Conference on Devices, Circuits and Systems (ICDCS), pp. 281-285, Coimbatore, 2016.\u003c/li\u003e\n\u003cli\u003eJ. K. Mishra, et al.,-Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications. \u0026quot;Journal of Circuits, Systems and Computers\u0026quot;, Vol. 30, No. 15, 2150270 (2021).\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"SRAM, Stability, Energy efficient, power, High speed and Low-Power VLSI applications","lastPublishedDoi":"10.21203/rs.3.rs-3992933/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-3992933/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eStatic random access memory (SRAM) is the typical memory for very large scale integrated (VLSI) circuits. A major reason for this is the high speed operation for SRAM in comparison to its previous counterparts, a major trade off for the circuit is its high power consumption. With the growing importance of memory architectures, it is crucial to lower the power consumption of SRAM cells. This major goal of this paper is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). SRAM is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The paper is organized into the following sections: 1. Introduction, Section 2 describes related work. The suggested work is explained in section 3, while the results and discussion are included in section 4. The results for all the sections are concluded in section 5 conclusions.\u003c/p\u003e","manuscriptTitle":"Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-02-29 19:27:20","doi":"10.21203/rs.3.rs-3992933/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"db43df18-b5e1-4c9e-ad15-a199b1cca6fb","owner":[],"postedDate":"February 29th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2025-02-11T06:24:16+00:00","versionOfRecord":[],"versionCreatedAt":"2024-02-29 19:27:20","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-3992933","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-3992933","identity":"rs-3992933","version":["v1"]},"buildId":"FbvkV6FR0MCFSLy54lSbu","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}