Proposing an ITC vandalized Threshold Voltage Divergence Model for short channel Omega Gate MOSFET using a partial 3-D Environment

We present an interface-trapped-charge (ITC) vandalized threshold voltage (V TH ) divergence model for omega-gate (Ω-G) MOSFETs using a partial 3-D scaling equation. To account the impact, the model comprises the equivalent number of gates, gate dielectric and silicon film thickness, channel limitations. The impacts of analogous oxide charges on the flat-band voltage are also examined for short-channel-free operation. A thin gate oxide is essential to prevent V TH value divergence caused by the ITC charges. The ITC vandalized device with a thick silicon sheet is altered with wee V TH value variations caused by trapped charges but rapidly increases in the thin silicon sheet device. We can reduce the V TH value by changing the value of oxide-to-gate underlap coverage factor (OUCF). Large underlap coverage factor value is desirable for positive trapped charges and small value for negative trapped charges. A damaged device with negative trapped charges performs better in short-channel conditions than one with positive trapped charges. Due to its 3-D nature, the proposed model may be efficiently used to investigate the V TH behavior and the device operating characteristics of omega-gate (Ω-G) MOSFET. It may also be competently used in device memory cell applications. Hence, the proposed model provides a deep understanding of device physics along with its computational ability, effectiveness and simplicity.