Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

Abstract This paper presents the design of an inverter, half adder, and ring oscillator using compact models of MoS2 channel-based tunnel field effect transistor (TFET). The TFET models (both n and p-type) are written in high-level hardware language Verilog-Analog (Verilog-A) following the analytical model of [1] and the output characteristics of the components are simulated in Cadence/Spectre software. The performance of the designed inverter (a basic building block of VLSI circuit) is analyzed by extracting its different parameters, such as transfer characteristics, power dissipation and consumption, delay, power delay product. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Moreover, our observation reveals that the ring oscillator can operate at a higher frequency with lower power consumption in comparison to the existing CMOS and GFET technologies. We have also reported an improvement to the limiting factor of ring oscillator performance i.e. phase noise at two different offset frequencies. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuit.