In-Network Memory Access: Bridging SmartNIC and Host Memory

In-Network Memory Access: Bridging SmartNIC and Host Memory | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article In-Network Memory Access: Bridging SmartNIC and Host Memory Mohammed Zain Farooqi, Masoud Hemmatpour, Tore Heide Larsen This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7047360/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 13 You are reading this latest preprint version Abstract SmartNICs have been increasingly utilized across various applications to offload specific computational tasks, thereby enhancing overall system performance. However, this offloading process introduces several communication challenges that must be addressed for effective integration. A key challenge lies in establishing efficient communication between the offloaded components and the main application running on the host. In this study, we evaluate different approaches for achieving memory access between the host and SmartNIC. We analyze memory access performance on both the SmartNIC and the host to support in-network applications and guide the selection of an appropriate memory access design. In-network computing FPGA SmartNIC DPU Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 22 Feb, 2026 Reviews received at journal 19 Feb, 2026 Reviews received at journal 15 Feb, 2026 Reviewers agreed at journal 03 Feb, 2026 Reviewers agreed at journal 02 Feb, 2026 Reviews received at journal 02 Feb, 2026 Reviewers agreed at journal 30 Jan, 2026 Reviewers agreed at journal 29 Jan, 2026 Reviewers agreed at journal 29 Jan, 2026 Reviewers invited by journal 29 Jan, 2026 Editor assigned by journal 08 Jul, 2025 Submission checks completed at journal 08 Jul, 2025 First submitted to journal 04 Jul, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-7047360","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":583621484,"identity":"f8f1d2ae-345c-4c10-af4a-4229fd3af004","order_by":0,"name":"Mohammed Zain Farooqi","email":"","orcid":"","institution":"","correspondingAuthor":false,"prefix":"","firstName":"Mohammed","middleName":"Zain","lastName":"Farooqi","suffix":""},{"id":583621485,"identity":"c2de38a0-a11a-4e09-b7ff-bc03dfa05814","order_by":1,"name":"Masoud Hemmatpour","email":"","orcid":"","institution":"","correspondingAuthor":false,"prefix":"","firstName":"Masoud","middleName":"","lastName":"Hemmatpour","suffix":""},{"id":583621486,"identity":"7ea8b675-4808-4aed-90b9-ab2d7ee53dab","order_by":2,"name":"Tore Heide Larsen","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAq0lEQVRIiWNgGAWjYLCCBxUMPAwMzA3EqeYBEQlnQDQjKVoS20AksVrs2XsfPkicVyejOyOx8QPjDhsibOE5bmyQuO0wj9mNxGYJxjNpRGiRSGOTSNx2AKSlQYKx7TBRWth/JM6pA9vyg1gtbAyJDcwgLW1E2nLmGLNEwjGgX848bLNIbCPCL+ztbYwfPtTU2ZsdTz5842MbESGGChJI1TAKRsEoGAWjADsAAJgmNg7i1TBvAAAAAElFTkSuQmCC","orcid":"","institution":"","correspondingAuthor":true,"prefix":"","firstName":"Tore","middleName":"Heide","lastName":"Larsen","suffix":""}],"badges":[],"createdAt":"2025-07-04 13:38:28","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-7047360/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-7047360/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":101753034,"identity":"40b9dedd-44d8-4ee3-a8e3-327d033967de","added_by":"auto","created_at":"2026-02-03 10:38:58","extension":"pdf","order_by":1,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2284000,"visible":true,"origin":"","legend":"","description":"","filename":"Innetworkmemoryaccessspringer.pdf","url":"https://assets-eu.researchsquare.com/files/rs-7047360/v1_covered_37b9666e-f02d-40ba-a036-f20442c4e863.pdf"}],"financialInterests":"No competing interests reported.","formattedTitle":"In-Network Memory Access: Bridging SmartNIC and Host Memory","fulltext":[],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":false,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":true,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":true,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"the-journal-of-supercomputing","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"Learn more about [The Journal of Supercomputing](https://www.springer.com/journal/11227)","snPcode":"11227","submissionUrl":"https://submission.nature.com/new-submission/11227/3","title":"The Journal of Supercomputing","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"stoa","reportingPortfolio":"Springer Hybrid","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"In-network computing, FPGA, SmartNIC, DPU","lastPublishedDoi":"10.21203/rs.3.rs-7047360/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-7047360/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"SmartNICs have been increasingly utilized across various applications to offload specific computational tasks, thereby enhancing overall system performance. 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