Gate structuring on bilayer transition metal dichalcogenides enables ultrahigh current density

Gate structuring on bilayer transition metal dichalcogenides enables ultrahigh current density | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Gate structuring on bilayer transition metal dichalcogenides enables ultrahigh current density Jeehwan Kim, Junyoung Kwon, Kyoung Yeon Kim, Dongwon Jang, Min Seok Yoo, and 13 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-4632503/v1 This work is licensed under a CC BY 4.0 License Status: Published Journal Publication published 09 Jan, 2026 Read the published version in Nature Materials → Version 1 posted You are reading this latest preprint version Abstract The foundry industry and academia dedicated to advancing logic transistors are encountering significant challenges in extending Moore's Law. In the industry, silicon (Si)-based transistors are currently adopting gate-all-around (GAA) structures and reducing channel thickness, even at the cost of decreased mobility, for maximizing gate controllability. To compensate for the reduced mobility, multi-channel structures are essential, making the fabrication process extremely challenging. Meanwhile, two-dimensional (2D) semiconductors are emerging as strong alternatives for the channel material in logic transistors, thanks to their ability to maintain crystallinity even when extremely thin. In the case of 2D semiconductors, introducing a dual gate structure, which has a much lower fabrication complexity, can achieve effects similar to GAA. Through this research, we have identified the fringing field originating from the common structure of elevated top contact in 2D FETs results in a high charge injection barrier. Through simulation and statistical analysis with large-area FET arrays, we confirmed that introducing a dual-gate structure in bilayer MoS 2 FETs effectively compensates for the fringing field. We have confirmed that this leads to a significant boost in on-current. Remarkably, even with conventional contacts and polycrystalline materials, we observed a record-high on-current of 1.55 mA/µm. Additional circuit simulations have confirmed the potential for dual gate bilayer FETs to surpass the performance of Si GAAFETs when possessing a gate length of 5 nm, achievable only with 2D materials. Therefore, here we propose that by using 2D materials, we can focus on extreme gate length scaling and monolithic 3D integration rather than the challenging GAA process for extending Moore’s Law. Physical sciences/Materials science/Materials for devices/Electronic devices Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices Physical sciences/Nanoscience and technology/Nanoscale materials/Two-dimensional materials Figures Figure 1 Figure 2 Figure 3 Figure 4 Main text As silicon (Si) transistors approach their atomic limits for gate length scaling, foundry companies and related academic society are focusing on enhancing the electrostatic control capability of the channel. The strategy now being adopted is structurally positioning the gate to have more contact with a larger portion of the channel. 1 , 2 This progress has occurred incrementally, evolving from the one-sided planar field-effect transistor (FET) to the three-sided Fin-FET, and ultimately to the four-sided gate-all-around (GAA) FET. Simultaneously, there has been a trend towards minimizing the thickness of the channel to gain additional electrostatic controllability. However, it is widely recognized that structural modifications alone will not be sufficient to sustain Moore's law, as the carrier mobility of silicon is expected to decline significantly below a thickness of 5 nm, resulting in a substantial decrease in current. 3 Therefore, to compensate this current reduction, it is essential to adopt a multi-channel configuration. 4 However, fabricating contacts and gates for such a structure requires introducing new processes not used in existing technology, which is very challenging, costly, and yields low. Moreover, future advanced technology nodes below the 1 nm scale lack viable solutions to sustain Moore's Law. 5 Consequently, a “monolayer” crystal semiconductor, so called two-dimensional (2D) transition metal dichalcogenide (TMD), has emerged as a compelling alternative for channel materials because its broken bonds-free surface nature offers a means to mitigate the pronounced short-channel effects observed in silicon. 3 , 6 2D TMDs exhibit high gate controllability as their major advantage, with no mobility drop even at channel thicknesses below 1 nm, theoretically enabling operation at gate lengths of 5 nm or less. Also, since single crystal growth of 2D TMDs on amorphous substrates is possible, sequential fabrication of dual gate structures can be easily implemented. 7 Similarly, due to the thin thickness, the dual gate structure can achieve effects similar to GAA structures. Nevertheless, until now, predictions that the thin nature of 2D materials would allow sufficient electrostatic control with single gate structures and the challenges of depositing high-quality top gates on 2D materials have hindered dual gate research. 8 As a result, TMD-based single gate transistors have not demonstrated significantly improved on-current ( I on ) performance compared to Si counterparts. So far, substantially high contact resistance between TMDs and metals has been regarded as the primary hurdle for achieving higher I on . In reality, a substantial improvement in I on has been observed by simply identifying appropriate contact metals. 9 , 10 Consequently, the research community’s focus has been centered around an interface engineering between metals and TMDs. Meanwhile, in this study, we reveal how significantly the introduction of dual gate structures can improve transistor performance with both simulations and experiments. Our circuit simulations demonstrate that with extreme gate length scaling in dual gate structures, performance comparable to Si 3 nm node technology fabricated using GAA processes can be achieved. By adopting planar dual gate FETs instead of the highly complex GAAFETs, similar performance can be achieved. This allows for monolithic 3D integration on arbitrary substrates at low temperatures, creating area gains and paving the way to sustain Moore's Law even at advanced nodes below 1 nm. 11 First, we discovered through simulations an important factor that has been overlooked in 2D TMD-based transistors: the potential barrier caused by the fringing field from the elevated top contact electrodes. We confirmed that the influence of the fringing field is greater in bilayers than in monolayers and that applying a dual gate can partially offset this potential barrier. As a result, introducing a dual gate for bilayer TMDs is expected to increase the current by approximately five times compared to single gate structures. To verify this sudden boost in I on through statistical experiments, we fabricated FET arrays on a 200-mm wafer-scale monolayer and bilayer MoS 2 films and observed the improvement in electrical performance for dual gate structures compared to single gate structures. Experimentally, it was confirmed that the I on of dual gate structures increased by approximately three times compared to single gate structures. Through the extraction of contact resistance ( R C ) using the statistical transfer length method (TLM), we confirmed that the reduction of the barrier near the contact electrode due to the introduction of dual gates is particularly pronounced in bilayer MoS 2 , aligning perfectly with our simulation results. Remarkably, utilizing polycrystalline MoS 2 and conventional Au contact electrodes, we achieved an astonishing I on of 1.55 mA/µm due to the I on boosting effect from the bilayer, dual-gate configuration. Furthermore, our FET utilizes high-k dielectrics on both top and bottom, effectively lowering the operating voltage compared to conventional TMD-based devices using global back gates, bringing it closer to the industrial Si transistors. Based on this, we conducted additional technology computer-aided design (TCAD) and simulation program with integrated circuit emphasis (SPICE) simulations and confirmed that bilayer MoS 2 dual gate transistors can achieve comparable I on compared to Si transistors at the 3 nm node, especially for gate lengths below 10 nm. We also confirmed the potential for our current device to operate normally without significant performance degradation compared to a planar Si circuit at the 45 nm node, which has the most similar geometry with our FET. As gate lengths for 2D TMD-based FETs further decrease, the contacted poly pitch (CPP) also decreases, potentially leading to area gain. This aspect could offer advantages over Si GAAFETs in terms of performance, power, and area (PPA). One of the greatest advantages of 2D materials is not only their extremely thin thickness but also the ability to grow single crystals on amorphous substrates, enabling their use in monolithic 3D integration. Therefore, we have demonstrated for the first time in this study that creating complementary FETs (CFETs) based on dual gate structures, rather than GAAFET processes which have higher fabrication complexities, and integrating these layers in a stacked configuration, may offer advantages when considering costs and performance. 7 , 11 On-current and electrical potential in single gate and dual gate MoS 2 FETs as predicted by TCAD simulations Unlike Si transistors, 2D TMDs lack heavy doping technology so far, necessitating direct metal contact to the undoped channel area. This contact takes the form of an elevated top metal electrode. In such a case, a relatively large fringing field can be expected between the metal and the channel near the metal. Nevertheless, until now, only considered as parasitic capacitance, no one has taken into account its impact on the current in the channel. 12 On the other hand, the electrical band gap of the most common TMD, monolayer MoS 2 , is relatively large, which is advantageous for leakage suppression. 13 , 14 However, it poses challenges in obtaining sufficient carrier mobility, and direct metal contact induces a large Schottky barrier height, leading to significant contact resistance. It is because the smaller band gap of the bilayer induces a lower Schottky barrier height, resulting in superior contact characteristics compared to monolayers. 15 Hence, bilayer MoS 2 could offer more physical space to transport charge carriers in response to the gate bias, resulting in the higher carrier mobility. 16 Therefore, to enhance the performance of the FET further, we opted for a straightforward combination of bilayer MoS 2 and a dual-gate configuration. 17 – 19 In this study, we systematically analyzed the impact of the fringing field, a factor that has always been present in 2D FETs but has been overlooked so far. Due to the characteristics of freestanding 2D materials, creating a back gate structure is relatively straightforward. Then, by creating a top gate, a typical MoS 2 dual gate FET is easily fabricated, as shown in the structure depicted in Fig. 1 a. For high performance, it is essential that the equivalent oxide thickness (EOT) of the top and bottom dielectrics are balanced. However, forming a high-quality top gate dielectric layer on a 2D material is challenging due to the noble surface, as widely acknowledged. 20 We utilized a low-temperature ALD interlayer deposition method known as the 'nanofog' technique to deposit the high quality top gate dielectric. 8 Furthermore, to align our simulations with our experimental results, we avoided using materials that might react with the 2D material or generate a native oxide layer easily. Therefore, we employed gold (Au) for both the source-drain and gate electrodes. Representative dual gate device's top view scanning electron microscopy (SEM) image and cross-section transmission electron microscopy (TEM) image are shown in Fig. 1 b and 1 c, respectively. Based on the real device geometry, we conducted accurate TCAD simulation modeling as shown in Fig. 1 d. In previous TCAD simulations based on 2D materials, the actual shape of the electrodes was not considered accurately. 21 – 23 Also, they were limited by using silicon-based tools to simulate 2D materials, which only considered changes in thickness and basic properties, leading to significant inaccuracies when compared to the experimental results. To confirm the characteristics of bilayer MoS 2 through simulation, we included the van der Waals gap between the upper and lower MoS 2 layers, which is the most significant difference from Si. Then we designed the simulation to match the known properties of bilayer MoS 2 , including band gap and dielectric constant. Based on this modeling, we conducted TCAD simulations for both monolayer and bilayer MoS 2 for both single gate and dual gate FET configurations. Initially, we defined the on-state for all cases with a gate-source voltage ( V gs ) of 3 V and a drain-source voltage ( V ds ) of 1 V. Subsequently, we extracted the corresponding currents for each case as shown in Fig. 1 e. For the monolayer, the introduction of the dual gate led to a doubling of the gate capacitance. Consequently, the electron density within the channel increased by approximately two-fold, being expected to result in an increase in current of about 2 times. However, in the case of the bilayer, the dual-gate FET exhibited a substantial increase in current, approximately five times higher compared to the single-gate configuration. This is highlighted in Fig. 1 e, where the additional increase in current, denoted by the 'question mark', indicates a notable contribution beyond the carrier density increase upon the application of dual gates in bilayer MoS 2 . As evident from the calculated transfer curves ( I ds – V gs ) in Extended Data Fig. 1 , there is no apparent impact due to the negative shift in the threshold voltage. Instead, the suppression of the short-channel effect in the dual-gate configuration leads to an improvement in subthreshold characteristics. In Fig. 1 f and 1 g, we illustrated the simulation results of the electrostatic potential within monolayer and bilayer MoS 2 FETs at on-state, respectively. In the enlarged view of the MoS 2 layer vicinity, as depicted in Supplementary Information Fig. S1 , differences in modeling between monolayer and bilayer can be observed. In both cases, we observe a significant potential drop around the source electrode in the single gate configuration, and this effect is mitigated when the dual gate is applied. The line profiles of the energy of conduction band edge in the x-direction for monolayer and bilayer MoS 2 , along with the corresponding electron density, are plotted in Fig. 1 h and 1 i, respectively. For bilayer MoS 2 , considering that the top layer in direct contact with the top metal contact serves as the main conduction layer, we computed the line profile specifically for this layer. (For potential profile of the bottom layer, see Fig. S2) Under all conditions, pronounced energy barriers are observed around the source electrode, leading to a notable reduction in charge density in this region. This barrier is directly attributed to the fringing field from the elevated contact. We demonstrated the creation of a low fringing field structure, suppressing the fringing field and consequently lowering the barrier. Therefore, as shown in Fig. S3, under the low fringing field conditions for bilayer MoS 2 FETs, a higher on-current can be obtained. Here, a significant distinction between monolayer and bilayer is apparent. In the case of the monolayer, there is minimal change in the barrier height even after the introduction of dual gates. However, for the bilayer, the dual-gate introduction noticeably compensates for this fringing field. The reason why the fringing field is more effectively compensated in the bilayer MoS 2 with dual gate compared to monolayer can be explained as follows: In monolayer MoS 2 , it is already significantly influenced by the back gate, whereas the main conduction layer in bilayer is the top layer, so lower layer screens out some of the effects of the back gate. At the same time, the top layer is more directly affected by the fringing field from the top contact. As a result, bilayer MoS 2 FET is expected to exhibit more than a 2-fold increase in additional I on due to the compensation of the fringing field with the introduction of the dual gate. We further theoretically verified it from the capacitance model described in Fig. S4. As well as on-state characteristics, the introduction of dual gates also significantly improved subthreshold characteristics such as subthreshold swing (SS) and leakage current. (Extended Data Fig. 1 ) 200-mm wafer scale growth of monolayer and bilayer MoS Our primary focus has been on achieving the uniform growth of bilayer TMDs across 200-mm wafers, a task not previously demonstrated due to the challenges associated with layer-by-layer growth directly on Si wafers. 24 , 25 Here, we introduced an additive during growth to enhance adatom diffusion. As a result, we could successfully regulate nucleation and promote lateral growth, achieving uniform growth even with bilayer thickness. As a result of these efforts, we have successfully achieved bilayer-dominated MoS 2 growth across 200-mm wafers. This accomplishment has enabled us to establish wafer-scale arrays of bilayer transistors with dual gating capabilities. While the growth of uniform monolayer films has been relatively well-established in previous research, there have been only very limited reports on the growth of uniform bilayer films. 24 Therefore, our focus was on adjusting the average thickness to match bilayer thickness for statistical analysis. To achieve uniform bilayer growth, it is necessary to suppress the nucleation of adlayers until the next layer growth is completed. We were able to obtain relatively uniform monolayer and bilayer films in 200-mm wafer scale through the utilization of the metal-organic chemical vapor deposition (MOCVD) method and use of proper growth additives. (See Methods for details) Fig. 2 a and 2 b respectively display cross-sectional TEM images of the grown monolayer and bilayer. In Fig. 2 c, characteristic Raman peaks of monolayer and bilayer MoS 2 , including E 1 2g and A 1g peaks, along with the Si substrate peak near 520 cm − 1 , are presented. The intensity of the A peak relative to the Si peak is significantly higher in the bilayer than in the monolayer. Moreover, the distance between the E-A peaks directly related to the layer number is precisely in line with the values reported in the literature, measuring 19.8 cm − 1 for the monolayer and 21.9 cm − 1 for the bilayer. 26 Of course, it would be challenging to claim that the entire film is strictly monolayer or bilayer, due to the presence of adlayer patches. However, through statistical Raman analysis, we can track the average number of layers. In Fig. 2 d, the distribution of the analyzed E-A peak distances from 100 Raman spectra within a 10 cm by 10 cm area of as-grown MoS 2 films is plotted. Also, as evident from the Raman mapping in Extended Data Fig. 2 , it can be confirmed that a generally uniform monolayer and bilayer were fabricated. Therefore, we can statistically consider the two MoS 2 films as predominantly monolayer and bilayer, respectively. Statistical assessment of monolayer and bilayer MoS FETs with single and dual gate configurations Based on the growth of wafer-scale monolayer and bilayer films, we succeeded fabricating FET arrays on 200-mm wafers. (Inset of Fig. 3 a) The detailed fabrication process is described in Fig. S5 and the Methods section. (For cross-section TEM images of the devices see Fig. S6) To ensure accurate analysis on difference between single gate and dual gate configurations, we measured the same device both before and after the formation of the top gate electrode. In this study, the analysis of the top gate-only configuration is not of significant relevance since the field from the top gate has a limited impact on lowering the contact barrier, while back gate electrostatically dopes contact region at the on-state. This can be observed from the statistical analysis of long-channel devices ( L ch > 500 nm) fabricated by only photolithography shown in Extended Data Fig. 3 . The measurements of the top-gate-only configuration reveal that it exhibits performance that is more than an order of magnitude lower than that of the back gate, due to the lower quality of top-gate dielectric compared with pre-deposited back-gate dielectric as well as lack of contact gating. Meanwhile, the transfer curves ( σ SH – V gs ) of hundreds of monolayer and bilayer MoS 2 FETs are plotted in Fig. 3 a and 3 b, respectively. The channel length ( L ch ) here was varied from 30 nm to 300 nm. In order to normalize the current with channel length and width of the various FETs, the y-axis was represented in sheet conductance ( σ SH ). The results indicate that both SS and I on are superior in the dual gate configuration compared to the single gate. Also, based on this, the change in I on with respect to L ch was plotted for monolayer and bilayer as shown in Fig. 3 c and 3 d, respectively. A huge increase in I on of dual-gate FET compared to single-gate FET was observed in all L ch ranges for dual gate FET. It is quite remarkable that the MoS 2 film, despite being polycrystalline, exhibits an average I on of around 700 µA/µm at L ch of 30 nm, simply with the combination of bilayer and dual gates. Interestingly, in bilayers, the increase in I on with dual gate compared to single gate is consistent regardless of L ch , whereas in monolayers, the increase becomes more pronounced as L ch increases. In previous simulation results, the difference of potential barrier height between single and dual gate in monolayers is not significant. Consequently, in the contact-dominant regime of short channels, the difference is around two-fold. However, in long channels, which enter the channel-dominant regime, changes in the channel that were not apparent in simulations seem to be observed. To investigate this further, we conducted TLM analysis for each case using the transfer curves for each L ch , as illustrated in Extended Data Fig. 4 . Here, V gs in each transfer curve was converted to overdrive voltage ( V od ), which was further transformed into carrier density using the capacitance values extracted in the various metal-insulator-metal (MIM) structures, as shown in Fig. S7. As a result, it is able to plot R C as a function of planar carrier density ( n 2D ), as shown in Fig. 3 e and 3 f for monolayer and bilayer, respectively. In both cases, the dual gate has a roughly two-fold higher capacitance than the single gate at the same V gs , resulting in a broader range of n 2D for the dual gate. Interestingly, as shown in Fig. 3 e, the lowest R C in the monolayer is comparable between the single gate and dual gate, measuring around 4.1 kΩ∙µm and 4.6 kΩ∙µm, respectively. This aligns precisely with the simulation results in Fig. 1 h, where the difference in charge injection barrier due to the fringing field was minimal. On the other hand, examining Fig. 3 f, in the bilayer, the R C shows a value of 4.3 kΩ∙µm under the single gate, which is not significantly different from the monolayer. However, with the introduction of the dual gate, it drastically improves to 1.3 kΩ∙µm, aligning precisely with the reduced charge injection barrier observed in the simulation in Fig. 1 j. As summarized in Fig. 3 g, the I on of dual gate monolayer MoS 2 FET showed an average increase of 2 times compared to a single gate, while in bilayer MoS 2 FET, it shows an increase of around 3.6 times. Surprisingly, this also matches exactly with the predictions made in Fig. 1 e. Now, we can attribute the additional increase in the bilayer to the compensation of the fringing field coming from the top gate. In Fig. 3 h, we plotted the proportion of R C and channel resistance ( R ch ) in the total resistance based on the R C and sheet resistance ( R sh ) extracted from TLM in Extended Data Fig. 4 . In the shortest FETs with L ch of 30 nm, the current proportion of R C is significant, and the twofold decrease in resistance in monolayers can be attributed to a rapid decrease in R sh while R C remains relatively constant. This holds true for bilayers as well, where not only R C but also the sharp decrease in R sh results in a substantial reduction in overall resistance. The crucial message here is that even with the thin thickness of monolayers, it is challenging to achieve full accumulation throughout the entire channel with only one-sided gating. The use of dual gates is essential to fully utilize the entire channel. Therefore, it implies that the carrier mobility of the channel can vary depending on the gate, even for the same material. This can be observed in Fig. S8, which compares the TLM mobility, excluding contact effect, extracted using the TLM method. Therefore, we have validated the fact that, even with an extremely thin channel material, leveraging the dual gate structure is advantageous. Benchmarking Ion of dual gate bilayer MoS2 FET To assess the maximum current level that MoS 2 can handle, we selected the best device of bilayer MoS 2 with dual gate configuration from the previously measured FETs and increased the V gs range up to + 4 V. Transfer curves ( I ds – V gs ) of the best device plotted in semi-log and linear scale are plotted in Fig. 4 a. The linear shape in the output curves ( I ds – V ds ) at low V ds regime in Fig. 4 b demonstrates that the contact is ohmic, contributing to the record-high I on of 1.55 mA/µm. We benchmarked the obtained I on as a function of V ds from the device in Fig. 4 c among n-type 2D FETs. Even with a simple structural change, we achieved higher I on compared to single crystal-based FETs. Of course, while direct comparisons with commercially available silicon-based components are not reasonable, our FET outperforms the I on requirements suggested by IEEE International Roadmap for Devices and Systems (IRDS) 2022 roadmap, 5 being leveraged from the maximum potential of bilayer MoS 2 by introducing dual gate. It is significant that these results were obtained at the lower source-drain bias ( V ds ) and V od among the high on-current 2D semiconductor-based FETs. 9 , 10 , 24 , 27 – 31 (Fig. 4 c and 4 d) Many studies have shown that low V ds results in high on-current, suggesting the potential to outperform silicon. However, these figures mostly come from fundamental research using global back gates, and thus are measured at high V od , as shown in Fig. 4 d. Except for a recent study, our work shows high I on at an operation voltage most similar to silicon, using local gates. This allows for a more accurate comparison with silicon. To address this, we comparatively examined the performance with a 45 nm node Si transistor that has a relatively similar gate length with our FET. The 45 nm node transistor typically has a gate length ranging from approximately 30 nm to 40 nm and uses a V dd of 1 V, 32 , 33 which are similar to our device. These factors also explain why only a few 2D FET based AC circuits have been reported so far. 22 , 34 , 35 To enable a relatively fair comparison under similar conditions, we scaled V gs by our device's EOT to 1 nm from 3.3 nm and applied an arbitrary shift to align the V th of the two devices as shown in Fig. S9. Here, with an I off of 100 nA/µm and V dd of 1 V, the I on is 690 µA/µm, which is about half the level of the Si 45 nm node FET. 32 , 33 Considering the difference in mobility between bulk Si and our MoS 2 , the results can be regarded as quite comparable. We can calibrate the TCAD model of Fig. 4 e with our experimentally based I-V curve, as shown in Fig. 4 f. Conversely, we can use the TCAD model to simulate I on by reducing the gate length. As shown in Fig. 4 d, to compare with the Si 3 nm node, reducing V dd to 0.7 V and the gate length to 12 nm—the limit for Si gate length—results in an I on increase to 1.27 mA/µm. Further reducing the gate length to 5 nm, the limit for bilayer MoS 2 , increases Ion to 2.08 mA/µm. The Si transistor in this scenario would likely be in a multi-channel configuration, potentially boosting the on-current further. Nevertheless, due to the large capacitance disadvantage inherent in the GAAFET structure, the AC circuit performance is expected to be comparable to that of planar dual gate MoS 2 . To indirectly demonstrate this, we conducted a simulation comparing the circuit performance of our device with that of a 45 nm node Si planar transistor, which has the most similar geometry to our device. Scaling our device to an advanced node involves making significant assumptions and may introduce inaccuracies, which is why we chose to compare it with the 45 nm node Si planar transistor instead. Nonetheless, the following assumptions are still necessary for comparison between our 2D FET and a 45 nm node Si FET. First, assumptions about the performance of p-type metal-oxide-semiconductors (PMOS) are needed. We simply assumed PMOS by symmetrizing the MoS 2 n-type metal-oxide-semiconductors (NMOS). Given that WSe 2 , which is an emerging 2D semiconductor as a PMOS candidate, has higher mobility and I on , we believe this approach is feasible in the future. 3 , 36 Second, to achieve fair circuit performance, it is assumed that there is no vertical overlap between the source/drain electrodes and the gate electrode. In the actual structure, contact doping is achieved using electrostatic gating of the contacts, while this structure results in excessively high gate capacitance, which leads to significant RC delay in the circuit. Instead, gate-dependent contact resistance was separately incorporated into the model using the experimental values from Fig. 3 f. To create a process design kit (PDK), which is crucial for SPICE circuit simulation, compact modeling of the 2D FET is necessary. Among these, the I-V curve can be calibrated using the experimental data from our Fig. S9 to fit the appropriate model. After applying a channel width of 500 nm and using the Verilog-A MIT Virtual Source model (MVS) to calibrate the transfer curves and output curves, we confirmed that the results fit well, as shown in Fig. 4 f. 37 , 38 However, as previously mentioned, we assumed a structure without overlap between source/drain and gate metal to optimize circuit performance, so we cannot use experimental C-V curve for circuit simulation. Therefore, based on the device structure in Fig. 4 e, we extracted the gate capacitance curve ( C gg - V g ) through TCAD simulation, and the results are shown in Fig. 4 g. These results are very similar to the curve calculated using the MVS model, indicating their excellent reliability. Based on these results, we were able to proceed with compact modeling of our 2D FET and simulate a 5-stage ring oscillator. The frequency is 3.56 GHz and 11.05 GHz, corresponding to a delay per stage of 28.1 and 9.1 ps for V dd of 1 V and 2 V, as shown in Fig. 4 h and i, respectively, which is comparable to Si 45 nm node's performance (6 ps). 32 (Fig. S10 and Fig. S11 for gate capacitance and ring oscillator performance of the FETs with overlapped gate, respectively) As we benchmarked our simulated ring oscillator delay in Fig. 4 j, there is still a significant difference between the experimentally obtained performance and the calculated performance. This is because the technology based on 2D materials is still underdeveloped, making it challenging to achieve balanced CMOS fabrication, and the lack of doping technology leads to the absence of spacer processes, resulting in high parasitic capacitance that limits circuit performance. From a device perspective, it is also necessary to engineer the interface with the dielectric and reduce contact resistance. This will not only improve performance but also ensure uniformity and reliability. Hence, for now, since the alternative target for 2D semiconductors is Si nanosheets with channel thicknesses of 4 nm or less, directly surpassing bulk Si planar transistors may not be feasible. Nevertheless, our computational objective was to demonstrate that 2D FETs can achieve performance levels similar to silicon as much as possible. Conclusions Through this study, we confirmed that the fringing field arising from the elevated contact in 2D FETs forms a significant barrier around the source, hindering the charge injection in 2D semiconductors. In particular, for bilayer MoS 2 , the introduction of a dual-gate structure compensates for this fringing field to some extent, leading to a significant boost in current compared to the single gate. This phenomenon was confirmed through simulations to be due to the two layers of bilayer MoS 2 being separated, unlike in Si. The resulting current boost was observed in both simulation and experiment. Furthermore, we demonstrated through TLM methods that the introduction of dual gates not only reduces the charge injection barrier but also increases channel mobility by opening additional electrical paths, even in extremely thin channels. An important point is that, unlike results analyzed from individual unit devices, the reliability of our results is enhanced by statistically comparing hundreds of devices processed through the same 200-mm wafer fabrication process. In essence, by demonstrating the benefits brought about by the introduction of dual gates, we have justified the adoption of GAA structures in 2D FETs, similar to Si. Lastly, our best device, despite utilizing polycrystalline MoS 2 , achieved a DC I on record of 1.55 mA/µm. We conducted simulations to evaluate the performance of our FET when applied to actual planar FETs, as our device achieved high I on while operating at industrially viable voltage levels. Using TCAD, we fitted our experimentally obtained transfer curves and calculated the capacitance. Based on this, we performed compact modeling to implement a 5-stage ring oscillator. The delay per stage was 9.1 ps at V dd of 2 V, which is comparable to that of the 45 nm node Si with similar dimensions. Moreover, in gate lengths below a few nanometers, where there is no degradation in mobility in an extremely thin channel, our device is expected to have a clear advantage over Si nanosheet transistors. Methods TCAD Simulation We use the multi-subband Boltzmann transport equation (MSBTE) solver, implemented in our in-house simulator. It calculates the Schrödinger equation perpendicular to the transport direction and one-dimensional MSBTE for each subband. Mode decomposition is used to reduce the computational burden at the realistic device scale, and periodic boundary condition is applied for the width direction. Layer-dependence effective mass and bandgap are considered as in Table 1, and a multi-layer model considering the van der Waals (vdW) gap is used to accurately reflect the electrostatic effects depending on the device structure. DFT results show that the MoS 2 layer has a high dielectric constant, while the vdW layer has a low dielectric constant. 39 , 40 This causes most of the potential drop to occur in the vdW layer, resulting in a significant difference in the electrical operation of monolayer and multilayer devices. The MSBTE solver is a semi-classical transport equation that cannot originally consider tunneling effects. However, the tunneling current is accurately included as nonlocal intravalley interaction based on the WKB tunneling model. 41 This allows for the accurate consideration of the source-induced injection barrier. In bilayer modeling, another challenge is calculating the current path correctly. In a few-layer top-contact device, the main current path is the top layer, as carriers with small electric field are rarely injected from the source to the bottom layer. However, the MSBTE solver considers the 1D transport equation and imposes the injection boundary condition on the sides, leading to the misleading conclusion that most of the current path is formed in the bottom layer, which is less susceptible to the source fringe field effect. To mimic the low current injection to the bottom layer by tunneling through the vdW layer, a thin tunneling layer is added to the bottom layer as in Fig. S2. Through these detailed modeling efforts, the origin of the substantial gain of I on and decrease of the R C when using dual-gate in a bilayer device is clearly identified. MOCVD of monolayer and bilayer MoS 2 The growth of 200 mm scale monolayer MoS 2 was conducted under the same conditions as in our previous studies. 42 – 44 We used a shower-head-type cold-wall MOCVD reactor for the growth of MoS 2 , utilizing Mo(CO) 6 as the Mo precursor and (C 2 H 5 ) 2 S 2 as the S precursor. The flow rates of the precursors were 0.001 sccm for Mo(CO) 6 , 0.007 sccm for (C 2 H 5 ) 2 S 2 , and 100 sccm for H 2 , all of which were precisely regulated by individual mass-flow controllers and electronic pressure controllers. The chamber pressure and wafer temperature were maintained at 5.0 torr and 600 o C, respectively, during the growth process. We used KI as an additive to improve adatom diffusion, placing it upstream in the reactor. Growth time was controlled from 12 minutes to 1 hour to control the layer number. Fabrication of 200-mm wafer scale FETs First, we started device fabrication with a 200 mm Si wafer and create a 100 nm SiO 2 layer through thermal oxidation. Next, we pattern the bottom gate electrode using photolithography with a stepper. At this stage, the negative process using the image reversal photoresist AZ5214 is utilized, followed by a lift-off process. For the bottom gate metal, 5 nm of Ti and 20 nm of Au are used. The creation of the bottom gate structure is completed by depositing 10 nm of HfO x using atomic layer deposition (ALD). Next a MoS 2 film grown by MOCVD is transferred onto the substrate. As in our previous study, 43 a semi-automatic transfer stage is utilized at this stage. After that, another photolithography process is carried out to pattern the active channel area of MoS 2 . The exposed areas of MoS 2 are etched using O 2 reactive ion etching (RIE) or a plasma asher. Next, we patterned fine source/drain electrodes for the short-channel device using e-beam lithography. In this case, a 495k PMMA A2 / 950k PMMA A2 bilayer is utilized as an e-beam resist for smooth lift-off. In this case, Au 20 nm is used as the contact metal. Another round photolithography, metal deposition, and lift-off are carried out to create metal leads connecting the pads for subsequent measurements. It is important to perform e-beam lithography first in this process, as PR residue can significantly degrade contact resistance of resulting FETs. To facilitate the deposition of dielectric on top of the MoS 2 for the fabrication of the top gate, an interlayer is deposited using a method known as the "nanofog" technique. 8 , 45 Top gate dielectric, 10 nm HfO x , is deposited using ALD. Then, similar to the bottom gate process, patterning is carried out to form the top gate dielectric, completing the device fabrication. See Fig. S5 for visualized fabrication processes. Compact modeling and 5-stage ring oscillator simulation It is crucial to extract I-V and C-V characteristics of 2D FET for obtaining a PDK, assuming that elements like interconnections are similar to existing Si technology. Firstly, in actual devices, electrostatic doping is necessary due to the lack of doping techniques in the contact region. This results in significant parasitic capacitance from the overlap between the source/drain electrodes and the gate electrode. Therefore, we assumed no gate overlap and separately applied the gate-dependent contact resistance to the I-V calibration. Then, we were able to obtain the C-V curve for the assumed structure without overlap using TCAD. The experimentally obtained I-V curve was also utilized with the Verilog-A MVS model. Based on the completed PDK for the 2D FET, we conducted a SPICE simulation of a 5-stage ring oscillator. The load capacitance per stage used in this simulation was 1.2 fF, identical to the value used in previously reported ring oscillators based on 45 nm node Si transistors. 46 , 47 References Cao W et al (2023) The future transistors. Nature 620:501–515 Ferain I, Colinge CA, Colinge J-P (2011) Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479:310–316 Liu Y et al (2021) Promises and prospects of two-dimensional transistors. Nature 591:43–53 Jeong J et al (2023) World’s First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFET ™ ) Process. in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–2 10.23919/VLSITechnologyandCir57934.2023.10185353 IEEE International Roadmap for Devices and Systems 2022 Edition . https://irds.ieee.org/editions/2022 O’Brien KP et al (2023) Process integration and future outlook of 2D transistors. Nat Commun 14:6400 Kim KS et al (2023) Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature 614:88–94 Ko J-S et al (2023) Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2. in ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC) 1–4 10.1109/ESSDERC59256.2023.10268527 Shen P-C et al (2021) Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593:211–217 Li W et al (2023) Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613:274–279 Kim KS et al Seamless monolithic three-dimensional integration of single-crystalline films by growth. 10.48550/arXiv.2312.03206 Guo Y et al (2021) Field-effect at electrical contacts to two-dimensional materials. Nano Res 14:4894–4900 Radisavljevic B, Radenovic A, Brivio J, Giacometti V, Kis A (2011) Single-layer MoS2 transistors. Nat Nanotechnol 6:147–150 Ugeda MM et al (2014) Giant bandgap renormalization and excitonic effects in a monolayer transition metal dichalcogenide semiconductor. Nat Mater 13:1091–1095 Kwon J et al (2017) Thickness-dependent Schottky barrier height of MoS2 field-effect transistors. Nanoscale 9:6151–6157 Cui X et al (2015) Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform. Nat Nanotechnol 10:534–540 Sun Z et al (2022) Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2. ACS Nano 16:14942–14950 Liao F et al (2020) High-Performance Logic and Memory Devices Based on a Dual-Gated MoS2 Architecture. ACS Appl Electron Mater 2:111–119 Asselberghs I et al (2020) Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab. in 2020 IEEE International Electron Devices Meeting (IEDM) 40.2.1–40.2.4 10.1109/IEDM13553.2020.9371926 Illarionov YY et al (2020) Insulators for 2D nanoelectronics: the gap to bridge. Nat Commun 11:3385 Pasadas F et al (2019) Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances. Npj 2D Mater Appl 3:47 Fan D et al (2023) Two-dimensional semiconductor integrated circuits operating at gigahertz frequencies. Nat Electron 6:879–887 Silvestri L et al (2023) Hierarchical modeling for TCAD simulation of short-channel 2D material-based FETs. Solid-State Electron 200:108533 Liu L et al (2022) Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature 605:69–75 Hwangbo S, Hu L, Hoang AT, Choi JY, Ahn J-H (2022) Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor. Nat Nanotechnol 17:500–506 Li H et al (2012) From Bulk to Monolayer MoS2: Evolution of Raman Scattering. Adv Funct Mater 22:1385–1390 Chou A-S et al (2020) High On-Current 2D nFET of 390 µA/µm at VDS = 1V using Monolayer CVD MoS2 without Intentional Doping. in. IEEE Symposium on VLSI Technology 1–2 (2020). 10.1109/VLSITechnology18217.2020.9265040 Chou A-S et al (2021) Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics. in 2021 IEEE International Electron Devices Meeting (IEDM) 7.2.1–7.2.4 10.1109/IEDM19574.2021.9720608 Chou A-S et al (2021) High On-State Current in Chemical Vapor Deposited Monolayer MoS2 nFETs With Sn Ohmic Contacts. IEEE Electron Device Lett 42:272–275 Li L et al (2024) Epitaxy of wafer-scale single-crystal MoS2 monolayer via buffer layer control. Nat Commun 15:1825 Xiong X et al (2021) Demonstration of Vertically-stacked CVD Monolayer Channels: MoS2 Nanosheets GAA-FET with Ion > 700 µA/µm and MoS2/WSe2 CFET. in 2021 IEEE International Electron Devices Meeting (IEDM) 7.5.1–7.5.4 10.1109/IEDM19574.2021.9720533 Cheng K-L et al (2007) A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 µm2 SRAM cell. in. IEEE International Electron Devices Meeting 243–246 (2007). 10.1109/IEDM.2007.4418913 Mistry K et al (2007) A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. in. IEEE International Electron Devices Meeting 247–250 (2007). 10.1109/IEDM.2007.4418914 Zou T et al (2023) High-Performance Solution-Processed 2D P-Type WSe2 Transistors and Circuits through Molecular Doping. Adv Mater 35:2208934 Li N et al (2020) Large-scale flexible and transparent electronics based on monolayer molybdenum disulfide field-effect transistors. Nat Electron 3:711–717 Wu R et al (2022) Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5 milliamperes per micrometre. Nat Electron 5:497–504 Yu L et al (2016) Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics. Nano Lett 16:6349–6356 Nourbakhsh A et al (2016) MoS2 Field-Effect Transistor with Sub-10 nm Channel Length. Nano Lett 16:7798–7806 Mirabelli G, Hurley PK, Duffy R (2019) Physics-based modelling of MoS2: the layered structure concept. Semicond Sci Technol 34:055015 Donetti L et al (2022) Towards a DFT-based layered model for TCAD simulations of MoS2. Solid-State Electron 197:108437 Stanojević Z et al (2021) Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO. IEEE Trans Electron Devices 68:5400–5406 Seol M et al (2020) High-Throughput Growth of Wafer-Scale Monolayer Transition Metal Dichalcogenide via Vertical Ostwald Ripening. Adv Mater 32:2003542 Kwon J et al (2024) 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide transistors. Nat Electron. 10.1038/s41928-024-01158-4 Nguyen VL et al (2023) Wafer-scale integration of transition metal dichalcogenide field-effect transistors using adhesion lithography. Nat Electron 6:146–153 Kwak I et al (2019) Low interface trap density in scaled bilayer gate oxides on 2D materials via nanofog low temperature atomic layer deposition. Appl Surf Sci 463:758–766 Hoffmann T et al (2006) Ni-based FUSI gates: CMOS Integration for 45nm node and beyond. in. International Electron Devices Meeting 1–4 (2006). 10.1109/IEDM.2006.346759 Kittl JA et al (2006) CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS: $ \hbox{Ni}_{2}\hbox{Si} $ , and $ \hbox{Ni}_{31}\hbox{Si}_{12} $ ) on HfSiON. IEEE Electron Device Lett 27:966–968 Chou B-J et al (2024) High-performance monolayer MoS2 nanosheet GAA transistor. Nanotechnology 35:125204 Jiang J et al (2024) Yttrium-doping-induced metallization of molybdenum disulfide for ohmic contacts in two-dimensional transistors. Nat Electron. 10.1038/s41928-024-01176-2 Chen X et al (2021) Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning. Nat Commun 12:5953 Wang H et al (2012) Integrated Circuits Based on Bilayer MoS2 Transistors. Nano Lett 12:4674–4680 Additional Declarations There is NO Competing Interest. Supplementary Files ExtendedData.docx SupplementaryInformationfinal.pdf Cite Share Download PDF Status: Published Journal Publication published 09 Jan, 2026 Read the published version in Nature Materials → Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-4632503","acceptedTermsAndConditions":true,"allowDirectSubmit":false,"archivedVersions":[],"articleType":"Article","associatedPublications":[],"authors":[{"id":324519524,"identity":"2a3a31f2-f4ff-4334-af36-b452a8c3ff9e","order_by":0,"name":"Jeehwan Kim","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAAt0lEQVRIiWNgGAWjYBACxgYGNhAtx8AMothI0GLMwMxMpBaYssQGBmK1MLc3H3vMU3MnfW07/wGGD2WHiXBYz7F0Y55jz3K3HWZmYJxxjhgtM3LMpHPYDoO1MPO2EaNl/vtv0jn/DqebgbT8JUrLDB426dy2wwlgLYxEaelJM5P+23fYEOgwg4M959IJazFsP/xMcsa3w/Jm5w8+fPCjzJoILQ1InAOE1QOBPFGqRsEoGAWjYGQDABN0OdB9X8p2AAAAAElFTkSuQmCC","orcid":"https://orcid.org/0000-0002-1547-0967","institution":"Massachusetts Institute of Technology","correspondingAuthor":true,"prefix":"","firstName":"Jeehwan","middleName":"","lastName":"Kim","suffix":""},{"id":324519525,"identity":"60f45d6c-b78b-4699-965b-1674326c4872","order_by":1,"name":"Junyoung Kwon","email":"","orcid":"https://orcid.org/0000-0002-5351-342X","institution":"Samsung Advanced Institute of Technology (South Korea)","correspondingAuthor":false,"prefix":"","firstName":"Junyoung","middleName":"","lastName":"Kwon","suffix":""},{"id":324519526,"identity":"c0c0dfaf-8cde-40e4-8f1d-642b007c073a","order_by":2,"name":"Kyoung Yeon Kim","email":"","orcid":"https://orcid.org/0000-0001-6977-9831","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Kyoung","middleName":"Yeon","lastName":"Kim","suffix":""},{"id":324519527,"identity":"5f1556cf-a0ce-430c-971d-16c0b2607c13","order_by":3,"name":"Dongwon Jang","email":"","orcid":"","institution":"Georgia Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Dongwon","middleName":"","lastName":"Jang","suffix":""},{"id":324519528,"identity":"3d2661f7-b3d6-4189-8c06-b6def2c86e2e","order_by":4,"name":"Min Seok Yoo","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Min","middleName":"Seok","lastName":"Yoo","suffix":""},{"id":324519529,"identity":"57fc3520-3e7f-459d-9106-68eaf6dcba6b","order_by":5,"name":"Alum Jung","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Alum","middleName":"","lastName":"Jung","suffix":""},{"id":324519530,"identity":"098bde15-7dd0-4781-add8-00d857513658","order_by":6,"name":"Woon Ih Choi","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Woon","middleName":"Ih","lastName":"Choi","suffix":""},{"id":324519531,"identity":"fb95cd8b-bd61-4ea2-8ea8-9b21897c088e","order_by":7,"name":"Yeonchoo Cho","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Yeonchoo","middleName":"","lastName":"Cho","suffix":""},{"id":324519532,"identity":"ce70e977-8d77-4186-b254-adea7baa80bb","order_by":8,"name":"Changhyun Kim","email":"","orcid":"https://orcid.org/0000-0002-0989-1482","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Changhyun","middleName":"","lastName":"Kim","suffix":""},{"id":324519533,"identity":"fd031ce7-841f-4ce6-af72-d4dde2b24160","order_by":9,"name":"Huije Ryu","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Huije","middleName":"","lastName":"Ryu","suffix":""},{"id":324519534,"identity":"b5153ec9-ebb1-429a-a1d4-db4d9f29dd31","order_by":10,"name":"Eunji Yang","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Eunji","middleName":"","lastName":"Yang","suffix":""},{"id":324519535,"identity":"7e67fe4c-eace-4289-873c-8aeb44b87c5d","order_by":11,"name":"Eun-Kyu Lee","email":"","orcid":"https://orcid.org/0000-0003-3056-3827","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Eun-Kyu","middleName":"","lastName":"Lee","suffix":""},{"id":324519536,"identity":"c6438b99-7546-403e-ba0c-c9bf106dadfc","order_by":12,"name":"Chang-Seok Lee","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Chang-Seok","middleName":"","lastName":"Lee","suffix":""},{"id":324519537,"identity":"1197a950-d291-471b-85fb-00d31cc3cad8","order_by":13,"name":"Sangwon Kim","email":"","orcid":"https://orcid.org/0000-0001-7026-8721","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Sangwon","middleName":"","lastName":"Kim","suffix":""},{"id":324519538,"identity":"498ff10d-8e73-4a7b-a474-0f216bff6a9a","order_by":14,"name":"Uihui Kwon","email":"","orcid":"","institution":"Samsung Electronics","correspondingAuthor":false,"prefix":"","firstName":"Uihui","middleName":"","lastName":"Kwon","suffix":""},{"id":324519539,"identity":"46d71bd6-116c-40ee-8025-fc18e068f925","order_by":15,"name":"Sung Kyu Lim","email":"","orcid":"","institution":"Georgia Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Sung","middleName":"Kyu","lastName":"Lim","suffix":""},{"id":324519540,"identity":"720d3b2f-9184-4a45-ad48-45d143aafe5b","order_by":16,"name":"Kyungeun Byun","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology, Samsung Electronics Corporation","correspondingAuthor":false,"prefix":"","firstName":"Kyungeun","middleName":"","lastName":"Byun","suffix":""},{"id":324519541,"identity":"b7843f50-5e33-4176-86e6-4c1dda3fc816","order_by":17,"name":"Minsu Seol","email":"","orcid":"","institution":"Samsung Advanced Institute of Technology","correspondingAuthor":false,"prefix":"","firstName":"Minsu","middleName":"","lastName":"Seol","suffix":""}],"badges":[],"createdAt":"2024-06-24 23:20:26","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-4632503/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-4632503/v1","draftVersion":[],"editorialEvents":[{"content":"https://doi.org/10.1038/s41563-025-02452-y","type":"published","date":"2026-01-09T05:00:00+00:00"}],"editorialNote":"","failedWorkflow":false,"files":[{"id":60024078,"identity":"8fdcfe7e-2801-4166-b6d5-3bfe45a88365","added_by":"auto","created_at":"2024-07-10 16:50:20","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":474783,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eTCAD simulation results based on the actual MoS\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e dual-gate FET\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ea.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eSchematic illustrating MoS\u003csub\u003e2\u003c/sub\u003e dual-gate FET with elevated Au contacts.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eb.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eFalse-color top view SEM images of a device with \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e of 30 nm among the actually fabricated MoS\u003csub\u003e2\u003c/sub\u003e FETs before the fabrication of the top gate.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ec.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eFalse-color cross-sectional TEM image of a representative MoS\u003csub\u003e2\u003c/sub\u003e dual-gate FET\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ed.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eTCAD simulation model of the MoS­\u003csub\u003e2\u003c/sub\u003e dual-gate FET fabricated based on the observed TEM image. MoS\u003csub\u003e2\u003c/sub\u003e is represented in black, HfO\u003csub\u003ex\u003c/sub\u003e in red, and the source (S), drain (D), and back gate (BG) metals are implemented in the form of the potential touching the surface. The top surface, represented in purple, is calculated as empty in the case of single gate simulation and with the potential of the Au in the case of dual gate simulation. The reproduction of such an elevated contact structure in the simulation enables the calculation of the role played by the fringing field.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ee.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eThe \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e values calculated through TCAD modeling for single gate and dual gate configurations in monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs. The on-state is defined at\u003cem\u003e V\u003c/em\u003e\u003csub\u003eds \u003c/sub\u003e= 1 V and \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e = 3 V. Primarily, due to the smaller band gap in bilayer MoS\u003csub\u003e2\u003c/sub\u003e, approximately a threefold increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e was calculated in the same single gate configuration compared to the monolayer. A twofold increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e in the dual gate compared to the single gate is expected due to the twofold gating effect. However, in the case of bilayer, more than a twofold unidentified increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e is observed.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ef.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eVisualized electrical potential of a monolayer MoS\u003csub\u003e2\u003c/sub\u003e FET in HfO\u003csub\u003ex\u003c/sub\u003e and MoS\u003csub\u003e2\u003c/sub\u003e at the on-state (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e = 1 V, \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e = 3 V) for both single gate and dual gate configurations.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eg.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eVisualized electrical potential of a bilayer MoS\u003csub\u003e2\u003c/sub\u003e FET in HfO\u003csub\u003ex\u003c/sub\u003e and MoS\u003csub\u003e2 \u003c/sub\u003eat the on-state for both single gate and dual gate configurations.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eh.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eLine profile along the y-direction of the conduction band (CB) energy and corresponding electron density within monolayer MoS\u003csub\u003e2\u003c/sub\u003e. While the presence of a fringing field-induced barrier near the source electrode is evident, the difference between single and dual gate configurations is not substantial.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ei.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eLine profile along the y-direction of the CB energy and corresponding electron density within the top layer of bilayer MoS\u003csub\u003e2\u003c/sub\u003e. The reduction in the barrier due to the introduction of the dual gate through the fringing field is clearly evident.\u003c/p\u003e","description":"","filename":"image1.png","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/867a57fbbce4ee287da48c68.png"},{"id":60023617,"identity":"34ccabc2-6193-484d-b8b8-674190ff1937","added_by":"auto","created_at":"2024-07-10 16:42:21","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":282170,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eCharacterization of 200-mm scale MoS\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e film\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ea.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eCross-sectional TEM image of a monolayer MoS\u003csub\u003e2\u003c/sub\u003e film.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eb.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eCross-sectional TEM image of a bilayer MoS\u003csub\u003e2\u003c/sub\u003e film.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ec.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eRepresentative Raman spectra of monolayer (green) and bilayer (navy) MoS\u003csub\u003e2\u003c/sub\u003e film. A clear blue shift of the A\u003csub\u003e1g\u003c/sub\u003e peak resulted from the increase in the layer number, leading to the enhanced distance between peaks A\u003csub\u003e1g\u003c/sub\u003e and E\u003csup\u003e1\u003c/sup\u003e\u003csub\u003e2g\u003c/sub\u003e. The peak around 520 cm\u003csup\u003e-1\u003c/sup\u003e on the far right is attributed to the Si peak, and, likewise, an increase in the layer number leads to both broadening and a decrease in intensity.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ed.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eDistribution of E-A peak distances obtained from Raman spectra at 1 cm intervals across a 10 cm x 10 cm area for monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e films. The distinct separation of film thickness is clearly evident on average.\u003c/p\u003e","description":"","filename":"image2.png","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/23d682c7e299ac6dad19bb9c.png"},{"id":60023616,"identity":"2fb3f8d0-9234-4dd4-8bcc-6ef8f9f4a04e","added_by":"auto","created_at":"2024-07-10 16:42:20","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":441873,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eStatistical electrical property analysis of a 200-mm scale FET array.\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ea.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eTransfer curves (\u003cem\u003eσ\u003c/em\u003e\u003csub\u003e\u003cem\u003eSH \u003c/em\u003e\u003c/sub\u003e– \u003cem\u003eV\u003c/em\u003e\u003csub\u003e\u003cem\u003egs\u003c/em\u003e\u003c/sub\u003e) of fabricated monolayer MoS\u003csub\u003e2\u003c/sub\u003e FETs with single-gate (green) and dual-gate (navy) configurations. The transistor's \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e varies from 30 nm to 300 nm, and the channel width varies from 500 nm to 3 mm. To normalize for the various channel dimensions, the y-axis is plotted in terms of conductance. The inset is a photo showing the MoS\u003csub\u003e2\u003c/sub\u003e FET array fabricated on a 200-mm wafer.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eb.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eTransfer curves of bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs with single-gate (orange) and dual-gate (wine) configurations.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ec.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eA graph plotting the \u003cem\u003eI\u003c/em\u003e\u003csub\u003e\u003cem\u003eon\u003c/em\u003e\u003c/sub\u003e values extracted from transfer curves of a monolayer MoS\u003csub\u003e2\u003c/sub\u003e FET array as a function of \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ed.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eThe same graph of a bilayer MoS\u003csub\u003e2\u003c/sub\u003e FET array.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ee.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eA graph plotting the statistically extracted \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eC\u003c/em\u003e\u003c/sub\u003e from the monolayer FET array using the TLM method as a function of the plane carrier density (\u003cem\u003en\u003c/em\u003e\u003csub\u003e\u003cem\u003e2D\u003c/em\u003e\u003c/sub\u003e). The minimum \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eC\u003c/em\u003e\u003c/sub\u003e values for single gate and dual gate configurations are at a similar level.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ef.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eThe same graph for the bilayer FET. A significant drop in \u003cem\u003eR\u003c/em\u003e\u003csub\u003e\u003cem\u003eC\u003c/em\u003e\u003c/sub\u003e is cleanly observed in the dual gate configuration.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eg.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eThe average on-current for both single gate and dual gate configurations in bilayer and monolayer MoS\u003csub\u003e2\u003c/sub\u003e FET arrays with a 30 nm \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e. As predicted in the simulation, a roughly twofold increase in current was observed in the dual gate compared to the single gate in monolayer, and similarly, a more than twofold increase in current was observed in bilayer. As validated by the simulation, it was discovered that this additional increase in current is due to the compensation of the fringing field by the top gate.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eh.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eResistances of single gate and dual gate configurations for monolayer and bilayer FETs with a \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e of 30 nm. \u003cem\u003e2R\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e (red) and channel resistance (\u003cem\u003eR\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e) (blue) extracted through TLM are shown.\u003c/p\u003e","description":"","filename":"image3.png","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/6cc89a04aa896a815c88b19b.png"},{"id":60023611,"identity":"ce212654-2767-44da-b4a8-b327ee5a9187","added_by":"auto","created_at":"2024-07-10 16:42:20","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":314909,"visible":true,"origin":"","legend":"\u003cp\u003e\u003cstrong\u003eBenchmarking of the best dual-gate bilayer MoS\u003c/strong\u003e\u003csub\u003e\u003cstrong\u003e2\u003c/strong\u003e\u003c/sub\u003e\u003cstrong\u003e FET and simulation results of a ring oscillator\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ea.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eTransfer curves (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) of the best bilayer MoS\u003csub\u003e2\u003c/sub\u003e dual-gate FET measured under \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e varying from 0.1 V to 1 V with a step of 0.1 V, plotted in semi-log scale (left) and linear scale (right).\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eb.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eOutput curves (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e) of the same FET plotted in linear scale under \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e varying from 0 V to 4 V with a step of 0.5 V. The observation of linear curves in the sub-saturation regime for all curves suggests the formation of ohmic contacts.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ec.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eA benchmark plot comparing the record-high on-current observed in our device with other studies as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e.\u003csup\u003e9,10,27,28,48,49\u003c/sup\u003e Despite being obtained at lower \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e compared to results using other single crystals, our on-current is the highest. The yellow boxes represent the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e requirements for IRDS HP in the years 2022, 2028, and 2037,\u003csup\u003e5\u003c/sup\u003e respectively. While direct comparison with the advanced Si transistors is not possible due to the broad operating voltage range of our device, it can be demonstrated that the 2D channel allows for sufficiently high current.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ed.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eA plot benchmarking the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of MoS\u003csub\u003e2\u003c/sub\u003e FETs from c based on overdrive voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eod\u003c/sub\u003e = \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e). MoS\u003csub\u003e2\u003c/sub\u003e FETs are represented by star symbols, and Si FETs are represented by pentagon symbols.\u003csup\u003e33\u003c/sup\u003e Notably, the actual \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of our best device are represented by filled red star symbols, while the unfilled red star symbols indicate how the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e change as the EOT, operating voltage, and gate length are adjusted to advanced technology nodes.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ee.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eDevice structure for TCAD simulation. A structure with no overlap between the source/drain electrodes and the gate electrode was assumed. The thickness of the bilayer MoS\u003csub\u003e2\u003c/sub\u003e was set to 1.5 nm, and the thickness of HfO\u003csub\u003ex\u003c/sub\u003e, with an EOT assumed to be 1 nm, was set to 3.1 nm.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ef.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eThe experimentally obtained (red circles) and the calibrated through the Verilog-A MIT virtual source (MVS) model (blue line) transfer curves (left) and output curves (right). The experimental values here were obtained from the transfer curves and output curves in \u003cstrong\u003ea\u003c/strong\u003e and \u003cstrong\u003eb\u003c/strong\u003e, assuming EOT scaling and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e shift. The actual width of the device, 500 nm, was included to convert to the actual current.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eg.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eGate capacitance curves (\u003cem\u003eC\u003c/em\u003e\u003csub\u003egg \u003c/sub\u003e- \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) calculated using TCAD (green triangle) for structure of e and those calculated using the MVS model (yellow line).\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eh.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003eSimulated output signal of a 2D CMOS-based 5-stage ring oscillator at \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e = 1 V. The frequency was measured at 3.56 GHz, and the delay per stage was calculated to be 28.1 ps.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ei.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003ePlot similar to \u003cstrong\u003eh\u003c/strong\u003e obtained at \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e = 2 V. The frequency was extracted as 11.05 GHz, and the delay per stage was 9.1 ps.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003ej.\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp; \u003c/strong\u003ePlot benchmarking the delay per stage of our ring oscillator as a function of \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e. Experimental results are indicated by filled symbols, while simulation results are represented by unfilled symbols.\u003csup\u003e22,33,35,50,51\u003c/sup\u003e\u003c/p\u003e","description":"","filename":"image4.png","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/4e4f6f3d1b064fe0c7eb7e1c.png"},{"id":99935466,"identity":"44aee46b-ff69-4d1a-9130-48e0289733ff","added_by":"auto","created_at":"2026-01-10 08:13:05","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":2464717,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/0c68edf5-8087-4a60-8d5e-e9c58488c172.pdf"},{"id":60024079,"identity":"5906c8b1-b225-4b2b-8b2d-83fe3b086146","added_by":"auto","created_at":"2024-07-10 16:50:20","extension":"docx","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":584259,"visible":true,"origin":"","legend":"","description":"","filename":"ExtendedData.docx","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/9c1885b68f78dba1849a9488.docx"},{"id":60023614,"identity":"e7fd9c42-3c8b-4cf9-9479-c730e6baa1be","added_by":"auto","created_at":"2024-07-10 16:42:20","extension":"pdf","order_by":2,"title":"","display":"","copyAsset":false,"role":"supplement","size":1161647,"visible":true,"origin":"","legend":"","description":"","filename":"SupplementaryInformationfinal.pdf","url":"https://assets-eu.researchsquare.com/files/rs-4632503/v1/353a3f7dd3cddd0b9137ffb2.pdf"}],"financialInterests":"There is \u003cb\u003eNO\u003c/b\u003e Competing Interest.","formattedTitle":"Gate structuring on bilayer transition metal dichalcogenides enables ultrahigh current density","fulltext":[{"header":"Main text","content":"\u003cp\u003eAs silicon (Si) transistors approach their atomic limits for gate length scaling, foundry companies and related academic society are focusing on enhancing the electrostatic control capability of the channel. The strategy now being adopted is structurally positioning the gate to have more contact with a larger portion of the channel.\u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e,\u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e\u003c/sup\u003e This progress has occurred incrementally, evolving from the one-sided planar field-effect transistor (FET) to the three-sided Fin-FET, and ultimately to the four-sided gate-all-around (GAA) FET. Simultaneously, there has been a trend towards minimizing the thickness of the channel to gain additional electrostatic controllability. However, it is widely recognized that structural modifications alone will not be sufficient to sustain Moore's law, as the carrier mobility of silicon is expected to decline significantly below a thickness of 5 nm, resulting in a substantial decrease in current.\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e\u003c/sup\u003e Therefore, to compensate this current reduction, it is essential to adopt a multi-channel configuration.\u003csup\u003e\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e\u003c/sup\u003e However, fabricating contacts and gates for such a structure requires introducing new processes not used in existing technology, which is very challenging, costly, and yields low. Moreover, future advanced technology nodes below the 1 nm scale lack viable solutions to sustain Moore's Law.\u003csup\u003e\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e Consequently, a “monolayer” crystal semiconductor, so called two-dimensional (2D) transition metal dichalcogenide (TMD), has emerged as a compelling alternative for channel materials because its broken bonds-free surface nature offers a means to mitigate the pronounced short-channel effects observed in silicon.\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e,\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e\u003c/sup\u003e 2D TMDs exhibit high gate controllability as their major advantage, with no mobility drop even at channel thicknesses below 1 nm, theoretically enabling operation at gate lengths of 5 nm or less. Also, since single crystal growth of 2D TMDs on amorphous substrates is possible, sequential fabrication of dual gate structures can be easily implemented.\u003csup\u003e\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e\u003c/sup\u003e Similarly, due to the thin thickness, the dual gate structure can achieve effects similar to GAA structures. Nevertheless, until now, predictions that the thin nature of 2D materials would allow sufficient electrostatic control with single gate structures and the challenges of depositing high-quality top gates on 2D materials have hindered dual gate research.\u003csup\u003e\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e As a result, TMD-based single gate transistors have not demonstrated significantly improved on-current (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e) performance compared to Si counterparts. So far, substantially high contact resistance between TMDs and metals has been regarded as the primary hurdle for achieving higher \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e. In reality, a substantial improvement in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e has been observed by simply identifying appropriate contact metals.\u003csup\u003e\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e,\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e\u003c/sup\u003e Consequently, the research community’s focus has been centered around an interface engineering between metals and TMDs.\u003c/p\u003e \u003cp\u003eMeanwhile, in this study, we reveal how significantly the introduction of dual gate structures can improve transistor performance with both simulations and experiments. Our circuit simulations demonstrate that with extreme gate length scaling in dual gate structures, performance comparable to Si 3 nm node technology fabricated using GAA processes can be achieved. By adopting planar dual gate FETs instead of the highly complex GAAFETs, similar performance can be achieved. This allows for monolithic 3D integration on arbitrary substrates at low temperatures, creating area gains and paving the way to sustain Moore's Law even at advanced nodes below 1 nm.\u003csup\u003e\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e\u003c/sup\u003e First, we discovered through simulations an important factor that has been overlooked in 2D TMD-based transistors: the potential barrier caused by the fringing field from the elevated top contact electrodes. We confirmed that the influence of the fringing field is greater in bilayers than in monolayers and that applying a dual gate can partially offset this potential barrier. As a result, introducing a dual gate for bilayer TMDs is expected to increase the current by approximately five times compared to single gate structures. To verify this sudden boost in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e through statistical experiments, we fabricated FET arrays on a 200-mm wafer-scale monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e films and observed the improvement in electrical performance for dual gate structures compared to single gate structures. Experimentally, it was confirmed that the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of dual gate structures increased by approximately three times compared to single gate structures. Through the extraction of contact resistance (\u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e) using the statistical transfer length method (TLM), we confirmed that the reduction of the barrier near the contact electrode due to the introduction of dual gates is particularly pronounced in bilayer MoS\u003csub\u003e2\u003c/sub\u003e, aligning perfectly with our simulation results. Remarkably, utilizing polycrystalline MoS\u003csub\u003e2\u003c/sub\u003e and conventional Au contact electrodes, we achieved an astonishing \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of 1.55 mA/µm due to the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e boosting effect from the bilayer, dual-gate configuration. Furthermore, our FET utilizes high-k dielectrics on both top and bottom, effectively lowering the operating voltage compared to conventional TMD-based devices using global back gates, bringing it closer to the industrial Si transistors. Based on this, we conducted additional technology computer-aided design (TCAD) and simulation program with integrated circuit emphasis (SPICE) simulations and confirmed that bilayer MoS\u003csub\u003e2\u003c/sub\u003e dual gate transistors can achieve comparable \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e compared to Si transistors at the 3 nm node, especially for gate lengths below 10 nm. We also confirmed the potential for our current device to operate normally without significant performance degradation compared to a planar Si circuit at the 45 nm node, which has the most similar geometry with our FET.\u003c/p\u003e \u003cp\u003eAs gate lengths for 2D TMD-based FETs further decrease, the contacted poly pitch (CPP) also decreases, potentially leading to area gain. This aspect could offer advantages over Si GAAFETs in terms of performance, power, and area (PPA). One of the greatest advantages of 2D materials is not only their extremely thin thickness but also the ability to grow single crystals on amorphous substrates, enabling their use in monolithic 3D integration. Therefore, we have demonstrated for the first time in this study that creating complementary FETs (CFETs) based on dual gate structures, rather than GAAFET processes which have higher fabrication complexities, and integrating these layers in a stacked configuration, may offer advantages when considering costs and performance.\u003csup\u003e\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e,\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e\u003c/sup\u003e\u003c/p\u003e "},{"header":"On-current and electrical potential in single gate and dual gate MoS 2 FETs as predicted by TCAD simulations","content":"\u003cp\u003eUnlike Si transistors, 2D TMDs lack heavy doping technology so far, necessitating direct metal contact to the undoped channel area. This contact takes the form of an elevated top metal electrode. In such a case, a relatively large fringing field can be expected between the metal and the channel near the metal. Nevertheless, until now, only considered as parasitic capacitance, no one has taken into account its impact on the current in the channel.\u003csup\u003e\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e\u003c/sup\u003e On the other hand, the electrical band gap of the most common TMD, monolayer MoS\u003csub\u003e2\u003c/sub\u003e, is relatively large, which is advantageous for leakage suppression.\u003csup\u003e\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e,\u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e\u003c/sup\u003e However, it poses challenges in obtaining sufficient carrier mobility, and direct metal contact induces a large Schottky barrier height, leading to significant contact resistance. It is because the smaller band gap of the bilayer induces a lower Schottky barrier height, resulting in superior contact characteristics compared to monolayers.\u003csup\u003e\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e\u003c/sup\u003e Hence, bilayer MoS\u003csub\u003e2\u003c/sub\u003e could offer more physical space to transport charge carriers in response to the gate bias, resulting in the higher carrier mobility.\u003csup\u003e\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e\u003c/sup\u003e Therefore, to enhance the performance of the FET further, we opted for a straightforward combination of bilayer MoS\u003csub\u003e2\u003c/sub\u003e and a dual-gate configuration.\u003csup\u003e\u003cspan additionalcitationids=\"CR18\" citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e–\u003cspan citationid=\"CR19\" class=\"CitationRef\"\u003e19\u003c/span\u003e\u003c/sup\u003e In this study, we systematically analyzed the impact of the fringing field, a factor that has always been present in 2D FETs but has been overlooked so far.\u003c/p\u003e\u003cp\u003eDue to the characteristics of freestanding 2D materials, creating a back gate structure is relatively straightforward. Then, by creating a top gate, a typical MoS\u003csub\u003e2\u003c/sub\u003e dual gate FET is easily fabricated, as shown in the structure depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ea. For high performance, it is essential that the equivalent oxide thickness (EOT) of the top and bottom dielectrics are balanced. However, forming a high-quality top gate dielectric layer on a 2D material is challenging due to the noble surface, as widely acknowledged.\u003csup\u003e\u003cspan citationid=\"CR20\" class=\"CitationRef\"\u003e20\u003c/span\u003e\u003c/sup\u003e We utilized a low-temperature ALD interlayer deposition method known as the 'nanofog' technique to deposit the high quality top gate dielectric.\u003csup\u003e\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e\u003c/sup\u003e Furthermore, to align our simulations with our experimental results, we avoided using materials that might react with the 2D material or generate a native oxide layer easily. Therefore, we employed gold (Au) for both the source-drain and gate electrodes. Representative dual gate device's top view scanning electron microscopy (SEM) image and cross-section transmission electron microscopy (TEM) image are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eb and \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ec, respectively.\u003c/p\u003e\u003cp\u003e \u003c/p\u003e\u003cp\u003eBased on the real device geometry, we conducted accurate TCAD simulation modeling as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ed. In previous TCAD simulations based on 2D materials, the actual shape of the electrodes was not considered accurately.\u003csup\u003e\u003cspan additionalcitationids=\"CR22\" citationid=\"CR21\" class=\"CitationRef\"\u003e21\u003c/span\u003e–\u003cspan citationid=\"CR23\" class=\"CitationRef\"\u003e23\u003c/span\u003e\u003c/sup\u003e Also, they were limited by using silicon-based tools to simulate 2D materials, which only considered changes in thickness and basic properties, leading to significant inaccuracies when compared to the experimental results. To confirm the characteristics of bilayer MoS\u003csub\u003e2\u003c/sub\u003e through simulation, we included the van der Waals gap between the upper and lower MoS\u003csub\u003e2\u003c/sub\u003e layers, which is the most significant difference from Si. Then we designed the simulation to match the known properties of bilayer MoS\u003csub\u003e2\u003c/sub\u003e, including band gap and dielectric constant. Based on this modeling, we conducted TCAD simulations for both monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e for both single gate and dual gate FET configurations. Initially, we defined the on-state for all cases with a gate-source voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) of 3 V and a drain-source voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e) of 1 V. Subsequently, we extracted the corresponding currents for each case as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ee. For the monolayer, the introduction of the dual gate led to a doubling of the gate capacitance. Consequently, the electron density within the channel increased by approximately two-fold, being expected to result in an increase in current of about 2 times. However, in the case of the bilayer, the dual-gate FET exhibited a substantial increase in current, approximately five times higher compared to the single-gate configuration. This is highlighted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ee, where the additional increase in current, denoted by the 'question mark', indicates a notable contribution beyond the carrier density increase upon the application of dual gates in bilayer MoS\u003csub\u003e2\u003c/sub\u003e. As evident from the calculated transfer curves (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) in Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e, there is no apparent impact due to the negative shift in the threshold voltage. Instead, the suppression of the short-channel effect in the dual-gate configuration leads to an improvement in subthreshold characteristics. In Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ef and \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eg, we illustrated the simulation results of the electrostatic potential within monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs at on-state, respectively. In the enlarged view of the MoS\u003csub\u003e2\u003c/sub\u003e layer vicinity, as depicted in Supplementary Information Fig. \u003cspan refid=\"MOESM1\" class=\"InternalRef\"\u003eS1\u003c/span\u003e, differences in modeling between monolayer and bilayer can be observed. In both cases, we observe a significant potential drop around the source electrode in the single gate configuration, and this effect is mitigated when the dual gate is applied. The line profiles of the energy of conduction band edge in the x-direction for monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e, along with the corresponding electron density, are plotted in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eh and \u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ei, respectively. For bilayer MoS\u003csub\u003e2\u003c/sub\u003e, considering that the top layer in direct contact with the top metal contact serves as the main conduction layer, we computed the line profile specifically for this layer. (For potential profile of the bottom layer, see Fig. S2) Under all conditions, pronounced energy barriers are observed around the source electrode, leading to a notable reduction in charge density in this region. This barrier is directly attributed to the fringing field from the elevated contact. We demonstrated the creation of a low fringing field structure, suppressing the fringing field and consequently lowering the barrier. Therefore, as shown in Fig. S3, under the low fringing field conditions for bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs, a higher on-current can be obtained. Here, a significant distinction between monolayer and bilayer is apparent. In the case of the monolayer, there is minimal change in the barrier height even after the introduction of dual gates. However, for the bilayer, the dual-gate introduction noticeably compensates for this fringing field. The reason why the fringing field is more effectively compensated in the bilayer MoS\u003csub\u003e2\u003c/sub\u003e with dual gate compared to monolayer can be explained as follows: In monolayer MoS\u003csub\u003e2\u003c/sub\u003e, it is already significantly influenced by the back gate, whereas the main conduction layer in bilayer is the top layer, so lower layer screens out some of the effects of the back gate. At the same time, the top layer is more directly affected by the fringing field from the top contact. As a result, bilayer MoS\u003csub\u003e2\u003c/sub\u003e FET is expected to exhibit more than a 2-fold increase in additional \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e due to the compensation of the fringing field with the introduction of the dual gate. We further theoretically verified it from the capacitance model described in Fig. S4. As well as on-state characteristics, the introduction of dual gates also significantly improved subthreshold characteristics such as subthreshold swing (SS) and leakage current. (Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003e)\u003c/p\u003e"},{"header":"200-mm wafer scale growth of monolayer and bilayer MoS","content":"\u003cp\u003eOur primary focus has been on achieving the uniform growth of bilayer TMDs across 200-mm wafers, a task not previously demonstrated due to the challenges associated with layer-by-layer growth directly on Si wafers.\u003csup\u003e\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e,\u003cspan citationid=\"CR25\" class=\"CitationRef\"\u003e25\u003c/span\u003e\u003c/sup\u003e Here, we introduced an additive during growth to enhance adatom diffusion. As a result, we could successfully regulate nucleation and promote lateral growth, achieving uniform growth even with bilayer thickness. As a result of these efforts, we have successfully achieved bilayer-dominated MoS\u003csub\u003e2\u003c/sub\u003e growth across 200-mm wafers. This accomplishment has enabled us to establish wafer-scale arrays of bilayer transistors with dual gating capabilities.\u003c/p\u003e\u003cp\u003eWhile the growth of uniform monolayer films has been relatively well-established in previous research, there have been only very limited reports on the growth of uniform bilayer films.\u003csup\u003e\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e\u003c/sup\u003e Therefore, our focus was on adjusting the average thickness to match bilayer thickness for statistical analysis. To achieve uniform bilayer growth, it is necessary to suppress the nucleation of adlayers until the next layer growth is completed. We were able to obtain relatively uniform monolayer and bilayer films in 200-mm wafer scale through the utilization of the metal-organic chemical vapor deposition (MOCVD) method and use of proper growth additives. (See Methods for details) Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ea and \u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003eb respectively display cross-sectional TEM images of the grown monolayer and bilayer. In Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ec, characteristic Raman peaks of monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e, including E\u003csup\u003e\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e\u003c/sup\u003e\u003csub\u003e2g\u003c/sub\u003e and A\u003csub\u003e1g\u003c/sub\u003e peaks, along with the Si substrate peak near 520 cm\u003csup\u003e− 1\u003c/sup\u003e, are presented. The intensity of the A peak relative to the Si peak is significantly higher in the bilayer than in the monolayer. Moreover, the distance between the E-A peaks directly related to the layer number is precisely in line with the values reported in the literature, measuring 19.8 cm\u003csup\u003e− 1\u003c/sup\u003e for the monolayer and 21.9 cm\u003csup\u003e− 1\u003c/sup\u003e for the bilayer.\u003csup\u003e\u003cspan citationid=\"CR26\" class=\"CitationRef\"\u003e26\u003c/span\u003e\u003c/sup\u003e Of course, it would be challenging to claim that the entire film is strictly monolayer or bilayer, due to the presence of adlayer patches. However, through statistical Raman analysis, we can track the average number of layers. In Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003ed, the distribution of the analyzed E-A peak distances from 100 Raman spectra within a 10 cm by 10 cm area of as-grown MoS\u003csub\u003e2\u003c/sub\u003e films is plotted. Also, as evident from the Raman mapping in Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig2\" class=\"InternalRef\"\u003e2\u003c/span\u003e, it can be confirmed that a generally uniform monolayer and bilayer were fabricated. Therefore, we can statistically consider the two MoS\u003csub\u003e2\u003c/sub\u003e films as predominantly monolayer and bilayer, respectively.\u003c/p\u003e"},{"header":"Statistical assessment of monolayer and bilayer MoS FETs with single and dual gate configurations","content":"\u003cp\u003eBased on the growth of wafer-scale monolayer and bilayer films, we succeeded fabricating FET arrays on 200-mm wafers. (Inset of Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ea) The detailed fabrication process is described in Fig. S5 and the \u003cspan refid=\"Sec5\" class=\"InternalRef\"\u003eMethods\u003c/span\u003e section. (For cross-section TEM images of the devices see Fig. S6) To ensure accurate analysis on difference between single gate and dual gate configurations, we measured the same device both before and after the formation of the top gate electrode. In this study, the analysis of the top gate-only configuration is not of significant relevance since the field from the top gate has a limited impact on lowering the contact barrier, while back gate electrostatically dopes contact region at the on-state. This can be observed from the statistical analysis of long-channel devices (\u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e \u0026gt; 500 nm) fabricated by only photolithography shown in Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003e. The measurements of the top-gate-only configuration reveal that it exhibits performance that is more than an order of magnitude lower than that of the back gate, due to the lower quality of top-gate dielectric compared with pre-deposited back-gate dielectric as well as lack of contact gating.\u003c/p\u003e\u003cp\u003e \u003c/p\u003e\u003cp\u003eMeanwhile, the transfer curves (\u003cem\u003eσ\u003c/em\u003e\u003csub\u003eSH\u003c/sub\u003e \u003cem\u003e– V\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) of hundreds of monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs are plotted in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ea and \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eb, respectively. The channel length (\u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e) here was varied from 30 nm to 300 nm. In order to normalize the current with channel length and width of the various FETs, the y-axis was represented in sheet conductance (\u003cem\u003eσ\u003c/em\u003e\u003csub\u003eSH\u003c/sub\u003e). The results indicate that both SS and \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e are superior in the dual gate configuration compared to the single gate. Also, based on this, the change in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e with respect to \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e was plotted for monolayer and bilayer as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ec and \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ed, respectively. A huge increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of dual-gate FET compared to single-gate FET was observed in all \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e ranges for dual gate FET. It is quite remarkable that the MoS\u003csub\u003e2\u003c/sub\u003e film, despite being polycrystalline, exhibits an average \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of around 700 µA/µm at \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e of 30 nm, simply with the combination of bilayer and dual gates. Interestingly, in bilayers, the increase in \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e with dual gate compared to single gate is consistent regardless of \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e, whereas in monolayers, the increase becomes more pronounced as \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e increases. In previous simulation results, the difference of potential barrier height between single and dual gate in monolayers is not significant. Consequently, in the contact-dominant regime of short channels, the difference is around two-fold. However, in long channels, which enter the channel-dominant regime, changes in the channel that were not apparent in simulations seem to be observed. To investigate this further, we conducted TLM analysis for each case using the transfer curves for each \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e, as illustrated in Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. Here, \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e in each transfer curve was converted to overdrive voltage (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eod\u003c/sub\u003e), which was further transformed into carrier density using the capacitance values extracted in the various metal-insulator-metal (MIM) structures, as shown in Fig. S7. As a result, it is able to plot \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e as a function of planar carrier density (\u003cem\u003en\u003c/em\u003e\u003csub\u003e2D\u003c/sub\u003e), as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ee and \u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ef for monolayer and bilayer, respectively. In both cases, the dual gate has a roughly two-fold higher capacitance than the single gate at the same \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e, resulting in a broader range of \u003cem\u003en\u003c/em\u003e\u003csub\u003e2D\u003c/sub\u003e for the dual gate. Interestingly, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ee, the lowest \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e in the monolayer is comparable between the single gate and dual gate, measuring around 4.1 kΩ∙µm and 4.6 kΩ∙µm, respectively. This aligns precisely with the simulation results in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003eh, where the difference in charge injection barrier due to the fringing field was minimal. On the other hand, examining Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ef, in the bilayer, the \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e shows a value of 4.3 kΩ∙µm under the single gate, which is not significantly different from the monolayer. However, with the introduction of the dual gate, it drastically improves to 1.3 kΩ∙µm, aligning precisely with the reduced charge injection barrier observed in the simulation in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ej. As summarized in Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eg, the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of dual gate monolayer MoS\u003csub\u003e2\u003c/sub\u003e FET showed an average increase of 2 times compared to a single gate, while in bilayer MoS\u003csub\u003e2\u003c/sub\u003e FET, it shows an increase of around 3.6 times. Surprisingly, this also matches exactly with the predictions made in Fig.\u0026nbsp;\u003cspan refid=\"Fig1\" class=\"InternalRef\"\u003e1\u003c/span\u003ee. Now, we can attribute the additional increase in the bilayer to the compensation of the fringing field coming from the top gate. In Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003eh, we plotted the proportion of \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e and channel resistance (\u003cem\u003eR\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e) in the total resistance based on the \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e and sheet resistance (\u003cem\u003eR\u003c/em\u003e\u003csub\u003esh\u003c/sub\u003e) extracted from TLM in Extended Data Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003e. In the shortest FETs with \u003cem\u003eL\u003c/em\u003e\u003csub\u003ech\u003c/sub\u003e of 30 nm, the current proportion of \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e is significant, and the twofold decrease in resistance in monolayers can be attributed to a rapid decrease in \u003cem\u003eR\u003c/em\u003e\u003csub\u003esh\u003c/sub\u003e while \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e remains relatively constant. This holds true for bilayers as well, where not only \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e but also the sharp decrease in \u003cem\u003eR\u003c/em\u003e\u003csub\u003esh\u003c/sub\u003e results in a substantial reduction in overall resistance. The crucial message here is that even with the thin thickness of monolayers, it is challenging to achieve full accumulation throughout the entire channel with only one-sided gating. The use of dual gates is essential to fully utilize the entire channel. Therefore, it implies that the carrier mobility of the channel can vary depending on the gate, even for the same material. This can be observed in Fig. S8, which compares the TLM mobility, excluding contact effect, extracted using the TLM method. Therefore, we have validated the fact that, even with an extremely thin channel material, leveraging the dual gate structure is advantageous.\u003c/p\u003e"},{"header":"Benchmarking Ion of dual gate bilayer MoS2 FET","content":"\u003cp\u003eTo assess the maximum current level that MoS\u003csub\u003e2\u003c/sub\u003e can handle, we selected the best device of bilayer MoS\u003csub\u003e2\u003c/sub\u003e with dual gate configuration from the previously measured FETs and increased the \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e range up to + 4 V. Transfer curves (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e) of the best device plotted in semi-log and linear scale are plotted in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ea. The linear shape in the output curves (\u003cem\u003eI\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e – \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e) at low \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e regime in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eb demonstrates that the contact is ohmic, contributing to the record-high \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e of 1.55 mA/µm. We benchmarked the obtained \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e as a function of \u003cspan type=\"ItalicUnderline\" class=\"ItalicUnderline\" name=\"Emphasis\"\u003eV\u003c/span\u003e\u003csub\u003eds\u003c/sub\u003e from the device in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ec among n-type 2D FETs. Even with a simple structural change, we achieved higher \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e compared to single crystal-based FETs. Of course, while direct comparisons with commercially available silicon-based components are not reasonable, our FET outperforms the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e requirements suggested by IEEE International Roadmap for Devices and Systems (IRDS) 2022 roadmap,\u003csup\u003e\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e\u003c/sup\u003e being leveraged from the maximum potential of bilayer MoS\u003csub\u003e2\u003c/sub\u003e by introducing dual gate. It is significant that these results were obtained at the lower source-drain bias (\u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e) and \u003cem\u003eV\u003c/em\u003e\u003csub\u003eod\u003c/sub\u003e among the high on-current 2D semiconductor-based FETs.\u003csup\u003e\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e,\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e,\u003cspan citationid=\"CR24\" class=\"CitationRef\"\u003e24\u003c/span\u003e,\u003cspan additionalcitationids=\"CR28 CR29 CR30\" citationid=\"CR27\" class=\"CitationRef\"\u003e27\u003c/span\u003e–\u003cspan citationid=\"CR31\" class=\"CitationRef\"\u003e31\u003c/span\u003e\u003c/sup\u003e (Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ec and \u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ed)\u003c/p\u003e\u003cp\u003eMany studies have shown that low \u003cem\u003eV\u003c/em\u003e\u003csub\u003eds\u003c/sub\u003e results in high on-current, suggesting the potential to outperform silicon. However, these figures mostly come from fundamental research using global back gates, and thus are measured at high \u003cem\u003eV\u003c/em\u003e\u003csub\u003eod\u003c/sub\u003e, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ed. Except for a recent study, our work shows high \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e at an operation voltage most similar to silicon, using local gates. This allows for a more accurate comparison with silicon. To address this, we comparatively examined the performance with a 45 nm node Si transistor that has a relatively similar gate length with our FET. The 45 nm node transistor typically has a gate length ranging from approximately 30 nm to 40 nm and uses a \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e of 1 V,\u003csup\u003e\u003cspan citationid=\"CR32\" class=\"CitationRef\"\u003e32\u003c/span\u003e,\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e\u003c/sup\u003e which are similar to our device. These factors also explain why only a few 2D FET based AC circuits have been reported so far.\u003csup\u003e\u003cspan citationid=\"CR22\" class=\"CitationRef\"\u003e22\u003c/span\u003e,\u003cspan citationid=\"CR34\" class=\"CitationRef\"\u003e34\u003c/span\u003e,\u003cspan citationid=\"CR35\" class=\"CitationRef\"\u003e35\u003c/span\u003e\u003c/sup\u003e To enable a relatively fair comparison under similar conditions, we scaled \u003cem\u003eV\u003c/em\u003e\u003csub\u003egs\u003c/sub\u003e by our device's EOT to 1 nm from 3.3 nm and applied an arbitrary shift to align the \u003cem\u003eV\u003c/em\u003e\u003csub\u003eth\u003c/sub\u003e of the two devices as shown in Fig. S9. Here, with an \u003cem\u003eI\u003c/em\u003e\u003csub\u003eoff\u003c/sub\u003e of 100 nA/µm and \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e of 1 V, the \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e is 690 µA/µm, which is about half the level of the Si 45 nm node FET.\u003csup\u003e\u003cspan citationid=\"CR32\" class=\"CitationRef\"\u003e32\u003c/span\u003e,\u003cspan citationid=\"CR33\" class=\"CitationRef\"\u003e33\u003c/span\u003e\u003c/sup\u003e Considering the difference in mobility between bulk Si and our MoS\u003csub\u003e2\u003c/sub\u003e, the results can be regarded as quite comparable. We can calibrate the TCAD model of Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ee with our experimentally based I-V curve, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ef. Conversely, we can use the TCAD model to simulate \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e by reducing the gate length. As shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ed, to compare with the Si 3 nm node, reducing \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e to 0.7 V and the gate length to 12 nm—the limit for Si gate length—results in an \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e increase to 1.27 mA/µm. Further reducing the gate length to 5 nm, the limit for bilayer MoS\u003csub\u003e2\u003c/sub\u003e, increases Ion to 2.08 mA/µm. The Si transistor in this scenario would likely be in a multi-channel configuration, potentially boosting the on-current further. Nevertheless, due to the large capacitance disadvantage inherent in the GAAFET structure, the AC circuit performance is expected to be comparable to that of planar dual gate MoS\u003csub\u003e2\u003c/sub\u003e.\u003c/p\u003e\u003cp\u003eTo indirectly demonstrate this, we conducted a simulation comparing the circuit performance of our device with that of a 45 nm node Si planar transistor, which has the most similar geometry to our device. Scaling our device to an advanced node involves making significant assumptions and may introduce inaccuracies, which is why we chose to compare it with the 45 nm node Si planar transistor instead. Nonetheless, the following assumptions are still necessary for comparison between our 2D FET and a 45 nm node Si FET. First, assumptions about the performance of p-type metal-oxide-semiconductors (PMOS) are needed. We simply assumed PMOS by symmetrizing the MoS\u003csub\u003e2\u003c/sub\u003e n-type metal-oxide-semiconductors (NMOS). Given that WSe\u003csub\u003e2\u003c/sub\u003e, which is an emerging 2D semiconductor as a PMOS candidate, has higher mobility and \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e, we believe this approach is feasible in the future.\u003csup\u003e\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e,\u003cspan citationid=\"CR36\" class=\"CitationRef\"\u003e36\u003c/span\u003e\u003c/sup\u003e Second, to achieve fair circuit performance, it is assumed that there is no vertical overlap between the source/drain electrodes and the gate electrode. In the actual structure, contact doping is achieved using electrostatic gating of the contacts, while this structure results in excessively high gate capacitance, which leads to significant RC delay in the circuit. Instead, gate-dependent contact resistance was separately incorporated into the model using the experimental values from Fig.\u0026nbsp;\u003cspan refid=\"Fig3\" class=\"InternalRef\"\u003e3\u003c/span\u003ef. To create a process design kit (PDK), which is crucial for SPICE circuit simulation, compact modeling of the 2D FET is necessary. Among these, the I-V curve can be calibrated using the experimental data from our Fig. S9 to fit the appropriate model. After applying a channel width of 500 nm and using the Verilog-A MIT Virtual Source model (MVS) to calibrate the transfer curves and output curves, we confirmed that the results fit well, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ef.\u003csup\u003e\u003cspan citationid=\"CR37\" class=\"CitationRef\"\u003e37\u003c/span\u003e,\u003cspan citationid=\"CR38\" class=\"CitationRef\"\u003e38\u003c/span\u003e\u003c/sup\u003e However, as previously mentioned, we assumed a structure without overlap between source/drain and gate metal to optimize circuit performance, so we cannot use experimental C-V curve for circuit simulation. Therefore, based on the device structure in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ee, we extracted the gate capacitance curve (\u003cem\u003eC\u003c/em\u003e\u003csub\u003egg\u003c/sub\u003e - \u003cem\u003eV\u003c/em\u003e\u003csub\u003eg\u003c/sub\u003e) through TCAD simulation, and the results are shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eg. These results are very similar to the curve calculated using the MVS model, indicating their excellent reliability. Based on these results, we were able to proceed with compact modeling of our 2D FET and simulate a 5-stage ring oscillator. The frequency is 3.56 GHz and 11.05 GHz, corresponding to a delay per stage of 28.1 and 9.1 ps for \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e of 1 V and 2 V, as shown in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003eh and i, respectively, which is comparable to Si 45 nm node's performance (6 ps).\u003csup\u003e\u003cspan citationid=\"CR32\" class=\"CitationRef\"\u003e32\u003c/span\u003e\u003c/sup\u003e (Fig. S10 and Fig. S11 for gate capacitance and ring oscillator performance of the FETs with overlapped gate, respectively) As we benchmarked our simulated ring oscillator delay in Fig.\u0026nbsp;\u003cspan refid=\"Fig4\" class=\"InternalRef\"\u003e4\u003c/span\u003ej, there is still a significant difference between the experimentally obtained performance and the calculated performance. This is because the technology based on 2D materials is still underdeveloped, making it challenging to achieve balanced CMOS fabrication, and the lack of doping technology leads to the absence of spacer processes, resulting in high parasitic capacitance that limits circuit performance. From a device perspective, it is also necessary to engineer the interface with the dielectric and reduce contact resistance. This will not only improve performance but also ensure uniformity and reliability. Hence, for now, since the alternative target for 2D semiconductors is Si nanosheets with channel thicknesses of 4 nm or less, directly surpassing bulk Si planar transistors may not be feasible. Nevertheless, our computational objective was to demonstrate that 2D FETs can achieve performance levels similar to silicon as much as possible.\u003c/p\u003e"},{"header":"Conclusions","content":"\u003cp\u003eThrough this study, we confirmed that the fringing field arising from the elevated contact in 2D FETs forms a significant barrier around the source, hindering the charge injection in 2D semiconductors. In particular, for bilayer MoS\u003csub\u003e2\u003c/sub\u003e, the introduction of a dual-gate structure compensates for this fringing field to some extent, leading to a significant boost in current compared to the single gate. This phenomenon was confirmed through simulations to be due to the two layers of bilayer MoS\u003csub\u003e2\u003c/sub\u003e being separated, unlike in Si. The resulting current boost was observed in both simulation and experiment. Furthermore, we demonstrated through TLM methods that the introduction of dual gates not only reduces the charge injection barrier but also increases channel mobility by opening additional electrical paths, even in extremely thin channels. An important point is that, unlike results analyzed from individual unit devices, the reliability of our results is enhanced by statistically comparing hundreds of devices processed through the same 200-mm wafer fabrication process. In essence, by demonstrating the benefits brought about by the introduction of dual gates, we have justified the adoption of GAA structures in 2D FETs, similar to Si. Lastly, our best device, despite utilizing polycrystalline MoS\u003csub\u003e2\u003c/sub\u003e, achieved a DC \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e record of 1.55 mA/\u0026micro;m. We conducted simulations to evaluate the performance of our FET when applied to actual planar FETs, as our device achieved high \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e while operating at industrially viable voltage levels. Using TCAD, we fitted our experimentally obtained transfer curves and calculated the capacitance. Based on this, we performed compact modeling to implement a 5-stage ring oscillator. The delay per stage was 9.1 ps at \u003cem\u003eV\u003c/em\u003e\u003csub\u003edd\u003c/sub\u003e of 2 V, which is comparable to that of the 45 nm node Si with similar dimensions. Moreover, in gate lengths below a few nanometers, where there is no degradation in mobility in an extremely thin channel, our device is expected to have a clear advantage over Si nanosheet transistors.\u003c/p\u003e"},{"header":"Methods","content":"\u003cdiv id=\"Sec6\" class=\"Section2\"\u003e \u003ch2\u003eTCAD Simulation\u003c/h2\u003e \u003cp\u003eWe use the multi-subband Boltzmann transport equation (MSBTE) solver, implemented in our in-house simulator. It calculates the Schr\u0026ouml;dinger equation perpendicular to the transport direction and one-dimensional MSBTE for each subband. Mode decomposition is used to reduce the computational burden at the realistic device scale, and periodic boundary condition is applied for the width direction. Layer-dependence effective mass and bandgap are considered as in Table\u0026nbsp;1, and a multi-layer model considering the van der Waals (vdW) gap is used to accurately reflect the electrostatic effects depending on the device structure. DFT results show that the MoS\u003csub\u003e2\u003c/sub\u003e layer has a high dielectric constant, while the vdW layer has a low dielectric constant.\u003csup\u003e\u003cspan citationid=\"CR39\" class=\"CitationRef\"\u003e39\u003c/span\u003e,\u003cspan citationid=\"CR40\" class=\"CitationRef\"\u003e40\u003c/span\u003e\u003c/sup\u003e This causes most of the potential drop to occur in the vdW layer, resulting in a significant difference in the electrical operation of monolayer and multilayer devices. The MSBTE solver is a semi-classical transport equation that cannot originally consider tunneling effects. However, the tunneling current is accurately included as nonlocal intravalley interaction based on the WKB tunneling model.\u003csup\u003e\u003cspan citationid=\"CR41\" class=\"CitationRef\"\u003e41\u003c/span\u003e\u003c/sup\u003e This allows for the accurate consideration of the source-induced injection barrier. In bilayer modeling, another challenge is calculating the current path correctly. In a few-layer top-contact device, the main current path is the top layer, as carriers with small electric field are rarely injected from the source to the bottom layer. However, the MSBTE solver considers the 1D transport equation and imposes the injection boundary condition on the sides, leading to the misleading conclusion that most of the current path is formed in the bottom layer, which is less susceptible to the source fringe field effect. To mimic the low current injection to the bottom layer by tunneling through the vdW layer, a thin tunneling layer is added to the bottom layer as in Fig. S2. Through these detailed modeling efforts, the origin of the substantial gain of \u003cem\u003eI\u003c/em\u003e\u003csub\u003eon\u003c/sub\u003e and decrease of the \u003cem\u003eR\u003c/em\u003e\u003csub\u003eC\u003c/sub\u003e when using dual-gate in a bilayer device is clearly identified.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003eMOCVD of monolayer and bilayer MoS\u003csub\u003e2\u003c/sub\u003e\u003c/h2\u003e \u003cp\u003eThe growth of 200 mm scale monolayer MoS\u003csub\u003e2\u003c/sub\u003e was conducted under the same conditions as in our previous studies.\u003csup\u003e\u003cspan additionalcitationids=\"CR43\" citationid=\"CR42\" class=\"CitationRef\"\u003e42\u003c/span\u003e\u0026ndash;\u003cspan citationid=\"CR44\" class=\"CitationRef\"\u003e44\u003c/span\u003e\u003c/sup\u003e We used a shower-head-type cold-wall MOCVD reactor for the growth of MoS\u003csub\u003e2\u003c/sub\u003e, utilizing Mo(CO)\u003csub\u003e6\u003c/sub\u003e as the Mo precursor and (C\u003csub\u003e2\u003c/sub\u003eH\u003csub\u003e5\u003c/sub\u003e)\u003csub\u003e2\u003c/sub\u003eS\u003csub\u003e2\u003c/sub\u003e as the S precursor. The flow rates of the precursors were 0.001 sccm for Mo(CO)\u003csub\u003e6\u003c/sub\u003e, 0.007 sccm for (C\u003csub\u003e2\u003c/sub\u003eH\u003csub\u003e5\u003c/sub\u003e)\u003csub\u003e2\u003c/sub\u003eS\u003csub\u003e2\u003c/sub\u003e, and 100 sccm for H\u003csub\u003e2\u003c/sub\u003e, all of which were precisely regulated by individual mass-flow controllers and electronic pressure controllers. The chamber pressure and wafer temperature were maintained at 5.0 torr and 600 \u003csup\u003eo\u003c/sup\u003eC, respectively, during the growth process. We used KI as an additive to improve adatom diffusion, placing it upstream in the reactor. Growth time was controlled from 12 minutes to 1 hour to control the layer number.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec8\" class=\"Section2\"\u003e \u003ch2\u003eFabrication of 200-mm wafer scale FETs\u003c/h2\u003e \u003cp\u003eFirst, we started device fabrication with a 200 mm Si wafer and create a 100 nm SiO\u003csub\u003e2\u003c/sub\u003e layer through thermal oxidation. Next, we pattern the bottom gate electrode using photolithography with a stepper. At this stage, the negative process using the image reversal photoresist AZ5214 is utilized, followed by a lift-off process. For the bottom gate metal, 5 nm of Ti and 20 nm of Au are used. The creation of the bottom gate structure is completed by depositing 10 nm of HfO\u003csub\u003ex\u003c/sub\u003e using atomic layer deposition (ALD). Next a MoS\u003csub\u003e2\u003c/sub\u003e film grown by MOCVD is transferred onto the substrate. As in our previous study,\u003csup\u003e\u003cspan citationid=\"CR43\" class=\"CitationRef\"\u003e43\u003c/span\u003e\u003c/sup\u003e a semi-automatic transfer stage is utilized at this stage. After that, another photolithography process is carried out to pattern the active channel area of MoS\u003csub\u003e2\u003c/sub\u003e. The exposed areas of MoS\u003csub\u003e2\u003c/sub\u003e are etched using O\u003csub\u003e2\u003c/sub\u003e reactive ion etching (RIE) or a plasma asher. Next, we patterned fine source/drain electrodes for the short-channel device using e-beam lithography. In this case, a 495k PMMA A2 / 950k PMMA A2 bilayer is utilized as an e-beam resist for smooth lift-off. In this case, Au 20 nm is used as the contact metal. Another round photolithography, metal deposition, and lift-off are carried out to create metal leads connecting the pads for subsequent measurements. It is important to perform e-beam lithography first in this process, as PR residue can significantly degrade contact resistance of resulting FETs. To facilitate the deposition of dielectric on top of the MoS\u003csub\u003e2\u003c/sub\u003e for the fabrication of the top gate, an interlayer is deposited using a method known as the \"nanofog\" technique.\u003csup\u003e\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e,\u003cspan citationid=\"CR45\" class=\"CitationRef\"\u003e45\u003c/span\u003e\u003c/sup\u003e Top gate dielectric, 10 nm HfO\u003csub\u003ex\u003c/sub\u003e, is deposited using ALD. Then, similar to the bottom gate process, patterning is carried out to form the top gate dielectric, completing the device fabrication. See Fig. S5 for visualized fabrication processes.\u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec9\" class=\"Section2\"\u003e \u003ch2\u003eCompact modeling and 5-stage ring oscillator simulation\u003c/h2\u003e \u003cp\u003eIt is crucial to extract I-V and C-V characteristics of 2D FET for obtaining a PDK, assuming that elements like interconnections are similar to existing Si technology. Firstly, in actual devices, electrostatic doping is necessary due to the lack of doping techniques in the contact region. This results in significant parasitic capacitance from the overlap between the source/drain electrodes and the gate electrode. Therefore, we assumed no gate overlap and separately applied the gate-dependent contact resistance to the I-V calibration. Then, we were able to obtain the C-V curve for the assumed structure without overlap using TCAD. The experimentally obtained I-V curve was also utilized with the Verilog-A MVS model. Based on the completed PDK for the 2D FET, we conducted a SPICE simulation of a 5-stage ring oscillator. The load capacitance per stage used in this simulation was 1.2 fF, identical to the value used in previously reported ring oscillators based on 45 nm node Si transistors.\u003csup\u003e\u003cspan citationid=\"CR46\" class=\"CitationRef\"\u003e46\u003c/span\u003e,\u003cspan citationid=\"CR47\" class=\"CitationRef\"\u003e47\u003c/span\u003e\u003c/sup\u003e\u003c/p\u003e \u003c/div\u003e"},{"header":"References","content":"\u003col\u003e\u003cli\u003e\u003cspan\u003eCao W et al (2023) The future transistors. Nature 620:501\u0026ndash;515\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eFerain I, Colinge CA, Colinge J-P (2011) Multigate transistors as the future of classical metal\u0026ndash;oxide\u0026ndash;semiconductor field-effect transistors. Nature 479:310\u0026ndash;316\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLiu Y et al (2021) Promises and prospects of two-dimensional transistors. Nature 591:43\u0026ndash;53\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eJeong J et al (2023) World\u0026rsquo;s First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFET\u003csup\u003e\u0026trade;\u003c/sup\u003e) Process. in \u003cem\u003e2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\u003c/em\u003e 1\u0026ndash;2 \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.23919/VLSITechnologyandCir57934.2023.10185353\u003c/span\u003e\u003cspan address=\"10.23919/VLSITechnologyandCir57934.2023.10185353\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003e\u003cem\u003eIEEE International Roadmap for Devices and Systems 2022 Edition\u003c/em\u003e. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003ehttps://irds.ieee.org/editions/2022\u003c/span\u003e\u003cspan address=\"https://irds.ieee.org/editions/2022\" targettype=\"URL\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eO\u0026rsquo;Brien KP et al (2023) Process integration and future outlook of 2D transistors. Nat Commun 14:6400\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKim KS et al (2023) Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature 614:88\u0026ndash;94\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKo J-S et al (2023) Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2. in \u003cem\u003eESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)\u003c/em\u003e 1\u0026ndash;4 \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/ESSDERC59256.2023.10268527\u003c/span\u003e\u003cspan address=\"10.1109/ESSDERC59256.2023.10268527\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eShen P-C et al (2021) Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593:211\u0026ndash;217\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLi W et al (2023) Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613:274\u0026ndash;279\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKim KS et al Seamless monolithic three-dimensional integration of single-crystalline films by growth. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.48550/arXiv.2312.03206\u003c/span\u003e\u003cspan address=\"10.48550/arXiv.2312.03206\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eGuo Y et al (2021) Field-effect at electrical contacts to two-dimensional materials. Nano Res 14:4894\u0026ndash;4900\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eRadisavljevic B, Radenovic A, Brivio J, Giacometti V, Kis A (2011) Single-layer MoS2 transistors. Nat Nanotechnol 6:147\u0026ndash;150\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eUgeda MM et al (2014) Giant bandgap renormalization and excitonic effects in a monolayer transition metal dichalcogenide semiconductor. Nat Mater 13:1091\u0026ndash;1095\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKwon J et al (2017) Thickness-dependent Schottky barrier height of MoS2 field-effect transistors. Nanoscale 9:6151\u0026ndash;6157\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eCui X et al (2015) Multi-terminal transport measurements of MoS2 using a van der Waals heterostructure device platform. Nat Nanotechnol 10:534\u0026ndash;540\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSun Z et al (2022) Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2. ACS Nano 16:14942\u0026ndash;14950\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLiao F et al (2020) High-Performance Logic and Memory Devices Based on a Dual-Gated MoS2 Architecture. ACS Appl Electron Mater 2:111\u0026ndash;119\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eAsselberghs I et al (2020) Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab. in \u003cem\u003e2020 IEEE International Electron Devices Meeting (IEDM)\u003c/em\u003e 40.2.1\u0026ndash;40.2.4 \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM13553.2020.9371926\u003c/span\u003e\u003cspan address=\"10.1109/IEDM13553.2020.9371926\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eIllarionov YY et al (2020) Insulators for 2D nanoelectronics: the gap to bridge. Nat Commun 11:3385\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003ePasadas F et al (2019) Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances. Npj 2D Mater Appl 3:47\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eFan D et al (2023) Two-dimensional semiconductor integrated circuits operating at gigahertz frequencies. Nat Electron 6:879\u0026ndash;887\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSilvestri L et al (2023) Hierarchical modeling for TCAD simulation of short-channel 2D material-based FETs. Solid-State Electron 200:108533\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLiu L et al (2022) Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature 605:69\u0026ndash;75\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eHwangbo S, Hu L, Hoang AT, Choi JY, Ahn J-H (2022) Wafer-scale monolithic integration of full-colour micro-LED display using MoS2 transistor. Nat Nanotechnol 17:500\u0026ndash;506\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLi H et al (2012) From Bulk to Monolayer MoS2: Evolution of Raman Scattering. Adv Funct Mater 22:1385\u0026ndash;1390\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChou A-S et al (2020) High On-Current 2D nFET of 390 \u0026micro;A/\u0026micro;m at VDS\u0026thinsp;=\u0026thinsp;1V using Monolayer CVD MoS2 without Intentional Doping. in. \u003cem\u003eIEEE Symposium on VLSI Technology\u003c/em\u003e 1\u0026ndash;2 (2020). \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/VLSITechnology18217.2020.9265040\u003c/span\u003e\u003cspan address=\"10.1109/VLSITechnology18217.2020.9265040\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChou A-S et al (2021) Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics. in \u003cem\u003e2021 IEEE International Electron Devices Meeting (IEDM)\u003c/em\u003e 7.2.1\u0026ndash;7.2.4 \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM19574.2021.9720608\u003c/span\u003e\u003cspan address=\"10.1109/IEDM19574.2021.9720608\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChou A-S et al (2021) High On-State Current in Chemical Vapor Deposited Monolayer MoS2 nFETs With Sn Ohmic Contacts. IEEE Electron Device Lett 42:272\u0026ndash;275\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLi L et al (2024) Epitaxy of wafer-scale single-crystal MoS2 monolayer via buffer layer control. Nat Commun 15:1825\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eXiong X et al (2021) Demonstration of Vertically-stacked CVD Monolayer Channels: MoS2 Nanosheets GAA-FET with Ion\u0026thinsp;\u0026gt;\u0026thinsp;700 \u0026micro;A/\u0026micro;m and MoS2/WSe2 CFET. in \u003cem\u003e2021 IEEE International Electron Devices Meeting (IEDM)\u003c/em\u003e 7.5.1\u0026ndash;7.5.4 \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM19574.2021.9720533\u003c/span\u003e\u003cspan address=\"10.1109/IEDM19574.2021.9720533\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eCheng K-L et al (2007) A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 \u0026micro;m2 SRAM cell. in. \u003cem\u003eIEEE International Electron Devices Meeting\u003c/em\u003e 243\u0026ndash;246 (2007). \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM.2007.4418913\u003c/span\u003e\u003cspan address=\"10.1109/IEDM.2007.4418913\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMistry K et al (2007) A 45nm Logic Technology with High-k\u0026thinsp;+\u0026thinsp;Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. in. \u003cem\u003eIEEE International Electron Devices Meeting\u003c/em\u003e 247\u0026ndash;250 (2007). \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM.2007.4418914\u003c/span\u003e\u003cspan address=\"10.1109/IEDM.2007.4418914\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eZou T et al (2023) High-Performance Solution-Processed 2D P-Type WSe2 Transistors and Circuits through Molecular Doping. Adv Mater 35:2208934\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eLi N et al (2020) Large-scale flexible and transparent electronics based on monolayer molybdenum disulfide field-effect transistors. Nat Electron 3:711\u0026ndash;717\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eWu R et al (2022) Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5 milliamperes per micrometre. Nat Electron 5:497\u0026ndash;504\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eYu L et al (2016) Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics. Nano Lett 16:6349\u0026ndash;6356\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eNourbakhsh A et al (2016) MoS2 Field-Effect Transistor with Sub-10 nm Channel Length. Nano Lett 16:7798\u0026ndash;7806\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eMirabelli G, Hurley PK, Duffy R (2019) Physics-based modelling of MoS2: the layered structure concept. Semicond Sci Technol 34:055015\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eDonetti L et al (2022) Towards a DFT-based layered model for TCAD simulations of MoS2. Solid-State Electron 197:108437\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eStanojević Z et al (2021) Nano Device Simulator\u0026mdash;A Practical Subband-BTE Solver for Path-Finding and DTCO. IEEE Trans Electron Devices 68:5400\u0026ndash;5406\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eSeol M et al (2020) High-Throughput Growth of Wafer-Scale Monolayer Transition Metal Dichalcogenide via Vertical Ostwald Ripening. Adv Mater 32:2003542\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKwon J et al (2024) 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide transistors. Nat Electron. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1038/s41928-024-01158-4\u003c/span\u003e\u003cspan address=\"10.1038/s41928-024-01158-4\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eNguyen VL et al (2023) Wafer-scale integration of transition metal dichalcogenide field-effect transistors using adhesion lithography. Nat Electron 6:146\u0026ndash;153\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKwak I et al (2019) Low interface trap density in scaled bilayer gate oxides on 2D materials via nanofog low temperature atomic layer deposition. Appl Surf Sci 463:758\u0026ndash;766\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eHoffmann T et al (2006) Ni-based FUSI gates: CMOS Integration for 45nm node and beyond. in. \u003cem\u003eInternational Electron Devices Meeting\u003c/em\u003e 1\u0026ndash;4 (2006). \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1109/IEDM.2006.346759\u003c/span\u003e\u003cspan address=\"10.1109/IEDM.2006.346759\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eKittl JA et al (2006) CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:\u003cspan\u003e$\u003c/span\u003e\\hbox{Ni}_{2}\\hbox{Si}\u003cspan\u003e$\u003c/span\u003e, and \u003cspan\u003e$\u003c/span\u003e\\hbox{Ni}_{31}\\hbox{Si}_{12}\u003cspan\u003e$\u003c/span\u003e) on HfSiON. IEEE Electron Device Lett 27:966\u0026ndash;968\u003c/span\u003e \u003c/li\u003e \u003cli\u003e\u003cspan\u003eChou B-J et al (2024) High-performance monolayer MoS2 nanosheet GAA transistor. Nanotechnology 35:125204\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eJiang J et al (2024) Yttrium-doping-induced metallization of molybdenum disulfide for ohmic contacts in two-dimensional transistors. Nat Electron. \u003cspan class=\"ExternalRef\"\u003e\u003cspan class=\"RefSource\"\u003e10.1038/s41928-024-01176-2\u003c/span\u003e\u003cspan address=\"10.1038/s41928-024-01176-2\" targettype=\"DOI\" class=\"RefTarget\"\u003e\u003c/span\u003e\u003c/span\u003e\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eChen X et al (2021) Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning. Nat Commun 12:5953\u003c/span\u003e\u003c/li\u003e \u003cli\u003e\u003cspan\u003eWang H et al (2012) Integrated Circuits Based on Bilayer MoS2 Transistors. Nano Lett 12:4674\u0026ndash;4680\u003c/span\u003e\u003c/li\u003e\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":true,"hideJournal":false,"highlight":"","institution":"","isAcceptedByJournal":true,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"nature-portfolio","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"","title":"Nature Portfolio","twitterHandle":"","acdcEnabled":false,"dfaEnabled":false,"editorialSystem":"ejp","reportingPortfolio":"","inReviewEnabled":true,"inReviewRevisionsEnabled":false},"keywords":"","lastPublishedDoi":"10.21203/rs.3.rs-4632503/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-4632503/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eThe foundry industry and academia dedicated to advancing logic transistors are encountering significant challenges in extending Moore's Law. In the industry, silicon (Si)-based transistors are currently adopting gate-all-around (GAA) structures and reducing channel thickness, even at the cost of decreased mobility, for maximizing gate controllability. To compensate for the reduced mobility, multi-channel structures are essential, making the fabrication process extremely challenging. Meanwhile, two-dimensional (2D) semiconductors are emerging as strong alternatives for the channel material in logic transistors, thanks to their ability to maintain crystallinity even when extremely thin. In the case of 2D semiconductors, introducing a dual gate structure, which has a much lower fabrication complexity, can achieve effects similar to GAA. Through this research, we have identified the fringing field originating from the common structure of elevated top contact in 2D FETs results in a high charge injection barrier. Through simulation and statistical analysis with large-area FET arrays, we confirmed that introducing a dual-gate structure in bilayer MoS\u003csub\u003e2\u003c/sub\u003e FETs effectively compensates for the fringing field. We have confirmed that this leads to a significant boost in on-current. Remarkably, even with conventional contacts and polycrystalline materials, we observed a record-high on-current of 1.55 mA/\u0026micro;m. Additional circuit simulations have confirmed the potential for dual gate bilayer FETs to surpass the performance of Si GAAFETs when possessing a gate length of 5 nm, achievable only with 2D materials. Therefore, here we propose that by using 2D materials, we can focus on extreme gate length scaling and monolithic 3D integration rather than the challenging GAA process for extending Moore\u0026rsquo;s Law.\u003c/p\u003e","manuscriptTitle":"Gate structuring on bilayer transition metal dichalcogenides enables ultrahigh current density","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2024-07-10 16:42:15","doi":"10.21203/rs.3.rs-4632503/v1","editorialEvents":[],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"nature-materials","isNatureJournal":true,"hasQc":false,"allowDirectSubmit":false,"externalIdentity":"nmat","sideBox":"Learn more about [Nature Materials](http://www.nature.com/nmat/)","snPcode":"","submissionUrl":"","title":"Nature Materials","twitterHandle":"","acdcEnabled":true,"dfaEnabled":true,"editorialSystem":"ejp","reportingPortfolio":"Nature Research","inReviewEnabled":true,"inReviewRevisionsEnabled":false}}],"origin":"","ownerIdentity":"edf3ab18-a3c9-434b-84b1-4f2cfe2bc608","owner":[],"postedDate":"July 10th, 2024","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"published-in-journal","subjectAreas":[{"id":34323488,"name":"Physical sciences/Materials science/Materials for devices/Electronic devices"},{"id":34323489,"name":"Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices"},{"id":34323490,"name":"Physical sciences/Nanoscience and technology/Nanoscale materials/Two-dimensional materials"}],"tags":[],"updatedAt":"2026-01-10T08:12:59+00:00","versionOfRecord":{"articleIdentity":"rs-4632503","link":"https://doi.org/10.1038/s41563-025-02452-y","journal":{"identity":"nature-materials","isVorOnly":false,"title":"Nature Materials"},"publishedOn":"2026-01-09 05:00:00","publishedOnDateReadable":"January 9th, 2026"},"versionCreatedAt":"2024-07-10 16:42:15","video":"","vorDoi":"10.1038/s41563-025-02452-y","vorDoiUrl":"https://doi.org/10.1038/s41563-025-02452-y","workflowStages":[]},"version":"v1","identity":"rs-4632503","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-4632503","identity":"rs-4632503","version":["v1"]},"buildId":"8U1c8b4HqxoKbykW_rLl7","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}