Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications

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Srinivasa Rao This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-2212833/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract Traditionally, Image processing applications perform momentous data refinement. One of the most efficacious methods for data manipulation in multiple image processing applications is approximate computing. This mitigates the circuit complexity and thereby reinforces the power, latency, and area metrics. Furthermore, multiplication is also an essential operation in most image-processing applications. In the current scenario, numerous existing state-of-the-art multipliers employed approximation computation techniques to raise the design metrics with limited accuracy. As a consequence, this paper instigates two novel multipliers, namely, one-bit Based Static Segment Inaccurate Multipliers - LBSSIM0 and LBSSIM1, with and without a Hybrid Estimator Logic Circuit (HELC), so as to revamp the accuracy and design metrics. The HELC function is to efface the lower-order significant input bit width data and conceal the inaccurate multiplication of the proposed LBSSIM designs using the barrel shifter and the leading unit. The preferred inaccurate multipliers are simulated and synthesized using Xilinx Vivado, MATLAB, and Cadence RTL compilers for the input widths of 8-bit, 16-bit, and 32-bit. The results reveal that the recommended LBSSIMs dwindle the delay, area, energy, and power on an average of 32.13%, 65.23%, 57.12%, and 64.3%, respectively, with the state-of-the-art Inaccurate Multipliers (IMs). It is also unveiled through the simulation results that the proposed LBSSIMs reinforce the performance of accuracy metrics, namely, MRED, NED, MED, and WCE, on an average of 42.12%, 17.23%, 46.54%, and 28.24%, respectively, as opposed to the state-of-the-art IMs. Eventually, after incorporating the proposed LBSSIMs in the image processing applications, they purveyed higher Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) when collated with the state-of-the-art IMs. Leading One Bit Static Segment Method Approximate Computing Hybrid Estimator Logic Circuit. Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 1. Introduction Very Large Scale Integration (VLSI) architectures must be used in Digital Signal Processing (DSP) applications. High-performance entities are incorporated into DSP designs to dilate image processing applications' precision, which boosts the whole performance with general-purpose processors employing comparable CMOS technology [ 1 , 2 ]. Multipliers and adders are two essential functions of filters used in DSP architecture. However, the filter performance may be degraded if the adders and multipliers are too slow, expensive in energy, inaccurate, or have a large overhead area. Due to this, a filter design centred on a scientific probability model is used to minimize the noisy data. This mathematical model, computation error tolerance, has been used to exchange precision for energy consumption [ 3 ]. Faulty multiplication and addition have effectively persisted in DSP design at the detriment of precision in favour of area, power, and speed advantages. Numerous studies have been done on multiplier designs to escalate energy efficiency while compromising accuracy in VLSI design. These studies used lesser least significant word lengths, extreme voltage scaling, and the employment of incorrect building blocks [ 4 ]-[ 12 ]. Latterly, the DSP design focus is on adder and multiplier circuit designs, with resource management. For the balanced performance of any design, the four essentials are energy efficiency, high computational accuracy, area efficiency, and high - speed. Moreover, in high-performance image processing applications, the design structure's stability is crucial in subsiding the error. Nevertheless, all existing IMs go astray to upgrade both design and accuracy metrics. High-precision algorithms predominantly prospered for core arithmetic units prior to being included in processor designs. Accordingly, this paper endeavours to design two new leading one Bit Based Static Segment Inaccurate Multipliers, namely, LBSSIM0 and LBSSIM1 with and without HELC, so as to enhance the design and accuracy metrics. This adaptation approach unveils the DSP application’s efficiency, which escalates the amount of computational accuracy. The hindrances of existing multipliers are taken into consideration, and effective design of LBSSIM0 and LBSSIM1 architectures are recommended and further applied to Gaussian Filter (GF), Image Smoothing Filter (ISF), and Edge Detection Filter (EDF) applications. In the LBSSIM0 design that is being proposed, the k-bit segment may start at either the k or k-k/2 bit positions of the k-bit input bit width. The static k/2-bit segment is determined by the Leading One Bit (LOB), which can be encountered in lower or higher-order segments. The LOB block receives one segment output; further, the barrel shifter accomplishes multiplication. For the k-bit input bit width, the preferred LBSSIM1 architecture permits the m-bit segment to start at either k or k-k/2 bit positions. The LOB identifies the static k/2-bit segment, which can be spotted either in lower or higher-order segment sections. By eradicating the lower order k/2-bit segment of the input bit width and if on choosing the k/2-bit higher order segment, the HELC upgrades the accuracy. Due to this, one output segment is employed to the LOB unit, and thereby the barrel-shifter performs multiplication. This method outstrips earlier IMs in terms of design and accuracy metrics. In addition to this, analysis of accuracy metrics [ 13 , 14 ] is accomplished for Worst Case of Error (WCE), Error Distance (ED), Mean Relative ED (MRED), Normalized ED (NED), and Mean ED (MED) for both the existing IMs and proposed LBSSIM0 and LBSSIM1 multipliers. Further, in this paper, ISF [ 15 ], GF [ 9 ], and EDF [ 16 ], combined with suggested multipliers (LBSSIM0, LBSSIM1) and the present IMs, are validated and tested with standard house test images [ 17 ] in order to analyze the equivalent quality metrics [ 18 ] in terms of PSNR and SSIM. The remaining paper is categorized as follows: The available inaccurate multiplication methods are explored in the second section. The third section bestowed the proposed LBSSIM designs. Later, the analysis of simulation results and applications are detailed in the fourth section. Eventually, the conclusion is furnished in the fifth section. 2. State-of-the-art Ims The latest IMs are studied in this segment. Khaing et al. presented an IM whose input bit widths are cleaved into precise and imprecise segments with limited MSBs and residue LSBs. Yet, accuracy is shrinked, depending on MSB and LSB bits [ 4 ]. Garg et al. came up with an IM by calculating the faulty products utilizing AND-OR logic for little LSBs [ 5 ]. The IM area and power are enhanced with an improvement in the input operand width. A precision configurable IM was developed by Garg et al. that incorporates the IM with EDC logic to engender damaged final products with high accuracy and low performance [ 6 ]. Additionally, in Dynamic-Range unbiased IM (DRIM), when the fault generated by the truncation method for shifting the MRED is pushed to zero, the LSB of the truncated input is set to one [ 7 ], and the accuracy metrics of DRIM hang on the dynamic range too. R. Jothin et al. designed an Adapted Static Segment IM (ASSIM) to escalate the precision. For this to be done, they utilized import ELC to repudiate the lower-order information of input width. However, the accuracy of ASSIM declined with increased input bit width [ 8 ]. Bharat Garg et al. have deliberated a LOB-based IM (LOBIM), which fostered a final inaccurate product that specifies j-bit from the k-bit input and hangs on LOB-logic [ 9 ]. The accuracy and design metrics of this IM depend on the chosen k-bits. Thereby, it enhanced the accuracy metrics by precisely electing m-bits centered on the LOB position. Bharat Garg et al. suggested an IM using the Rounding Approach (RAIM). Initially, the input bit width of the operand is rounded to the adjacent power of two values, and then the final IM product is realized using a few adders and barrel shifters [ 10 ]. The proposed RAIM significantly diminished the performance complexity and depleted the energy consumption but with an increase in error. Shaghayegh Vahdat et al. created error-efficient IM, which ameliorates the accuracy and design metrics, but flaws heighten as the width of the input revamps [ 11 ]. As per the literature review, the state-of-the-art IMs imparted better design metrics but not improved accuracy metrics. Hence, the proposed LBSSIMs minimize the design metrics with the minimization of error metrics which are explained in the following section. 3. Proposed Leading One-bit Based Static Segment Inaccurate Multipliers This segment deliberates the two LBSSIM Architectures processes. 3.1. Proposed LBSSIM0 The main objective of the proposed LBSSIM0 is to narrow the design metrics by using the static segment approach with the LOB unit, in contrast with State-of-the-art IMs. Generally, the LOB unit is detected in the leading bit position from MSB to LSB side of input operands. Using the position of this value, directly left shift the other input value; hence, the LOB unit has reduced the complexity of the proposed IM design compared to the State-of-the-art IMs. The process of the proposed k-bit LBSSIM0 multiplier is given beneath: For each k-bit input bit width, the m-bit lower-order or higher-order LOB segment output is taken. One k/2-bit segment output is applied to the LOB unit. The barrel shifter performs multiplying operations for the outputs of the k/2-bit segment and the LOB unit. By shifting the k-bit-based LOB, position value is attained by shifting the 2k-bit incorrect product. Figure 1 illustrates the suggested k-bit LBSSIM0 architecture. Each k/2-bit input bit width segment is taken from the available two input segments. The LOB unit grabs one of the values of the segment, and the LOB unit output is specified as the LOB position. The LOB operation is extensively narrated in [ 9 ]. The Mathematical expression of the LOB unit is conveyed in Eq. (1). The Gate level representation of the LOB Unit for 8-bit input operands is indicated in Fig. 2 . \(Y=(\prod\limits_{{k=i+1}}^{{\frac{k}{2} - 2}} {\overline {{B(k)}} } ) \bullet B(k)\) for \(0 \leqslant k \leqslant \frac{k}{2} - 2\) (1) Where Y = k/2-bit B. A barrel shifter utilizes the last k-bit multiplication wielding the k/2-bit segment and LOB value. Gate level representation of the barrel shifter is fully explicated in ref [ 20 ]. By adding zeros, the multiplier k-bit output may be increased to a 2k-bit output. The multiplexer chooses W1 when two segments of the input operands are from the higher and m-bit lower segments, or vice versa. The multiplexer selects W2 when both segments are from the m-bit lower segments. The multiplexer choosesW3 when both input operand parts come from the higher ones. The circuit's complexity, power, and latency are diminished in the proposed LBSSIM0. 3.2. Proposed LBSSIM1 The main objective of the proposed LBSSIM1 is to shorten the design and error metrics compared to that of State-of-the-art IMs, by exploiting the static segment approach with LOB and HELC units. By incorporating the HELC unit in the proposed LBSSIM0, the errors are reduced compared to State-of-the-art IMs. Furthermore, by exercising the HELC unit, the suggested LBSSIM1 multiplier has alleviated error metrics values compared to that of LBSSIM0. The procedure of the proposed k-bit LBSSIM1 multiplier is given below: For each k-bit’s input bit width, lower or higher order LOB segments output of k/2-bit is chosen. K/2-bit’s output of one segment is applied to the HELC unit. The output of HELC is applied to the LOB unit. The barrel shifter executes the multiplying operation on HELC and LOB output related to k/2-bit. By extending the k-bit LOB position value, 2k-bit incorrect product is figured out. The LBSSIM multiplier designs have incremented accuracy for all the input bit width combinations by replacing the k-bit multipliers circuit with the k/2-bit multiplier for large values. Figure 3 depicts the preferred LBSSIM1 architecture. In this multiplier, the higher segment values which were given to the HELC unit earlier (LBSSIM0 multiplier) are now applied to the LOB unit. As a result, by adopting the HELC unit, the chosen LBSSIM1 multiplier magnified both the accuracy and design metrics. The main intention of the HELC unit is to escalate the accuracy of the proposed LBSSIM1 in contrast to the state-of-the-art IMs and the suggested LBSSIM0. Figure 4 manifests the HELC architecture, and Table 1 expounds its logic function. According to this approach, the HELC's output function will be either R1 or Binary to Excess Three Code (BETC) output R1 + 3, which is totally based on the control signals. Table 1 HELC Truth table CA R1 < 2 m -1 (C = Carry Output) Output S1 0 × R1 1 × R1 1 0 R1 + 3 1 1 R1 4. Comparison Of Simulation Results This segment projects the analysis of design metrics and subsequently compares the proposed multipliers to existing IM’s with reference to design, accuracy, and quality metrics. 4.1 Design Metrics Analysis Design metrics of the suggested LBSSIM0 and LBSSIM1 multipliers in a company with state-of-the-art IMs [ 7 ]-[ 10 ] (DRIM, ASSIM, LOBIM, and RAIM) having input bit widths of 8-bit, 16-bit, and 32-bit are examined and are coded in Verilog HDL. Succeeding, all IMs are synthesized using Cadence RTL Compiler with 90 nm standard CMOS library. The truncation length of the DRIM design is six. The ASSIM and LOBAM truncation lengths are half of the input operand, and the type of RAIM is an unsigned RAIM. Table 2 bestows the design metrics of state-of-the-art IMs and proposed multipliers in terms of delay, area, energy, and power, from which it is divulged that the proposed 8-bit LBSSIM0 and LBSSIM1 slump the energy consumption compared to DRIM, ASSIM, LOBIM, and RAIM. Moreover, the proposed multipliers plunge the delay and power on an average of 28.32%, 48.23%, and 68.23%, respectively, over past 8-bit IMs [ 7 ], [ 8 ], [ 9 ], [ 10 ]. Table 2 design metrics comparison of 8-bit IMs Bit-Width Metrics DRIM [ 7 ] ASSIM [ 8 ] LOBIM [ 9 ] RAIM [ 10 ] LBSSIM0 LBSSIM1 8-bit Area ( µm 2 ) 1820 576 1247 1461 175 176 Delay ( ns ) 4.25 3.11 5.24 6.54 1.56 1.56 Power ( mW ) 0.09 0.05 0.02 0.09 0.03 0.02 Energy ( fJ ) 382 155 104 588 468 312 The underneath Table 3 exhibits the design metric analysis of 16-bit proposed and current multipliers, from which it is proclaimed that the suggested multipliers dwindled energy compared to DRIM, ASSIM, LOBIM, and RAIM. Moreover, they also slackened the delay, area, and power, on an average of 28.2%, 58.12%, and 56.23%, respectively, in contrast to DRIM, ASSIM, LOBIM, and RAIM. Table 3 design metrics comparison of 16-bit IMs Bit-Width Metrics DRIM [ 7 ] ASSIM [ 8 ] LOBIM [ 9 ] RAIM [ 10 ] LBSSIM0 LBSSIM1 16-bit Area ( µm 2 ) 3012 1939 3417 6739 478 479 Delay ( ns ) 5.18 7.19 4.69 8.54 3.15 3.13 Power ( mW ) 31.12 180.1 190.4 30.12 17.33 17.31 Energy ( fJ ) 6781 1294 892 1281 545 541 Similarly, Table 4 depicts the design metric analysis of 32-bit proposed and current multipliers, showing that the suggested multipliers consume less energy than DRIM, ASSIM, LOBIM, and RAIM. Furthermore, it is also exposed that LBSSIM0 and LBSSIM1 multipliers slashed the delay, area and power on an average of 24.32%, 40.5%, and 62.23% individually, compared to 32-bit IMs [ 7 ], [ 8 ], [ 9 ], [ 10 ]. Table 4 design metrics comparison of 32-bit IMs Bit-Width Metrics DRIM [ 7 ] ASSIM [ 8 ] LOBIM [ 9 ] RAIM [ 10 ] LBSSIM0 LBSSIM1 32-bit Area ( µm 2 ) 5146 5730 8931 19865 1335 1334 Delay ( ns ) 5.54 13.99 6.99 12.41 4.55 3.15 Power ( mW ) 82.13 794.36 631.1 82.4 44.25 30.06 Energy ( fJ ) 45000 11113 44113 10225 2033 946 On top of that, the design metrics were also graphically depicted in Fig. 5 , which clearly differentiates between state-of-the-art and proposed IMs. Figure 5 (a) illustrates the area, Fig. 5 (b) depicts the delay, Fig. 5 (c) illustrates the power, and Fig. 5 (d) depicts the energy. From these graphs, it’s very transparent that the proposed IMs achieved a declination in design metrics compared to the state-of-the-art IMs. 4.2 Accuracy and Quality Metrics Analysis This section primarily illustrates the accuracy metrics analysis of the proposed LBSSIM0 and LBSSIM1 multipliers in terms of NED, MED, MRED, ED, and WCE. Subsequently, the proposed multipliers and the state-of-the-art IMs are gauged based on the accuracy metrics in ref. [ 13 , 14 ]. Ultimately, analysis of quality metrics is accomplished in terms of PSNR and SSIM by amalgamating the proposed and state-of-the-art IMs in the ISF, GF, and EDF. 4.2.1 Analysis of Accuracy Metrics The accuracies of proposed multipliers, namely, LBSSIM0 and LBSSIM1, are estimated using accuracy metrics like MRED, NED, MED, and WCE and compared with the state-of-the-art IMs. The discussed IMs are coded in Verilog HDL, simulated with 1 million systematic input patterns, and their respective accuracy metrics are computed in MATLAB. The simulation procedure of computing the accuracy metrics is systematically expounded in [ 11 ]. Table 5 itemizes the accuracy metrics for the chosen LBSSIM0, LBSSIM1 and the existing IMs of bit widths 8-bit, 16-bit, and 32-bit. The reported results illustrate that the proposed LBSSIM0 and LBSSIM1 have minimized ED in the range of 28.15% − 43.23%, compared to DRIM, ASSIM, LOBIM, and RAIM. Table 5 further clarifies that, for the proposed LBSSIM0 and LBSSIM1 multipliers the values of MRED, NED, MED, and WCE are slackened in contrast to DRIM, ASSIM, LOBIM, and RAIM, lying in the range of 19.22% − 9.09%, 70.1% − 19.13%, 78.22% − 9.22%, and 48.21% − 19.1%, respectively. Table 5 Accuracy metrics comparison of IMs Bit-Width Metrics DRIM [ 7 ] ASSIM [ 8 ] LOBIM [ 9 ] RAIM [ 10 ] LBSSIM0 LBSSIM0 8-bit MRED 6.07E-05 1.02E-06 2.36E-05 5.16E-06 6.63E-06 5.37E-08 NED 0.25 0.23 0.21 0.08 0.18 0.16 MED 1.59E + 04 1088.8 1.26E + 04 5.01E + 03 4.46E + 04 4458.1 ED 1.03E + 09 70798444 823636708 325889758 289887262 289887262 WCE 65378 48248 62158 62950 24658 24658 16-bit MRED 1.22E-07 7.85E-07 3.70E-06 3.80E-06 5.20E-06 5.20E-06 NED 0.15 0.13 1.18E-04 0.18 0.35 0.32 MED 4.96E + 02 2.74E + 03 5.08E + 05 6.57E + 06 5.27E + 03 5274.2 ED 130116224 718644558 1.33E + 11 1.72E + 12 342954162 342954156 WCE 53520 22418 4.29E + 09 3.75E + 09 15170 15170 32-bit MRED 2.79E-05 3.79E-06 3.80E-06 3.81E-05 4.77E-06 2.18E-06 NED 0.21 6.20E-04 1.58E-04 0.29 0.22 0.20 MED 1.01E + 04 2.66E + 06 6.81E + 05 1.27E + 07 3.46E + 03 8.34E + 03 ED 2.62E + 09 6.98E + 11 1.78E + 11 3.34E + 12 224708161 606751018 WCE 47950 4.31E + 09 4.42E + 09 4.39E + 08 15138 42036 Additionally, the Accuracy metrics are graphically portrayed in Fig. 6 , which reveals the collation of the state-of-the-art and proposed IMs for bit width’s − 8-bit, 16-bit, and 32-bit. Figure 6 (a) presents the NED, Fig. 6 (b) illustrates the MED, Fig. 6 (c) depicts the MRED, Fig. 6 (d) presents the ED, and Fig. 6 (e) illustrates the WCE, and from these, it’s transparent that the preferred IMs shrink the accuracy metrics compared to that of state-of-the-art IMs. 4.2.2Analysis of ISF/GF/EDF Quality Metrics In this segment, for the purpose of quality metrics analysis of SSIM and PSNR, ISF, GF, and EDF with the proposed multipliers are simulated and tested with standard test images. In ISF, GF, and EDF, the pixel is generated by performing convolution between the sub-matrix of input image's and the standard mask [ 11 ], [ 9 ], [ 16 ]. Furthermore, like other IM’s, the proposed LBSSIM0 and LBSSIM1 multipliers are also used to analyze the performance of ISF, GF, and EDF. ISF, GF, and EDF homogenized with the proposed 8-bit LBSSIM0, LBSSIM1 and state-of-the-art IMs are evaluated using the quality metrics. These IMs, ISF, GF, and EDF are examined and simulated using a standard house image. The extraction process of quality metrics is completely described in [ 11 ]. Table 6 renders the computed quality metrics of ISF integrated with state-of-the-art and proposed IMs. The reported results conclude that ISF merged with the proposed multipliers revamp SSIM and PSNR in the limit of 4.5% − 7.4% and 7.9% − 11.2%, respectively, over the ISF combined with state-of-the-art IM’s, namely, DRIM, ASSIM, LOBIM, and RAIM. Table 6 ISF quality metrics of the IMs Metrics DRIM[ 7 ] ASSIM[ 8 ] LOBIM[ 9 ] RAIM[ 10 ] LBSSIM0 LBSSIM1 SSIM 0.738 0.713 0.713 0.712 0.792 0.802 PSNR (db) 28.81 28.75 27.91 27.82 30.12 30.11 Also, the House images of the ISF combined with state-of-the-art and proposed IMs are depicted in Fig. 7 and present that the ISF combined with proposed multipliers give better image quality in contrast to past IMs [ 7 ], [ 8 ], [ 9 ], [ 10 ]. Table 7 depicts the quality metrics of GF combined with state-of-the-art and proposed IMs. The reported simulation results demonstrate that GF combined with the proposed multipliers (LBSSIM0, LBSSIM1) upgraded the PSNR and SSIM metrics and are within the limits of 4.3% − 6.9% and 9.9% − 11.34%, respectively. Table 7 GF quality metrics of the IMs. Metrics DRIM[ 7 ] ASSIM[ 8 ] LOBIM[ 9 ] RAIM[ 10 ] LBSSIM0 LBSSIM1 PSNR (db) 27.12 27.91 27.26 27.45 29.12 29.14 SSIM 0.722 0.711 0.713 0.723 0.801 0.802 House test images of GF combined with state-of-the-art and proposed multipliers are depicted in Fig. 8 . It’s perspicuous from the images that GF combined with proposed LBSSIM0 and LBSSIM1 gives good image quality than the GF combined with the DRIM, ASSIM, LOBIM, and RAIM. Table 8 projects the computed quality metric EDF, combined with state-of-the-art and proposed IMs. The reported results illustrate that, in contrast to past IMs with EDF, EDF in combination with the proposed multipliers, provided better PSNR and SSIM, lying in the limits of 16.6% − 17.3%, and17.9% − 19.7%, respectively. Also, the House test images of EDF combined with state-of-the-art and proposed IMs are pictured in Fig. 9 . It conveys that EDF combined with proposed IM’s enhanced the image quality compared to the EDF combined with state-of-the-art IM’s like DRIM, ASSIM, LOBIM, and RAIM. Table 8 EDF quality metrics of the IMs Metrics DRIM[ 7 ] ASSIM[ 8 ] LOBIM[ 9 ] RAIM[ 10 ] LBSSIM0 LBSSIM1 PSNR (db) 20.13 20.47 21.22 20.15 24.12 24.01 SSIM 0.412 0.413 0.421 0.402 0.513 0.513 5. Conclusion This paper propounds two static segment IMs (LBSSIM0 and LBSSIM1) based on the LOB technique. In LBSSIM0, the barrel shifter initially executes multiplication after applying one k/2-bit of static output to the LOB unit and, later, identifies the k/2-bit static segment using the LOB position value. Thereby, the multiplexer ultimately selects the incorrect product. The multiplier LBSSIM1 performs the remaining operations, and just like LBSSIM0, it also executes a multiplier function while adding one block to represent the HELC unit. The area, latency, power, and accuracy metrics of the proposed LBSSIM0 and LBSSIM1 multipliers are better than those of state-of-the-art IMs. Eventually, the proposed LBSSIM0 and LBSSIM1 are integrated with ISF, GF, and EDF, which are tested using quality measures. The simulation findings demonstrate that when combined with the ISF, GF, and EDF, the proposed multipliers achieved refined quality metrics than the ISF, GF, and EDF mixed with state-of-the-art IMs. Declarations Data Availability Statement Data sharing is unconnected to this paper since no datasets were produced or examined throughout the Proposed and state-of-the-art IM s. Funding No Funding Conflict of Interest Statement I certify no actual or potential conflict of interest about this article. Competing Interests The authors declare that they have no known competing financial interests or personal relationships that could influence the work reported in this paper. References J. Han and M. Orshansky (2013) "Approximate computing: An emerging paradigm for energy-efficient design". In Proc. of 18 th IEEE European Test Symposium (ETS) , IEEE European, pp. 1–6. Botella G, García C, Meyer-Bäse U (2013) Hardware implementation of machine vision systems: image and video processing . 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Wang Z, Bovik A, Sheikh H, Simoncelli E (2004) Image quality assessment: from error visibility to structural similarity. IEEE Transactions on Image Processing 13(4):600–612. Vahdat S, Kamal M, Afzali-Kusha A, Pedram M (2019) TOSAM: An energy-efficient truncation-and rounding-based scalable approximate multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27(5): 1161-1173. Karthikumar .R, Allin Joe D (2017) Behavioral level simulation of Vedic multiplier for ALU. Journal of Advanced Research in Dynamical and Control Systems 9(16):1231-1249. Supplementary Files AuthorsPictureBiography.docx Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. 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Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {"props":{"pageProps":{"initialData":{"identity":"rs-2212833","acceptedTermsAndConditions":true,"allowDirectSubmit":true,"archivedVersions":[],"articleType":"Research Article","associatedPublications":[],"authors":[{"id":150827758,"identity":"fe55a63e-169b-40b1-97c8-49c1c5470fb0","order_by":0,"name":"Tilak Raju Daram","email":"data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAZAAAAAyAQMAAABI0h/eAAAABlBMVEX///8AAABVwtN+AAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA70lEQVRIiWNgGAWjYDACZuYGxgYgxSB//uEDIJ+Hj5AOHmZGqBYJHmYDkAAbQS0MEC0MQC1sEiCaoBZ7dsbGjzP32LEb3O49Vvk1x06GjYH54aMb+B3WLLnhWTKzwZ1zabdltyUDHcZmbJxDwC+SDw4wMxscSDC7LbmNGaiFh02agJbmnw8O1IO1FEtuqydKS5vkhgOHmQ1u5Jgxftx2mAgthxnbLGccOM4seeZYsjTjtuM8bMwE/MLef/jwzZ4D1cl8x5sPfvy5rdqen7354WN8WmAgGUQw84BJIpSDgB2IYPxBpOpRMApGwSgYWQAAOiZF0Uk+Kx8AAAAASUVORK5CYII=","orcid":"https://orcid.org/0000-0002-4360-6067","institution":"Vignan's Institute of Engineering for Women","correspondingAuthor":true,"prefix":"","firstName":"Tilak","middleName":"Raju","lastName":"Daram","suffix":""},{"id":150827759,"identity":"48ec264f-6213-4663-b2fa-5beeac2cbf51","order_by":1,"name":"Y. Srinivasa Rao","email":"","orcid":"","institution":"Andhra University","correspondingAuthor":false,"prefix":"","firstName":"Y.","middleName":"Srinivasa","lastName":"Rao","suffix":""}],"badges":[],"createdAt":"2022-10-28 12:27:47","currentVersionCode":1,"declarations":"","doi":"10.21203/rs.3.rs-2212833/v1","doiUrl":"https://doi.org/10.21203/rs.3.rs-2212833/v1","draftVersion":[],"editorialEvents":[],"editorialNote":"","failedWorkflow":false,"files":[{"id":28959570,"identity":"6b82d201-26f6-4bb2-b2b3-cecd41548780","added_by":"auto","created_at":"2022-11-11 16:12:59","extension":"png","order_by":1,"title":"Figure 1","display":"","copyAsset":false,"role":"figure","size":146017,"visible":true,"origin":"","legend":"\u003cp\u003eArchitecture of proposed LBSSIM0 multiplier\u003c/p\u003e","description":"","filename":"floatimage1.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/d231ba8d899d3e615f890952.png"},{"id":28958506,"identity":"d1e785b0-de03-423c-96a5-cd4cd7c3e3b7","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":2,"title":"Figure 2","display":"","copyAsset":false,"role":"figure","size":119418,"visible":true,"origin":"","legend":"\u003cp\u003eGate-level LOB unit representation for 8-bit input operands [19].\u003c/p\u003e","description":"","filename":"floatimage2.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/7e11e040428eb39457bf4934.png"},{"id":28958515,"identity":"ea1de27b-ca30-423d-bd61-692d2a3306c2","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":3,"title":"Figure 3","display":"","copyAsset":false,"role":"figure","size":163481,"visible":true,"origin":"","legend":"\u003cp\u003eProposed LBSSIM1 architecture\u003c/p\u003e","description":"","filename":"floatimage3.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/64f36f6f76a21b787fb6a422.png"},{"id":28958507,"identity":"d2a8f8a6-9af3-43d2-8c61-275d8d83ff3a","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":4,"title":"Figure 4","display":"","copyAsset":false,"role":"figure","size":62981,"visible":true,"origin":"","legend":"\u003cp\u003eArchitecture of HELC unit\u003c/p\u003e","description":"","filename":"floatimage4.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/764872820d0e78d1e45e2a18.png"},{"id":28958510,"identity":"638ad231-7987-408c-b829-24136729b069","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":5,"title":"Figure 5","display":"","copyAsset":false,"role":"figure","size":1038693,"visible":true,"origin":"","legend":"\u003cp\u003eGraphical Comparison of\u003cstrong\u003e state-of-the-art \u003c/strong\u003eand proposed IMs in terms of \u0026nbsp;(a) Area, (b) Delay, (c) Power, and (d) Energy, holding bit width’s - 8-bit,16-bit, and 32-bit,\u003c/p\u003e","description":"","filename":"floatimage5.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/fde6161c729d8a386cfbb04b.png"},{"id":28959139,"identity":"807b0dea-66a0-42dc-a099-01f51db73962","added_by":"auto","created_at":"2022-11-11 16:04:59","extension":"png","order_by":6,"title":"Figure 6","display":"","copyAsset":false,"role":"figure","size":1486879,"visible":true,"origin":"","legend":"\u003cp\u003eGraphical Comparison of proposed and current IMs in terms of (a) NED, (b) MED, (c) MRED, (d) ED, and (e) WCE\u003c/p\u003e","description":"","filename":"floatimage6.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/5b8c6cd24c45d480b23b7e96.png"},{"id":28958512,"identity":"5301b5f4-ca6c-4c4e-845a-d3501fe7b8a5","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":7,"title":"Figure 7","display":"","copyAsset":false,"role":"figure","size":1094624,"visible":true,"origin":"","legend":"\u003cp\u003eHouse test images of ISF combined with: (a) DRIM [7], (b) ASSIM [8], (c) LOBIM [9], (d) RAIM [10], (e) LBSSIM0, and (f) LBSSIM1\u003c/p\u003e","description":"","filename":"floatimage7.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/a6c95c09e0e53c4b133974b7.png"},{"id":28959140,"identity":"0731606b-feba-4900-ade1-13524c0d3c46","added_by":"auto","created_at":"2022-11-11 16:04:59","extension":"png","order_by":8,"title":"Figure 8","display":"","copyAsset":false,"role":"figure","size":270842,"visible":true,"origin":"","legend":"\u003cp\u003eHouse test images of GF combined with: (a) DRIM [7], (b) ASSIM [8], (c) LOBIM [9], (d) RAIM [10], (e) LBSSIM0, and (f) LBSSIM1\u003c/p\u003e","description":"","filename":"floatimage8.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/44fa644c6637d4cb27d95a6b.png"},{"id":28958514,"identity":"05b30092-1dfe-4a71-9876-948cf96f8f02","added_by":"auto","created_at":"2022-11-11 15:56:59","extension":"png","order_by":9,"title":"Figure 9","display":"","copyAsset":false,"role":"figure","size":191791,"visible":true,"origin":"","legend":"\u003cp\u003eHouse test images of EDF combined with: (a) DRIM [7], (b) ASSIM [8], (c)LOBIM [9], (d) RAIM [10], (e) LBSSIM0, and (f) LBSSIM1\u003c/p\u003e","description":"","filename":"floatimage9.png","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/b390acc69f824ad59df5c9e0.png"},{"id":104437715,"identity":"666cd4a5-03c4-447e-a9b2-d647309bac70","added_by":"auto","created_at":"2026-03-11 17:11:50","extension":"pdf","order_by":0,"title":"","display":"","copyAsset":false,"role":"manuscript-pdf","size":5059425,"visible":true,"origin":"","legend":"","description":"","filename":"manuscript.pdf","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/2b5f951d-c22c-4e98-bdb0-f61499f6f83b.pdf"},{"id":28959137,"identity":"b070e654-5664-46c6-b29f-b038af00555c","added_by":"auto","created_at":"2022-11-11 16:04:59","extension":"docx","order_by":1,"title":"","display":"","copyAsset":false,"role":"supplement","size":45400,"visible":true,"origin":"","legend":"","description":"","filename":"AuthorsPictureBiography.docx","url":"https://assets-eu.researchsquare.com/files/rs-2212833/v1/dd95409daf660d7ca37cf528.docx"}],"financialInterests":"","formattedTitle":"Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications","fulltext":[{"header":"1. Introduction","content":"\u003cp\u003eVery Large Scale Integration (VLSI) architectures must be used in Digital Signal Processing (DSP) applications. High-performance entities are incorporated into DSP designs to dilate image processing applications' precision, which boosts the whole performance with general-purpose processors employing comparable CMOS technology [\u003cspan citationid=\"CR1\" class=\"CitationRef\"\u003e1\u003c/span\u003e, \u003cspan citationid=\"CR2\" class=\"CitationRef\"\u003e2\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eMultipliers and adders are two essential functions of filters used in DSP architecture. However, the filter performance may be degraded if the adders and multipliers are too slow, expensive in energy, inaccurate, or have a large overhead area. Due to this, a filter design centred on a scientific probability model is used to minimize the noisy data. This mathematical model, computation error tolerance, has been used to exchange precision for energy consumption [\u003cspan citationid=\"CR3\" class=\"CitationRef\"\u003e3\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eFaulty multiplication and addition have effectively persisted in DSP design at the detriment of precision in favour of area, power, and speed advantages. Numerous studies have been done on multiplier designs to escalate energy efficiency while compromising accuracy in VLSI design. These studies used lesser least significant word lengths, extreme voltage scaling, and the employment of incorrect building blocks [\u003cspan additionalcitationids=\"CR5 CR6 CR7 CR8 CR9 CR10 CR11\" citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]-[\u003cspan citationid=\"CR12\" class=\"CitationRef\"\u003e12\u003c/span\u003e]. Latterly, the DSP design focus is on adder and multiplier circuit designs, with resource management. For the balanced performance of any design, the four essentials are energy efficiency, high computational accuracy, area efficiency, and high - speed. Moreover, in high-performance image processing applications, the design structure's stability is crucial in subsiding the error. Nevertheless, all existing IMs go astray to upgrade both design and accuracy metrics.\u003c/p\u003e \u003cp\u003eHigh-precision algorithms predominantly prospered for core arithmetic units prior to being included in processor designs. Accordingly, this paper endeavours to design two new leading one Bit Based Static Segment Inaccurate Multipliers, namely, LBSSIM0 and LBSSIM1 with and without HELC, so as to enhance the design and accuracy metrics. This adaptation approach unveils the DSP application\u0026rsquo;s efficiency, which escalates the amount of computational accuracy. The hindrances of existing multipliers are taken into consideration, and effective design of LBSSIM0 and LBSSIM1 architectures are recommended and further applied to Gaussian Filter (GF), Image Smoothing Filter (ISF), and Edge Detection Filter (EDF) applications.\u003c/p\u003e \u003cp\u003eIn the LBSSIM0 design that is being proposed, the k-bit segment may start at either the k or k-k/2 bit positions of the k-bit input bit width. The static k/2-bit segment is determined by the Leading One Bit (LOB), which can be encountered in lower or higher-order segments. The LOB block receives one segment output; further, the barrel shifter accomplishes multiplication. For the k-bit input bit width, the preferred LBSSIM1 architecture permits the m-bit segment to start at either k or k-k/2 bit positions. The LOB identifies the static k/2-bit segment, which can be spotted either in lower or higher-order segment sections. By eradicating the lower order k/2-bit segment of the input bit width and if on choosing the k/2-bit higher order segment, the HELC upgrades the accuracy. Due to this, one output segment is employed to the LOB unit, and thereby the barrel-shifter performs multiplication. This method outstrips earlier IMs in terms of design and accuracy metrics. In addition to this, analysis of accuracy metrics [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e, \u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e] is accomplished for Worst Case of Error (WCE), Error Distance (ED), Mean Relative ED (MRED), Normalized ED (NED), and Mean ED (MED) for both the existing IMs and proposed LBSSIM0 and LBSSIM1 multipliers. Further, in this paper, ISF [\u003cspan citationid=\"CR15\" class=\"CitationRef\"\u003e15\u003c/span\u003e], GF [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], and EDF [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e], combined with suggested multipliers (LBSSIM0, LBSSIM1) and the present IMs, are validated and tested with standard house test images [\u003cspan citationid=\"CR17\" class=\"CitationRef\"\u003e17\u003c/span\u003e] in order to analyze the equivalent quality metrics [\u003cspan citationid=\"CR18\" class=\"CitationRef\"\u003e18\u003c/span\u003e] in terms of PSNR and SSIM.\u003c/p\u003e \u003cp\u003eThe remaining paper is categorized as follows: The available inaccurate multiplication methods are explored in the second section. The third section bestowed the proposed LBSSIM designs. Later, the analysis of simulation results and applications are detailed in the fourth section. Eventually, the conclusion is furnished in the fifth section.\u003c/p\u003e"},{"header":"2. State-of-the-art Ims","content":"\u003cp\u003eThe latest IMs are studied in this segment. Khaing et al. presented an IM whose input bit widths are cleaved into precise and imprecise segments with limited MSBs and residue LSBs. Yet, accuracy is shrinked, depending on MSB and LSB bits [\u003cspan citationid=\"CR4\" class=\"CitationRef\"\u003e4\u003c/span\u003e]. Garg et al. came up with an IM by calculating the faulty products utilizing AND-OR logic for little LSBs [\u003cspan citationid=\"CR5\" class=\"CitationRef\"\u003e5\u003c/span\u003e]. The IM area and power are enhanced with an improvement in the input operand width. A precision configurable IM was developed by Garg et al. that incorporates the IM with EDC logic to engender damaged final products with high accuracy and low performance [\u003cspan citationid=\"CR6\" class=\"CitationRef\"\u003e6\u003c/span\u003e]. Additionally, in Dynamic-Range unbiased IM (DRIM), when the fault generated by the truncation method for shifting the MRED is pushed to zero, the LSB of the truncated input is set to one [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], and the accuracy metrics of DRIM hang on the dynamic range too. R. Jothin et al. designed an Adapted Static Segment IM (ASSIM) to escalate the precision. For this to be done, they utilized import ELC to repudiate the lower-order information of input width. However, the accuracy of ASSIM declined with increased input bit width [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]. Bharat Garg et al. have deliberated a LOB-based IM (LOBIM), which fostered a final inaccurate product that specifies j-bit from the k-bit input and hangs on LOB-logic [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]. The accuracy and design metrics of this IM depend on the chosen k-bits. Thereby, it enhanced the accuracy metrics by precisely electing m-bits centered on the LOB position. Bharat Garg et al. suggested an IM using the Rounding Approach (RAIM). Initially, the input bit width of the operand is rounded to the adjacent power of two values, and then the final IM product is realized using a few adders and barrel shifters [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]. The proposed RAIM significantly diminished the performance complexity and depleted the energy consumption but with an increase in error. Shaghayegh Vahdat et al. created error-efficient IM, which ameliorates the accuracy and design metrics, but flaws heighten as the width of the input revamps [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e]. As per the literature review, the state-of-the-art IMs imparted better design metrics but not improved accuracy metrics. Hence, the proposed LBSSIMs minimize the design metrics with the minimization of error metrics which are explained in the following section.\u003c/p\u003e"},{"header":"3. Proposed Leading One-bit Based Static Segment Inaccurate Multipliers","content":"\u003cp\u003eThis segment deliberates the two LBSSIM Architectures processes.\u003c/p\u003e\n\u003cdiv class=\"Section2\" id=\"Sec4\"\u003e\n \u003ch2\u003e3.1. Proposed LBSSIM0\u003c/h2\u003e\n \u003cp\u003eThe main objective of the proposed LBSSIM0 is to narrow the design metrics by using the static segment approach with the LOB unit, in contrast with State-of-the-art IMs. Generally, the LOB unit is detected in the leading bit position from MSB to LSB side of input operands. Using the position of this value, directly left shift the other input value; hence, the LOB unit has reduced the complexity of the proposed IM design compared to the State-of-the-art IMs. The process of the proposed k-bit LBSSIM0 multiplier is given beneath:\u003c/p\u003e\n \u003col style=\"list-style-type: lower-roman;\"\u003e\n \u003cli\u003eFor each k-bit input bit width, the m-bit lower-order or higher-order LOB segment output is taken.\u0026nbsp;\u003c/li\u003e\n \u003cli\u003eOne k/2-bit segment output is applied to the LOB unit.\u003c/li\u003e\n \u003cli\u003eThe barrel shifter performs multiplying operations for the outputs of the k/2-bit segment and the LOB unit.\u003c/li\u003e\n \u003cli\u003eBy shifting the k-bit-based LOB, position value is attained by shifting the 2k-bit incorrect product.\u003c/li\u003e\n \u003c/ol\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e illustrates the suggested k-bit LBSSIM0 architecture. Each k/2-bit input bit width segment is taken from the available two input segments. The LOB unit grabs one of the values of the segment, and the LOB unit output is specified as the LOB position. The LOB operation is extensively narrated in [\u003cspan class=\"CitationRef\"\u003e9\u003c/span\u003e]. The Mathematical expression of the LOB unit is conveyed in Eq. (1). The Gate level representation of the LOB Unit for 8-bit input operands is indicated in Fig. \u003cspan class=\"InternalRef\"\u003e2\u003c/span\u003e.\u003c/p\u003e\n \u003cp\u003e\u003cspan class=\"InlineEquation\"\u003e\u0026nbsp;\u003cspan class=\"mathinline\"\u003e\\(Y=(\\prod\\limits_{{k=i+1}}^{{\\frac{k}{2} - 2}} {\\overline {{B(k)}} } ) \\bullet B(k)\\)\u003c/span\u003e\u0026nbsp;\u003c/span\u003efor\u003cspan class=\"InlineEquation\"\u003e\u003cspan class=\"mathinline\"\u003e\\(0 \\leqslant k \\leqslant \\frac{k}{2} - 2\\)\u003c/span\u003e\u003c/span\u003e (1)\u003c/p\u003e\n \u003cp\u003eWhere \u003cem\u003eY\u003c/em\u003e\u0026thinsp;=\u0026thinsp;\u003cem\u003ek/2-bit B.\u003c/em\u003e\u003c/p\u003e\n \u003cp\u003eA barrel shifter utilizes the last k-bit multiplication wielding the k/2-bit segment and LOB value. Gate level representation of the barrel shifter is fully explicated in ref [\u003cspan class=\"CitationRef\"\u003e20\u003c/span\u003e]. By adding zeros, the multiplier k-bit output may be increased to a 2k-bit output. The multiplexer chooses W1 when two segments of the input operands are from the higher and m-bit lower segments, or vice versa. The multiplexer selects W2 when both segments are from the m-bit lower segments. The multiplexer choosesW3 when both input operand parts come from the higher ones. The circuit\u0026apos;s complexity, power, and latency are diminished in the proposed LBSSIM0.\u003c/p\u003e\n\u003c/div\u003e\n\u003cdiv class=\"Section2\" id=\"Sec5\"\u003e\n \u003ch2\u003e3.2. Proposed LBSSIM1\u003c/h2\u003e\n \u003cp\u003eThe main objective of the proposed LBSSIM1 is to shorten the design and error metrics compared to that of State-of-the-art IMs, by exploiting the static segment approach with LOB and HELC units. By incorporating the HELC unit in the proposed LBSSIM0, the errors are reduced compared to State-of-the-art IMs. Furthermore, by exercising the HELC unit, the suggested LBSSIM1 multiplier has alleviated error metrics values compared to that of LBSSIM0.\u003c/p\u003e\n \u003cp\u003eThe procedure of the proposed k-bit LBSSIM1 multiplier is given below:\u003c/p\u003e\n \u003col style=\"list-style-type: lower-roman;\"\u003e\n \u003cli\u003eFor each k-bit\u0026rsquo;s input bit width, lower or higher order LOB segments output of k/2-bit is chosen.\u003c/li\u003e\n \u003cli\u003eK/2-bit\u0026rsquo;s output of one segment is applied to the HELC unit.\u003c/li\u003e\n \u003cli\u003eThe output of HELC is applied to the LOB unit.\u003c/li\u003e\n \u003cli\u003eThe barrel shifter executes the multiplying operation on HELC and LOB output related to k/2-bit.\u003c/li\u003e\n \u003cli\u003eBy extending the k-bit LOB position value, 2k-bit\u0026nbsp;incorrect\u0026nbsp;product is figured out.\u003c/li\u003e\n \u003c/ol\u003e\n \u003cp\u003e\u003cbr\u003eThe LBSSIM multiplier designs have incremented accuracy for all the input bit width combinations by replacing the k-bit multipliers circuit with the k/2-bit multiplier for large values.\u003c/p\u003e\n \u003cp\u003eFigure \u003cspan class=\"InternalRef\"\u003e3\u003c/span\u003e depicts the preferred LBSSIM1 architecture. In this multiplier, the higher segment values which were given to the HELC unit earlier (LBSSIM0 multiplier) are now applied to the LOB unit. As a result, by adopting the HELC unit, the chosen LBSSIM1 multiplier magnified both the accuracy and design metrics.\u003c/p\u003e\n \u003cp\u003eThe main intention of the HELC unit is to escalate the accuracy of the proposed LBSSIM1 in contrast to the state-of-the-art IMs and the suggested LBSSIM0. Figure \u003cspan class=\"InternalRef\"\u003e4\u003c/span\u003e manifests the HELC architecture, and Table \u003cspan class=\"InternalRef\"\u003e1\u003c/span\u003e expounds its logic function. According to this approach, the HELC\u0026apos;s output function will be either R1 or Binary to Excess Three Code (BETC) output R1\u0026thinsp;+\u0026thinsp;3, which is totally based on the control signals.\u003c/p\u003e\u0026nbsp;\u003ctable border=\"1\" id=\"Tab1\"\u003e\n \u003ccaption language=\"En\"\u003e\n \u003cdiv class=\"CaptionNumber\"\u003eTable 1\u003c/div\u003e\n \u003cdiv class=\"CaptionContent\"\u003e\n \u003cp\u003eHELC Truth table\u003c/p\u003e\n \u003c/div\u003e\n \u003c/caption\u003e\n \u003cthead\u003e\n \u003ctr\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eCA\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eR1\u0026thinsp;\u0026lt;\u0026thinsp;2\u003csup\u003em\u003c/sup\u003e-1\u003c/p\u003e\n \u003cp\u003e(C\u0026thinsp;=\u0026thinsp;Carry Output)\u003c/p\u003e\n \u003c/th\u003e\n \u003cth align=\"left\"\u003e\n \u003cp\u003eOutput S1\u003c/p\u003e\n \u003c/th\u003e\n \u003c/tr\u003e\n \u003c/thead\u003e\n \u003ctbody\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u0026times;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eR1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e\u0026times;\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eR1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e0\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eR1\u0026thinsp;+\u0026thinsp;3\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003ctr\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003e1\u003c/p\u003e\n \u003c/td\u003e\n \u003ctd align=\"left\"\u003e\n \u003cp\u003eR1\u003c/p\u003e\n \u003c/td\u003e\n \u003c/tr\u003e\n \u003c/tbody\u003e\n \u003c/table\u003e\n \u003cp\u003e\u003c/p\u003e\n \u003cp\u003e\u003cbr\u003e\u003c/p\u003e\n\u003c/div\u003e"},{"header":"4. Comparison Of Simulation Results","content":"\u003cp\u003eThis segment projects the analysis of design metrics and subsequently compares the proposed multipliers to existing IM\u0026rsquo;s with reference to design, accuracy, and quality metrics.\u003c/p\u003e \u003cdiv id=\"Sec7\" class=\"Section2\"\u003e \u003ch2\u003e4.1 Design Metrics Analysis\u003c/h2\u003e \u003cp\u003eDesign metrics of the suggested LBSSIM0 and LBSSIM1 multipliers in a company with state-of-the-art IMs [\u003cspan additionalcitationids=\"CR8 CR9\" citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]-[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e] (DRIM, ASSIM, LOBIM, and RAIM) having input bit widths of 8-bit, 16-bit, and 32-bit are examined and are coded in Verilog HDL. Succeeding, all IMs are synthesized using Cadence RTL Compiler with 90 nm standard CMOS library. The truncation length of the DRIM design is six. The ASSIM and LOBAM truncation lengths are half of the input operand, and the type of RAIM is an unsigned RAIM.\u003c/p\u003e \u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab2\" class=\"InternalRef\"\u003e2\u003c/span\u003e bestows the design metrics of state-of-the-art IMs and proposed multipliers in terms of delay, area, energy, and power, from which it is divulged that the proposed 8-bit LBSSIM0 and LBSSIM1 slump the energy consumption compared to DRIM, ASSIM, LOBIM, and RAIM. Moreover, the proposed multipliers plunge the delay and power on an average of 28.32%, 48.23%, and 68.23%, respectively, over past 8-bit IMs [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab2\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 2\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003edesign metrics comparison of 8-bit IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"8\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eBit-Width\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eDRIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eASSIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eLOBIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eRAIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e \u003cp\u003e\u003cb\u003e8-bit\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eArea (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e\u0026micro;m\u003c/span\u003e\u003csup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e2\u003c/span\u003e\u003c/sup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e)\u003c/span\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1820\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e576\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1247\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e1461\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e175\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e176\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eDelay (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003ens\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e4.25\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e3.11\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e5.24\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e6.54\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e1.56\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e1.56\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003ePower (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003emW\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e0.09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e0.05\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e0.02\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e0.03\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e0.02\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eEnergy (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003efJ\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e382\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e155\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e104\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e588\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e468\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e312\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eThe underneath Table\u0026nbsp;\u003cspan refid=\"Tab3\" class=\"InternalRef\"\u003e3\u003c/span\u003e exhibits the design metric analysis of 16-bit proposed and current multipliers, from which it is proclaimed that the suggested multipliers dwindled energy compared to DRIM, ASSIM, LOBIM, and RAIM. Moreover, they also slackened the delay, area, and power, on an average of 28.2%, 58.12%, and 56.23%, respectively, in contrast to DRIM, ASSIM, LOBIM, and RAIM.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab3\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 3\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003edesign metrics comparison of 16-bit IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"8\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eBit-Width\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eDRIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eASSIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eLOBIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eRAIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e \u003cp\u003e\u003cb\u003e16-bit\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eArea (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e\u0026micro;m\u003c/span\u003e\u003csup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e2\u003c/span\u003e\u003c/sup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e)\u003c/span\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e3012\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e1939\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e3417\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e6739\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e478\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e479\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eDelay (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003ens\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e5.18\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e7.19\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e4.69\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e8.54\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e3.15\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e3.13\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003ePower (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003emW\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e31.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e180.1\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e190.4\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e30.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e17.33\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e17.31\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eEnergy (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003efJ\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6781\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e1294\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e892\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e1281\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e545\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e541\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eSimilarly, Table\u0026nbsp;\u003cspan refid=\"Tab4\" class=\"InternalRef\"\u003e4\u003c/span\u003e depicts the design metric analysis of 32-bit proposed and current multipliers, showing that the suggested multipliers consume less energy than DRIM, ASSIM, LOBIM, and RAIM. Furthermore, it is also exposed that LBSSIM0 and LBSSIM1 multipliers slashed the delay, area and power on an average of 24.32%, 40.5%, and 62.23% individually, compared to 32-bit IMs [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab4\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 4\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003edesign metrics comparison of 32-bit IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"8\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eBit-Width\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eDRIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eASSIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eLOBIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eRAIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\" morerows=\"3\" rowspan=\"4\"\u003e \u003cp\u003e\u003cb\u003e32-bit\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eArea (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e\u0026micro;m\u003c/span\u003e\u003csup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e2\u003c/span\u003e\u003c/sup\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003e)\u003c/span\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e5146\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e5730\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e8931\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e19865\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e1335\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e1334\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eDelay (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003ens\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e5.54\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e13.99\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e6.99\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e12.41\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e4.55\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e3.15\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003ePower (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003emW\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e82.13\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e794.36\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e631.1\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e82.4\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e44.25\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e30.06\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eEnergy (\u003c/b\u003e\u003cspan type=\"BoldItalic\" class=\"BoldItalic\" name=\"Emphasis\"\u003efJ\u003c/span\u003e\u003cb\u003e)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e45000\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e11113\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e44113\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e10225\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e2033\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e946\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eOn top of that, the design metrics were also graphically depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e, which clearly differentiates between state-of-the-art and proposed IMs. Figure\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(a) illustrates the area, Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(b) depicts the delay, Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e(c) illustrates the power, and Fig.\u0026nbsp;\u003cspan refid=\"Fig5\" class=\"InternalRef\"\u003e5\u003c/span\u003e (d) depicts the energy. From these graphs, it\u0026rsquo;s very transparent that the proposed IMs achieved a declination in design metrics compared to the state-of-the-art IMs.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003cdiv id=\"Sec8\" class=\"Section2\"\u003e \u003ch2\u003e4.2 Accuracy and Quality Metrics Analysis\u003c/h2\u003e \u003cp\u003eThis section primarily illustrates the accuracy metrics analysis of the proposed LBSSIM0 and LBSSIM1 multipliers in terms of NED, MED, MRED, ED, and WCE. Subsequently, the proposed multipliers and the state-of-the-art IMs are gauged based on the accuracy metrics in ref. [\u003cspan citationid=\"CR13\" class=\"CitationRef\"\u003e13\u003c/span\u003e, \u003cspan citationid=\"CR14\" class=\"CitationRef\"\u003e14\u003c/span\u003e]. Ultimately, analysis of quality metrics is accomplished in terms of PSNR and SSIM by amalgamating the proposed and state-of-the-art IMs in the ISF, GF, and EDF.\u003c/p\u003e \u003cdiv id=\"Sec9\" class=\"Section3\"\u003e \u003ch2\u003e4.2.1 Analysis of Accuracy Metrics\u003c/h2\u003e \u003cp\u003eThe accuracies of proposed multipliers, namely, LBSSIM0 and LBSSIM1, are estimated using accuracy metrics like MRED, NED, MED, and WCE and compared with the state-of-the-art IMs. The discussed IMs are coded in Verilog HDL, simulated with 1\u0026nbsp;million systematic input patterns, and their respective accuracy metrics are computed in MATLAB. The simulation procedure of computing the accuracy metrics is systematically expounded in [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab5\" class=\"InternalRef\"\u003e5\u003c/span\u003e itemizes the accuracy metrics for the chosen LBSSIM0, LBSSIM1 and the existing IMs of bit widths 8-bit, 16-bit, and 32-bit. The reported results illustrate that the proposed LBSSIM0 and LBSSIM1 have minimized ED in the range of 28.15% \u0026minus;\u0026thinsp;43.23%, compared to DRIM, ASSIM, LOBIM, and RAIM. Table\u0026nbsp;\u003cspan refid=\"Tab5\" class=\"InternalRef\"\u003e5\u003c/span\u003e further clarifies that, for the proposed LBSSIM0 and LBSSIM1 multipliers the values of MRED, NED, MED, and WCE are slackened in contrast to DRIM, ASSIM, LOBIM, and RAIM, lying in the range of 19.22% \u0026minus;\u0026thinsp;9.09%, 70.1% \u0026minus;\u0026thinsp;19.13%, 78.22% \u0026minus;\u0026thinsp;9.22%, and 48.21% \u0026minus;\u0026thinsp;19.1%, respectively.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab5\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 5\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eAccuracy metrics comparison of IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"8\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c8\" colnum=\"8\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eBit-Width\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eDRIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eASSIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eLOBIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eRAIM\u003c/p\u003e \u003cp\u003e[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c8\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e \u003cp\u003e8-bit\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eMRED\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e6.07E-05\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e1.02E-06\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e2.36E-05\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e5.16E-06\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e6.63E-06\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e5.37E-08\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eNED\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e0.25\u003c/p\u003e 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align=\"left\" colname=\"c8\"\u003e \u003cp\u003e342954156\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eWCE\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e53520\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e22418\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e4.29E\u0026thinsp;+\u0026thinsp;09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e3.75E\u0026thinsp;+\u0026thinsp;09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e15170\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e15170\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\" morerows=\"4\" rowspan=\"5\"\u003e \u003cp\u003e32-bit\u003c/p\u003e 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colname=\"c4\"\u003e \u003cp\u003e6.20E-04\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1.58E-04\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e0.29\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e0.22\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e0.20\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eMED\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e1.01E\u0026thinsp;+\u0026thinsp;04\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e2.66E\u0026thinsp;+\u0026thinsp;06\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e6.81E\u0026thinsp;+\u0026thinsp;05\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e1.27E\u0026thinsp;+\u0026thinsp;07\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e3.46E\u0026thinsp;+\u0026thinsp;03\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e8.34E\u0026thinsp;+\u0026thinsp;03\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eED\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e2.62E\u0026thinsp;+\u0026thinsp;09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e6.98E\u0026thinsp;+\u0026thinsp;11\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e1.78E\u0026thinsp;+\u0026thinsp;11\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e3.34E\u0026thinsp;+\u0026thinsp;12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e224708161\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e606751018\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c2\"\u003e \u003cp\u003e\u003cb\u003eWCE\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c3\"\u003e \u003cp\u003e47950\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c4\"\u003e \u003cp\u003e4.31E\u0026thinsp;+\u0026thinsp;09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c5\"\u003e \u003cp\u003e4.42E\u0026thinsp;+\u0026thinsp;09\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c6\"\u003e \u003cp\u003e4.39E\u0026thinsp;+\u0026thinsp;08\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c7\"\u003e \u003cp\u003e15138\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"left\" colname=\"c8\"\u003e \u003cp\u003e42036\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eAdditionally, the Accuracy metrics are graphically portrayed in Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e, which reveals the collation of the state-of-the-art and proposed IMs for bit width\u0026rsquo;s \u0026minus;\u0026thinsp;8-bit, 16-bit, and 32-bit. Figure\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(a) presents the NED, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(b) illustrates the MED, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(c) depicts the MRED, Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(d) presents the ED, and Fig.\u0026nbsp;\u003cspan refid=\"Fig6\" class=\"InternalRef\"\u003e6\u003c/span\u003e(e) illustrates the WCE, and from these, it\u0026rsquo;s transparent that the preferred IMs shrink the accuracy metrics compared to that of state-of-the-art IMs.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003e \u003cb\u003e4.2.2Analysis of ISF/GF/EDF Quality Metrics\u003c/b\u003e \u003c/p\u003e \u003cp\u003eIn this segment, for the purpose of quality metrics analysis of SSIM and PSNR, ISF, GF, and EDF with the proposed multipliers are simulated and tested with standard test images. In ISF, GF, and EDF, the pixel is generated by performing convolution between the sub-matrix of input image's and the standard mask [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], [\u003cspan citationid=\"CR16\" class=\"CitationRef\"\u003e16\u003c/span\u003e]. Furthermore, like other IM\u0026rsquo;s, the proposed LBSSIM0 and LBSSIM1 multipliers are also used to analyze the performance of ISF, GF, and EDF.\u003c/p\u003e \u003cp\u003eISF, GF, and EDF homogenized with the proposed 8-bit LBSSIM0, LBSSIM1 and state-of-the-art IMs are evaluated using the quality metrics. These IMs, ISF, GF, and EDF are examined and simulated using a standard house image. The extraction process of quality metrics is completely described in [\u003cspan citationid=\"CR11\" class=\"CitationRef\"\u003e11\u003c/span\u003e].\u003c/p\u003e \u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab6\" class=\"InternalRef\"\u003e6\u003c/span\u003e renders the computed quality metrics of ISF integrated with state-of-the-art and proposed IMs. The reported results conclude that ISF merged with the proposed multipliers revamp SSIM and PSNR in the limit of 4.5% \u0026minus;\u0026thinsp;7.4% and 7.9% \u0026minus;\u0026thinsp;11.2%, respectively, over the ISF combined with state-of-the-art IM\u0026rsquo;s, namely, DRIM, ASSIM, LOBIM, and RAIM.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab6\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 6\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eISF quality metrics of the IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"7\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eDRIM[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eASSIM[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eLOBIM[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eRAIM[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eSSIM\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e0.738\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e0.713\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e0.713\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e0.712\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e0.792\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.802\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003ePSNR (db)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e28.81\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e28.75\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e27.91\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e27.82\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e30.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e30.11\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eAlso, the House images of the ISF combined with state-of-the-art and proposed IMs are depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig7\" class=\"InternalRef\"\u003e7\u003c/span\u003e and present that the ISF combined with proposed multipliers give better image quality in contrast to past IMs [\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e], [\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e], [\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e], [\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e].\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab7\" class=\"InternalRef\"\u003e7\u003c/span\u003e depicts the quality metrics of GF combined with state-of-the-art and proposed IMs. The reported simulation results demonstrate that GF combined with the proposed multipliers (LBSSIM0, LBSSIM1) upgraded the PSNR and SSIM metrics and are within the limits of 4.3% \u0026minus;\u0026thinsp;6.9% and 9.9% \u0026minus;\u0026thinsp;11.34%, respectively.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab7\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 7\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eGF quality metrics of the IMs.\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"7\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eDRIM[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eASSIM[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eLOBIM[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eRAIM[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003ePSNR (db)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e27.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e27.91\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e27.26\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e27.45\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e29.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e29.14\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eSSIM\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e0.722\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e0.711\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e0.713\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e0.723\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e0.801\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.802\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003eHouse test images of GF combined with state-of-the-art and proposed multipliers are depicted in Fig.\u0026nbsp;\u003cspan refid=\"Fig8\" class=\"InternalRef\"\u003e8\u003c/span\u003e. It\u0026rsquo;s perspicuous from the images that GF combined with proposed LBSSIM0 and LBSSIM1 gives good image quality than the GF combined with the DRIM, ASSIM, LOBIM, and RAIM.\u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003cp\u003eTable\u0026nbsp;\u003cspan refid=\"Tab8\" class=\"InternalRef\"\u003e8\u003c/span\u003e projects the computed quality metric EDF, combined with state-of-the-art and proposed IMs. The reported results illustrate that, in contrast to past IMs with EDF, EDF in combination with the proposed multipliers, provided better PSNR and SSIM, lying in the limits of 16.6% \u0026minus;\u0026thinsp;17.3%, and17.9% \u0026minus;\u0026thinsp;19.7%, respectively.\u003c/p\u003e \u003cp\u003eAlso, the House test images of EDF combined with state-of-the-art and proposed IMs are pictured in Fig.\u0026nbsp;\u003cspan refid=\"Fig9\" class=\"InternalRef\"\u003e9\u003c/span\u003e. It conveys that EDF combined with proposed IM\u0026rsquo;s enhanced the image quality compared to the EDF combined with state-of-the-art IM\u0026rsquo;s like DRIM, ASSIM, LOBIM, and RAIM.\u003c/p\u003e \u003cp\u003e \u003cdiv class=\"gridtable\"\u003e\u003ctable float=\"Yes\" id=\"Tab8\" border=\"1\"\u003e \u003ccaption language=\"En\"\u003e \u003cdiv class=\"CaptionNumber\"\u003eTable 8\u003c/div\u003e \u003cdiv class=\"CaptionContent\"\u003e \u003cp\u003eEDF quality metrics of the IMs\u003c/p\u003e \u003c/div\u003e \u003c/caption\u003e \u003ccolgroup cols=\"7\"\u003e \u003cdiv align=\"left\" class=\"colspec\" colname=\"c1\" colnum=\"1\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c2\" colnum=\"2\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c3\" colnum=\"3\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c4\" colnum=\"4\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c5\" colnum=\"5\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c6\" colnum=\"6\"\u003e\u003c/div\u003e \u003cdiv align=\"char\" char=\".\" class=\"colspec\" colname=\"c7\" colnum=\"7\"\u003e\u003c/div\u003e \u003cthead\u003e \u003ctr\u003e \u003cth align=\"left\" colname=\"c1\"\u003e \u003cp\u003eMetrics\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c2\"\u003e \u003cp\u003eDRIM[\u003cspan citationid=\"CR7\" class=\"CitationRef\"\u003e7\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c3\"\u003e \u003cp\u003eASSIM[\u003cspan citationid=\"CR8\" class=\"CitationRef\"\u003e8\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c4\"\u003e \u003cp\u003eLOBIM[\u003cspan citationid=\"CR9\" class=\"CitationRef\"\u003e9\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c5\"\u003e \u003cp\u003eRAIM[\u003cspan citationid=\"CR10\" class=\"CitationRef\"\u003e10\u003c/span\u003e]\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c6\"\u003e \u003cp\u003eLBSSIM0\u003c/p\u003e \u003c/th\u003e \u003cth align=\"left\" colname=\"c7\"\u003e \u003cp\u003eLBSSIM1\u003c/p\u003e \u003c/th\u003e \u003c/tr\u003e \u003c/thead\u003e \u003ctbody\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003ePSNR (db)\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e20.13\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e20.47\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e21.22\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e20.15\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e24.12\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e24.01\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003ctr\u003e \u003ctd align=\"left\" colname=\"c1\"\u003e \u003cp\u003e\u003cb\u003eSSIM\u003c/b\u003e\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c2\"\u003e \u003cp\u003e0.412\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c3\"\u003e \u003cp\u003e0.413\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c4\"\u003e \u003cp\u003e0.421\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c5\"\u003e \u003cp\u003e0.402\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c6\"\u003e \u003cp\u003e0.513\u003c/p\u003e \u003c/td\u003e \u003ctd align=\"char\" char=\".\" colname=\"c7\"\u003e \u003cp\u003e0.513\u003c/p\u003e \u003c/td\u003e \u003c/tr\u003e \u003c/tbody\u003e \u003c/colgroup\u003e \u003c/table\u003e\u003c/div\u003e \u003c/p\u003e \u003cp\u003e \u003c/p\u003e \u003c/div\u003e \u003c/div\u003e"},{"header":"5. Conclusion","content":"\u003cp\u003eThis paper propounds two static segment IMs (LBSSIM0 and LBSSIM1) based on the LOB technique. In LBSSIM0, the barrel shifter initially executes multiplication after applying one k/2-bit of static output to the LOB unit and, later, identifies the k/2-bit static segment using the LOB position value. Thereby, the multiplexer ultimately selects the incorrect product. The multiplier LBSSIM1 performs the remaining operations, and just like LBSSIM0, it also executes a multiplier function while adding one block to represent the HELC unit. The area, latency, power, and accuracy metrics of the proposed LBSSIM0 and LBSSIM1 multipliers are better than those of state-of-the-art IMs. Eventually, the proposed LBSSIM0 and LBSSIM1 are integrated with ISF, GF, and EDF, which are tested using quality measures. The simulation findings demonstrate that when combined with the ISF, GF, and EDF, the proposed multipliers achieved refined quality metrics than the ISF, GF, and EDF mixed with state-of-the-art IMs.\u003c/p\u003e"},{"header":"Declarations","content":"\u003cp\u003e\u003cstrong\u003eData Availability Statement\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eData sharing is unconnected to this paper since no datasets were produced or examined throughout the Proposed and \u003cstrong\u003estate-of-the-art IM\u003c/strong\u003es.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eFunding\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eNo Funding\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eConflict of Interest Statement\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eI certify no actual or potential conflict of interest about this article.\u003c/p\u003e\n\u003cp\u003e\u003cstrong\u003eCompeting Interests\u003c/strong\u003e\u003c/p\u003e\n\u003cp\u003eThe authors declare that they have no known competing financial interests or personal relationships that could influence the work reported in this paper.\u003c/p\u003e"},{"header":"References","content":"\u003col\u003e\n\u003cli\u003eJ. Han and M. Orshansky (2013) \u0026quot;Approximate computing: An emerging paradigm for energy-efficient design\u0026quot;. \u003cem\u003eIn Proc. of 18\u003csup\u003eth\u003c/sup\u003e IEEE European Test Symposium (ETS)\u003c/em\u003e, IEEE European, pp. 1\u0026ndash;6.\u003c/li\u003e\n\u003cli\u003eBotella G, Garc\u0026iacute;a C, Meyer-B\u0026auml;se U (2013) Hardware implementation of machine vision systems: image and video processing\u003cem\u003e. EURASIP Journal on Advances in Signal Processing\u003c/em\u003e,152:1\u0026ndash;4.\u003c/li\u003e\n\u003cli\u003eVasudevan M, Chakrabarti C (2014) \u0026ldquo;Image processing using approximate Data path units\u0026rdquo;. In: \u003cem\u003eProc. of IEEE InternationalSympo. Circuits Sys\u003c/em\u003e, pp. 1544\u0026ndash;1547.\u003c/li\u003e\n\u003cli\u003eKyaw KY, Goh W-L, Yeo K-S (2010) \u0026ldquo;Low-power high-speed multiplier for error-tolerant application\u0026rdquo;. In: \u003cem\u003eProc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\u003c/em\u003e, pp 1\u0026ndash;4.\u003c/li\u003e\n\u003cli\u003eGarg B, Sharma G (2016) \u0026ldquo;Low power signal processing via approximate multiplier for error-resilient applications\u0026rdquo;. In: \u003cem\u003eProc. of 11\u003csup\u003eth\u003c/sup\u003e International Conference on Industrial and Information Systems (ICIIS)\u003c/em\u003e, IEEE, pp 546\u0026ndash;551.\u003c/li\u003e\n\u003cli\u003eKulkarni P, Gupta P, Ercegovac M (2011) \u0026ldquo;Trading accuracy for power with an under-designed multiplier architecture\u0026rdquo;. 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Meo (2020) Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers. \u003cem\u003eIEEE Transactions on Circuits and Systems I: Regular Papers\u003c/em\u003e 67(9):3021-3034.\u003c/li\u003e\n\u003cli\u003eGarg B, Sharma G (2016) A quality-aware energy-scalable Gaussian smoothing filter for image processing applications. \u003cem\u003eMicroprocessors Microsystems\u003c/em\u003e 45:1\u0026ndash;9.\u003c/li\u003e\n\u003cli\u003eWang Z, Bovik A, Sheikh H, Simoncelli E (2004) Image quality assessment: from error visibility to structural similarity.\u003cem\u003eIEEE Transactions on Image Processing \u003c/em\u003e13(4):600\u0026ndash;612.\u003c/li\u003e\n\u003cli\u003eVahdat S, Kamal M, Afzali-Kusha A, Pedram M (2019) TOSAM: An energy-efficient truncation-and rounding-based scalable approximate multiplier.\u003cem\u003eIEEE Transactions on Very Large Scale Integration (VLSI) Systems\u003c/em\u003e 27(5): 1161-1173.\u003c/li\u003e\n\u003cli\u003eKarthikumar .R, Allin Joe D (2017) Behavioral level simulation of Vedic multiplier for ALU. \u003cem\u003eJournal of Advanced Research in Dynamical and Control Systems\u003c/em\u003e 9(16):1231-1249.\u003c/li\u003e\n\u003c/ol\u003e"}],"fulltextSource":"","fullText":"","funders":[],"hasAdminPriorityOnWorkflow":false,"hasManuscriptDocX":true,"hasOptedInToPreprint":true,"hasPassedJournalQc":"","hasAnyPriority":false,"hideJournal":true,"highlight":"","institution":"","isAcceptedByJournal":false,"isAuthorSuppliedPdf":false,"isDeskRejected":"","isHiddenFromSearch":false,"isInQc":false,"isInWorkflow":false,"isPdf":false,"isPdfUpToDate":true,"isWithdrawnOrRetracted":false,"journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true},"keywords":"Leading One Bit, Static Segment Method, Approximate Computing, Hybrid Estimator Logic Circuit.","lastPublishedDoi":"10.21203/rs.3.rs-2212833/v1","lastPublishedDoiUrl":"https://doi.org/10.21203/rs.3.rs-2212833/v1","license":{"name":"CC BY 4.0","url":"https://creativecommons.org/licenses/by/4.0/"},"manuscriptAbstract":"\u003cp\u003eTraditionally, Image processing applications perform momentous data refinement. One of the most efficacious methods for data manipulation in multiple image processing applications is approximate computing. This mitigates the circuit complexity and thereby reinforces the power, latency, and area metrics. Furthermore, multiplication is also an essential operation in most image-processing applications. In the current scenario, numerous existing state-of-the-art multipliers employed approximation computation techniques to raise the design metrics with limited accuracy. As a consequence, this paper instigates two novel multipliers, namely, one-bit Based Static Segment Inaccurate Multipliers - LBSSIM0 and LBSSIM1, with and without a Hybrid Estimator Logic Circuit (HELC), so as to revamp the accuracy and design metrics. The HELC function is to efface the lower-order significant input bit width data and conceal the inaccurate multiplication of the proposed LBSSIM designs using the barrel shifter and the leading unit. The preferred inaccurate multipliers are simulated and synthesized using Xilinx Vivado, MATLAB, and Cadence RTL compilers for the input widths of 8-bit, 16-bit, and 32-bit. The results reveal that the recommended LBSSIMs dwindle the delay, area, energy, and power on an average of 32.13%, 65.23%, 57.12%, and 64.3%, respectively, with the state-of-the-art Inaccurate Multipliers (IMs). It is also unveiled through the simulation results that the proposed LBSSIMs reinforce the performance of accuracy metrics, namely, MRED, NED, MED, and WCE, on an average of 42.12%, 17.23%, 46.54%, and 28.24%, respectively, as opposed to the state-of-the-art IMs. Eventually, after incorporating the proposed LBSSIMs in the image processing applications, they purveyed higher Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) when collated with the state-of-the-art IMs.\u003c/p\u003e","manuscriptTitle":"Efficient Design of Static Segment Inaccurate Multiplier using Leading One-Bit Approach for Image Processing Applications","msid":"","msnumber":"","nonDraftVersions":[{"code":1,"date":"2022-11-11 15:56:54","doi":"10.21203/rs.3.rs-2212833/v1","editorialEvents":[{"type":"communityComments","content":0}],"status":"published","journal":{"display":true,"email":"[email protected]","identity":"researchsquare","isNatureJournal":false,"hasQc":true,"allowDirectSubmit":true,"externalIdentity":"","sideBox":"","snPcode":"","submissionUrl":"/submission","title":"Research Square","twitterHandle":"researchsquare","acdcEnabled":true,"dfaEnabled":false,"editorialSystem":"","reportingPortfolio":"","inReviewEnabled":false,"inReviewRevisionsEnabled":true}}],"origin":"","ownerIdentity":"5c98a376-c659-4045-922f-193cd667443b","owner":[],"postedDate":"November 11th, 2022","published":true,"recentEditorialEvents":[],"rejectedJournal":[],"revision":"","amendment":"","status":"posted","subjectAreas":[],"tags":[],"updatedAt":"2026-03-11T17:11:27+00:00","versionOfRecord":[],"versionCreatedAt":"2022-11-11 15:56:54","video":"","vorDoi":"","vorDoiUrl":"","workflowStages":[]},"version":"v1","identity":"rs-2212833","journalConfig":"researchsquare"},"__N_SSP":true},"page":"/article/[identity]/[[...version]]","query":{"redirect":"/article/rs-2212833","identity":"rs-2212833","version":["v1"]},"buildId":"_2-kVJe1T_tPrBINL-cwx","isFallback":false,"isExperimentalCompile":false,"dynamicIds":[84888],"gssp":true,"scriptLoader":[]}