{"paper_id":"36a990bf-837b-400f-b98a-c298f39ce8ba","body_text":"Low Power and Highly Stable 10T SRAM Cell Design Using Stacked and MTCMOS Techniques | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Research Article Low Power and Highly Stable 10T SRAM Cell Design Using Stacked and MTCMOS Techniques Md. Mozahidul Islam, Fariha Zaman, Md. Tawfiq Amin This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-7923985/v1 This work is licensed under a CC BY 4.0 License Status: Under Review Version 1 posted 14 You are reading this latest preprint version Abstract A comparison of three 10T SRAM designs, Conventional, Stacked and Multi-Threshold CMOS (MTCMOS) was conducted at the 90 nm technology node. This followed earlier findings that the 10T SRAM out performed the 6T, 8T and 12T designs. The 10T cell was chosen for its optimal balance of power use, stability, and performance. It achieved a higher static noise margin (SNM) and significantly lower power consumption than the 8T and 12T designs. The three variations of 10T implementations were then closely compared, revealing that the MTCMOS-based 10T SRAM cell out performed the other two. The simulation results showed that the 10T SRAM based on MTCMOS was the most stable, with a Static Noise Margin (SNM) of 379.456 mV. It also had the lowest power consumption at 13.8 μW. At the process corners, SRAM cells achieved the best average voltage and stability in FF. There was minimal degradation in FS and FF-like behaviour in SF, while the worst case occurred at SS. For leakage, the MTCMOS 10T had the lowest value, around 720 μW. Although the stacked 10T SRAM showed better read/write performance and output quality, it did not match the MTCMOS scheme in static power reduction. In general, the 10T SRAM cell based on MTCMOS is the most stable and energy-efficient option for future high-performance,low-power applications. 10T SRAM Static Noise Margin (SNM) MTCMOS Stacked SRAM Power Consumption High Performance Memory Read/Write Stability Full Text Additional Declarations No competing interests reported. Cite Share Download PDF Status: Under Review Version 1 posted Editorial decision: Revision requested 13 Feb, 2026 Reviews received at journal 29 Jan, 2026 Reviewers agreed at journal 22 Jan, 2026 Reviews received at journal 21 Jan, 2026 Reviewers agreed at journal 20 Jan, 2026 Reviewers agreed at journal 19 Jan, 2026 Reviewers agreed at journal 15 Jan, 2026 Reviews received at journal 16 Nov, 2025 Reviewers agreed at journal 01 Nov, 2025 Reviewers agreed at journal 28 Oct, 2025 Reviewers invited by journal 27 Oct, 2025 Editor assigned by journal 23 Oct, 2025 Submission checks completed at journal 23 Oct, 2025 First submitted to journal 22 Oct, 2025 You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. Also discoverable on Platform About Our Team In Review Editorial Policies Advisory Board Help Center Resources Author Services Accessibility API Access RSS feed Manage Cookie Preferences © Research Square 2026 | ISSN 2693-5015 (online) Privacy Policy Terms of Service Do Not Sell My Personal Information {\"props\":{\"pageProps\":{\"initialData\":{\"identity\":\"rs-7923985\",\"acceptedTermsAndConditions\":true,\"allowDirectSubmit\":false,\"archivedVersions\":[],\"articleType\":\"Research Article\",\"associatedPublications\":[],\"authors\":[{\"id\":533425415,\"identity\":\"9f0bdcbc-fb2b-4394-a36d-251207cc5ca5\",\"order_by\":0,\"name\":\"Md. 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This followed earlier findings that the 10T SRAM out performed the 6T, 8T and 12T designs. The 10T cell was chosen for its optimal balance of power use, stability, and performance. It achieved a higher static noise margin (SNM) and significantly lower power consumption than the 8T and 12T designs. The three variations of 10T implementations were then closely compared, revealing that the MTCMOS-based 10T SRAM cell out performed the other two. The simulation results showed that the 10T SRAM based on MTCMOS was the most stable, with a Static Noise Margin (SNM) of 379.456 mV. It also had the lowest power consumption at 13.8 μW. At the process corners, SRAM cells achieved the best average voltage and stability in FF. There was minimal degradation in FS and FF-like behaviour in SF, while the worst case occurred at SS. For leakage, the MTCMOS 10T had the lowest value, around 720 μW. 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