{"paper_id":"02eabd9b-4095-4faf-9976-4c0487d3c462","body_text":"Quantum transport for gate length scaling limit of Si NWFETs based on calibrated k·p Hamiltonian parameters | Research Square window.SnipcartSettings = { analytics: { enabled: false } }; (function() { var accessVector = localStorage.getItem('access_vector') || ''; window.dataLayer = window.dataLayer || []; if (accessVector) { window.dataLayer.push({ user: { profile: { profileInfo: { snid: accessVector } } } }); } })(); (function(w,d,s,l,i){w[l]=w[l]||[];w[l].push({'gtm.start':new Date().getTime(),event:'gtm.js'});var f=d.getElementsByTagName(s)[0],j=d.createElement(s),dl=l!='dataLayer'?'&l='+l:'';j.async=true;j.src='https://www.googletagmanager.com/gtm.js?id='+i+dl;f.parentNode.insertBefore(j,f);})(window,document,'script','dataLayer','GTM-K279D39R'); Browse Preprints In Review Journals COVID-19 Preprints AJE Video Bytes Research Tools Research Promotion AJE Professional Editing AJE Rubriq About Preprint Platform In Review Editorial Policies Our Team Advisory Board Help Center Sign In Submit a Preprint Cite Share Download PDF Article Quantum transport for gate length scaling limit of Si NWFETs based on calibrated k·p Hamiltonian parameters Zhenhua Wu, Guohui Zhan, Tongshuai Zhu, Jiaxin Yao, Kun Luo, Shengli Zhang, and 1 more This is a preprint; it has not been peer reviewed by a journal. https://doi.org/ 10.21203/rs.3.rs-3826152/v1 This work is licensed under a CC BY 4.0 License Status: Posted Version 1 posted You are reading this latest preprint version Abstract We present a comprehensive investigation of quantum transport in silicon nanowire field-effect transistors (Si NWFETs) at the scaling limit. The Si bulk $\\bm{k}\\cdot\\bm{p}$ Hamiltonian parameters are rendered invalid at smaller scales due to pronounced quantum confinement effects. Consequently, nanowire $\\bm{k}\\cdot\\bm{p}$ Hamiltonian parameters are meticulously calibrated using first-principle HSE06 band structures through the fast least square method. Based on the Non-Equilibrium Green's functon(NEGF) formalism, we systematically analyze the performance limits of \\textrm{Si} gate-all-around NWFETs under varying gate lengths. With diminishing gate lengths, quantum tunneling from source to drain intensifies, leading to a degradation in subthreshold swing. Our findings reveal that the gate length scaling limit for N-type devices surpasses that of P-type devices, and distinct gate scaling limits are elucidated for varying cross-sectional sizes, for instance, the ultimate scaling limit of a 4 nm $\\times$ 4 nm cross-section Si nanowires is approximately 10 nm. Physical sciences/Physics/Electronics, photonics and device physics Physical sciences/Materials science/Nanoscale materials/Nanowires Physical sciences/Materials science/Theory and computation/Atomistic models Full Text Additional Declarations (Not answered) Supplementary Files SupplementaryMaterials.pdf Cite Share Download PDF Status: Posted Version 1 posted You are reading this latest preprint version Research Square lets you share your work early, gain feedback from the community, and start making changes to your manuscript prior to peer review in a journal. As a division of Research Square Company, we’re committed to making research communication faster, fairer, and more useful. We do this by developing innovative software and high quality services for the global research community. Our growing team is made up of researchers and industry professionals working together to solve the most critical problems facing scientific publishing. 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